CN112803762A - Low-voltage power supply enabling control circuit, enabling module and low-voltage control chip - Google Patents
Low-voltage power supply enabling control circuit, enabling module and low-voltage control chip Download PDFInfo
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- CN112803762A CN112803762A CN202110127731.2A CN202110127731A CN112803762A CN 112803762 A CN112803762 A CN 112803762A CN 202110127731 A CN202110127731 A CN 202110127731A CN 112803762 A CN112803762 A CN 112803762A
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
- H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/36—Means for starting or stopping converters
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Abstract
The invention provides a low-voltage power supply enabling control circuit, an enabling module and a low-voltage control chip. A low voltage power supply enable control circuit comprising: the first subcircuit is connected to the EN signal input end; a second shunt circuit; a self-biasing circuit connected between the first subcircuit and the second subcircuit; and the output circuit is connected to the second subcircuit. The buck-boost control chip is ingenious in structural design, and the enable control of the buck-boost control chip under the condition of VIN low-voltage power supply is realized.
Description
Technical Field
The invention relates to the field of synchronous buck-boost control chips, in particular to a low-voltage power supply enabling control circuit, an enabling module and a low-voltage control chip.
Background
In the existing market, under the condition that the VIN voltage is lower, the buck-boost control chip can not be normally started due to the process angle and the temperature, so that the use effect of the chip is influenced.
Disclosure of Invention
The invention aims to provide a low-voltage power supply enabling control circuit, an enabling module and a low-voltage control chip.
The invention aims to solve the problem that the existing buck-boost control chip is in a low-voltage power supply state.
Compared with the prior art, the technical scheme and the beneficial effects of the invention are as follows:
a low voltage power supply enable control circuit comprising: the first subcircuit is connected to the EN signal input end; a second shunt circuit; a self-biasing circuit connected between the first subcircuit and the second subcircuit; and the output circuit is connected to the second subcircuit.
As a further improvement, the first subcircuit includes: the grid electrode of the first MOS tube is connected to the EN signal input end; the drain electrode of the second MOS tube is connected to the drain electrode of the first MOS tube, the grid electrode of the second MOS tube is connected to the drain electrode of the second MOS tube, and the source electrode of the second MOS tube is connected to the voltage input end; a grid electrode of the third MOS tube is connected to the grid electrode of the second MOS tube, and a source electrode of the third MOS tube is connected to the voltage input end; the anode of the third diode is connected to the drain electrode of the third MOS tube; and the anode of the fourth diode is connected to the cathode of the third diode, and the cathode of the fourth diode is grounded.
As a further improvement, the first sub-circuit further includes: one end of the first resistor is connected to the source electrode of the first MOS tube, and the other end of the first resistor is grounded.
As a further improvement, the second shunt circuit includes: the source electrode of the eighth MOS tube is grounded; a source electrode of the ninth MOS tube is connected to a drain electrode of the eighth MOS tube, and a gate electrode of the ninth MOS tube is connected to a gate electrode of the first MOS tube; a source electrode of the tenth MOS transistor is connected to the drain electrode of the ninth MOS transistor, and a gate electrode of the tenth MOS transistor is connected to the drain electrode of the third MOS transistor; a source electrode of the eleventh MOS transistor is connected to the voltage input end, a gate electrode of the eleventh MOS transistor is connected to a drain electrode of the eleventh MOS transistor, and a drain electrode of the eleventh MOS transistor is connected to a drain electrode of the tenth MOS transistor; a grid electrode of the twelfth MOS tube is connected to a grid electrode of the eleventh MOS tube, and a source electrode of the twelfth MOS tube is connected to the voltage input end; a thirteenth MOS tube, wherein the source electrode of the thirteenth MOS tube is grounded, and the grid electrode of the thirteenth MOS tube is connected to the drain electrode of the thirteenth MOS tube; a drain electrode of the fourteenth MOS tube is connected to a drain electrode of the thirteenth MOS tube, and a source electrode of the fourteenth MOS tube is connected to a gate electrode of the tenth MOS tube.
As a further improvement, the self-bias circuit includes: a source electrode of the fourth MOS tube is grounded, a grid electrode of the fourth MOS tube is connected to a drain electrode of the fourth MOS tube, and a grid electrode of the fourth MOS tube is connected to a grid electrode of the eighth MOS tube; a drain electrode of the fifth MOS tube is connected to a drain electrode of the fourth MOS tube, and a source electrode of the fifth MOS tube is connected to a drain electrode of the third MOS tube; one end of the second resistor is grounded; a source electrode of the sixth MOS tube is connected to the other end of the second resistor, and a grid electrode of the sixth MOS tube is connected to a grid electrode of the fourth MOS tube; the drain electrode of the seventh MOS tube is connected to the drain electrode of the sixth MOS tube, the gate electrode of the seventh MOS tube is connected to the drain electrode of the seventh MOS tube, the gate electrode of the seventh MOS tube is connected to the gate electrode of the fifth MOS tube, the source electrode of the seventh MOS tube is connected to the source electrode of the fifth MOS tube, and the gate electrode of the seventh MOS tube is connected to the gate electrode of the fourteenth MOS tube.
As a further improvement, the output circuit includes: a fifteenth MOS tube, wherein the source electrode of the fifteenth MOS tube is grounded, and the drain electrode of the fifteenth MOS tube is connected with the drain electrode of the thirteenth MOS tube; a sixth MOS transistor, a drain of which is connected to a drain of the fifth MOS transistor, and a gate of which is connected to a gate of the fifth MOS transistor; and the source electrode of the seventeenth MOS tube is connected to the source electrode of the sixteenth MOS tube, and the grid electrode of the seventeenth MOS tube is connected to the grid electrode of the sixteenth MOS tube.
As a further improvement, the power supply further comprises a third sub-circuit, wherein the third sub-circuit comprises: one end of the third resistor is connected to the EN signal input end, and the other end of the third resistor is connected to the grid electrode of the first MOS tube; the anode of the second diode is connected to the other end of the third resistor; and the anode of the first diode is connected to the cathode of the second diode, and the cathode of the first diode is grounded.
As a further improvement, the first MOS transistor, the fourth MOS transistor, the sixth MOS transistor, the eighth MOS transistor, the ninth MOS transistor, the tenth MOS transistor, the thirteenth MOS transistor, the fifteenth MOS transistor, and the seventeenth MOS transistor are all NMOS transistors; the second MOS transistor, the third MOS transistor, the fifth MOS transistor, the seventh MOS transistor, the eleventh MOS transistor, the twelfth MOS transistor, the fourteenth MOS transistor, and the sixteenth MOS transistor are all PMOS transistors.
An enabling module comprising the low-voltage power supply enabling control circuit, further comprising: the bias current output end is connected to the drain electrode of the twelfth MOS tube; a BG _ OK signal end connected to the gate of the seventeenth MOS transistor; the BG voltage end is connected to the drain electrode of the seventeenth MOS tube; and the reference voltage output end is connected to the source electrode of the seventeenth MOS tube.
A low-voltage control chip comprises the enabling module and further comprises: the first input end of the low dropout regulator is connected to the voltage input end, the second input end of the low dropout regulator is connected to the bias current output end, and the third input end of the low dropout regulator is connected to the reference voltage output end; the input end of the band-gap voltage reference module is connected to the output end of the low dropout linear regulator, and the output end of the band-gap voltage reference module is connected to the reference voltage output end; and the input ends of the other modules are connected to the output end of the band-gap voltage reference module.
The invention has the beneficial effects that: the low-voltage enabling control circuit of the enabling module adopts a combination of a first subcircuit, a second subcircuit, a self-bias circuit, an output circuit and a third subcircuit, the enabling module is driven to start working through an EN signal, the enabling module provides bias current and preliminary reference voltage for the low-dropout linear regulator, and the low-dropout linear regulator can work and provides VDD working voltage for the band-gap voltage reference module; the band-gap voltage reference module generates an accurate reference voltage after working normally and replaces the primary reference voltage of the enabling module; the buck-boost control chip is ingenious in structural design, and the enable control of the buck-boost control chip under the condition of VIN low-voltage power supply is realized.
Drawings
Fig. 1 is a schematic diagram of a low-voltage power supply enable control circuit according to an embodiment of the present invention.
Fig. 2 is a module connection diagram of a low-voltage control chip according to an embodiment of the present invention.
In the figure: 1. first subcircuit 2, second subcircuit 3, self-biasing circuit
4. Output circuit 5, third divide circuit 6 enable module
7. Low dropout linear regulator 8, band gap voltage reference module 9 and other modules
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings of the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be obtained by a person skilled in the art without any inventive step based on the embodiments of the present invention, are within the scope of the present invention. Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be obtained by a person skilled in the art without any inventive step based on the embodiments of the present invention, are within the scope of the present invention.
In the description of the present invention, the terms "first" and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implying any number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.
Referring to fig. 1, a low voltage power supply enable control circuit includes: the first subcircuit 1 is connected to an EN signal input end; a second subcircuit 2; a self-bias circuit 3, wherein the self-bias circuit 3 is connected between the first subcircuit 1 and the second subcircuit 2; and the output circuit 4 is connected to the second sub-circuit 2. The first sub-circuit 1 includes: the grid electrode of the first MOS tube M1 is connected to the EN signal input end; a second MOS transistor M2, a drain of the second MOS transistor M2 is connected to the drain of the first MOS transistor M1, a gate of the second MOS transistor M2 is connected to the drain of the second MOS transistor M2, and a source of the second MOS transistor M2 is connected to a voltage input terminal; a third MOS transistor M3, a gate of the third MOS transistor M3 is connected to the gate of the second MOS transistor M2, and a source of the third MOS transistor M3 is connected to the voltage input terminal; a third diode D3, wherein the anode of the third diode D3 is connected to the drain of the third MOS transistor M3; a fourth diode D4, wherein the anode of the fourth diode D4 is connected to the cathode of the third diode D3, and the cathode of the fourth diode D4 is grounded.
The first sub-circuit 1 further includes: one end of the first resistor R1 is connected to the source of the first MOS transistor M1, and the other end of the first resistor R1 is grounded.
The second shunt circuit 2 includes: an eighth MOS transistor M8, wherein the source of the eighth MOS transistor M8 is grounded; a ninth MOS transistor M9, wherein the source of the ninth MOS transistor M9 is connected to the drain of the eighth MOS transistor M8, and the gate of the ninth MOS transistor M9 is connected to the gate of the first MOS transistor M1; a tenth MOS transistor M10, wherein the source of the tenth MOS transistor M10 is connected to the drain of the ninth MOS transistor M9, and the gate of the tenth MOS transistor M10 is connected to the drain of the third MOS transistor M3; an eleventh MOS transistor M11, wherein a source of the eleventh MOS transistor M11 is connected to the voltage input terminal, a gate of the eleventh MOS transistor M11 is connected to a drain of the eleventh MOS transistor M11, and a drain of the eleventh MOS transistor M11 is connected to a drain of the tenth MOS transistor M10; a twelfth MOS transistor M12, the gate of the twelfth MOS transistor M12 is connected to the gate of the eleventh MOS transistor M11, and the source of the twelfth MOS transistor M12 is connected to the voltage input terminal; a thirteenth MOS transistor M13, wherein the source of the thirteenth MOS transistor M13 is grounded, and the gate of the thirteenth MOS transistor M13 is connected to the drain of the thirteenth MOS transistor M13; a fourteenth MOS transistor M14, a drain of the fourteenth MOS transistor M14 is connected to the drain of the thirteenth MOS transistor M13, and a source of the fourteenth MOS transistor M14 is connected to a gate of the tenth MOS transistor M10.
The self-bias circuit 3 includes: a fourth MOS transistor M4, in which a source of the fourth MOS transistor M4 is grounded, a gate of the fourth MOS transistor M4 is connected to a drain of the fourth MOS transistor M4, and a gate of the fourth MOS transistor M4 is connected to a gate of the eighth MOS transistor M8; a fifth MOS transistor M5, wherein the drain of the fifth MOS transistor M5 is connected to the drain of the fourth MOS transistor M4, and the source of the fifth MOS transistor M5 is connected to the drain of the third MOS transistor M3; a second resistor R2, one end of the second resistor R2 is grounded; a sixth MOS transistor M6, a source of the sixth MOS transistor M6 is connected to the other end of the second resistor R2, and a gate of the sixth MOS transistor M6 is connected to the gate of the fourth MOS transistor M4; a seventh MOS transistor M7, wherein a drain of the seventh MOS transistor M7 is connected to a drain of the sixth MOS transistor M6, a gate of the seventh MOS transistor M7 is connected to a drain of the seventh MOS transistor M7, a gate of the seventh MOS transistor M7 is connected to a gate of the fifth MOS transistor M5, a source of the seventh MOS transistor M7 is connected to a source of the fifth MOS transistor M5, and a gate of the seventh MOS transistor M7 is connected to a gate of the fourteenth MOS transistor M14.
The output circuit 4 includes: a fifteenth MOS transistor M15, in which the source of the fifteenth MOS transistor M15 is grounded, and the drain of the fifteenth MOS transistor M15 is connected to the drain of the thirteenth MOS transistor M13; a sixteenth MOS transistor M16, wherein a drain of the sixteenth MOS transistor M16 is connected to the drain of the fifteenth MOS transistor M15, and a gate of the sixteenth MOS transistor M16 is connected to the gate of the fifteenth MOS transistor M15; a seventeenth MOS transistor M17, wherein a source of the seventeenth MOS transistor M17 is connected to the source of the sixteenth MOS transistor M16, and a gate of the seventeenth MOS transistor M17 is connected to the gate of the sixteenth MOS transistor M16.
A low voltage supply enable control circuit further comprises a third sub-circuit 5, said third sub-circuit 5 comprising: one end of the third resistor R3 is connected to the EN signal input end, and the other end of the third resistor R3 is connected to the gate of the first MOS transistor M1; a second diode D2, an anode of the second diode D2 being connected to the other end of the third resistor R3; a first diode D1, the anode of the first diode D1 is connected to the cathode of the second diode D2, and the cathode of the first diode D1 is grounded.
The first MOS transistor M1, the fourth MOS transistor M4, the sixth MOS transistor M6, the eighth MOS transistor M8, the ninth MOS transistor M9, the tenth MOS transistor M10, the thirteenth MOS transistor M13, the fifteenth MOS transistor M15, and the seventeenth MOS transistor M17 are all NMOS transistors; the second MOS transistor M2, the third MOS transistor M3, the fifth MOS transistor M5, the seventh MOS transistor M7, the eleventh MOS transistor M11, the twelfth MOS transistor M12, the fourteenth MOS transistor M14, and the sixteenth MOS transistor M16 are all PMOS transistors.
Referring to fig. 1, an enabling module 6 includes the low-voltage power supply enabling control circuit, and further includes: a bias current output terminal Ibias connected to the drain of the twelfth MOS transistor M12; a BG _ OK signal terminal BG _ OK connected to the gate of the seventeenth MOS transistor M17; a BG voltage end VBG connected to the drain of the seventeenth MOS transistor M17; a reference voltage output terminal LDO _ REF connected to the source of the seventeenth MOS transistor M17.
Referring to fig. 2, a low voltage control chip includes the enable module 6, and further includes: a low dropout regulator 7, wherein a first input terminal of the low dropout regulator 7 is connected to the voltage input terminal, a second input terminal of the low dropout regulator 7 is connected to the bias current output terminal, and a third input terminal of the low dropout regulator 7 is connected to the reference voltage output terminal; the input end of the band gap voltage reference module 8 is connected to the output end of the low dropout linear regulator 7, and the output end of the band gap voltage reference module 8 is connected to the reference voltage output end; and the input end of the other module 9 is connected to the output end of the bandgap voltage reference module 8. The low-voltage control chip is a buck-boost control chip in a low-voltage power supply state.
The working principle of the low-voltage power supply enabling control circuit, the enabling module and the low-voltage control chip provided by the invention is as follows:
the EN signal is an external Enable signal, and when the EN signal is high, the Enable module 6(Enable) starts to operate, and provides a bias current and a preliminary reference voltage for the low dropout regulator 7(LDO), so that the low dropout regulator 7(LDO) can operate and provide a VDD operating voltage for the Bandgap voltage reference module 8 (Bandgap). The bandgap voltage reference generates a precise reference voltage after working normally, and replaces the preliminary reference voltage of the Enable module 6 (Enable).
EN may be as high as 40V, and in order to prevent the gate-source voltage of the first MOS transistor M1 from being too high, and to add the diode for voltage stabilization, the stabilized signal EN _ LV controls the first MOS transistor M1 and generates a bias current. The bias current is injected into the diode through the second MOS transistor M2 and the third MOS transistor M3 to form a power rail (power rail) to provide the operating voltage for the self-bias circuit 3. The current provided by the third MOS transistor M3 must be larger than the current consumed by the self-bias circuit 3 to prevent the power supply rail from being pulled low. Since EN _ LV and the power supply voltage rail serve as the turn-on voltages of the ninth MOS transistor M9 and the tenth MOS transistor M10, the current can flow through the eleventh MOS transistor M11 to the twelfth MOS transistor M12 to form Ibias, which is the bias current in fig. 2, and is input to the operational amplifier of the low dropout linear regulator 7(LDO) as the tail current.
Another function of the circuit is to generate a reference voltage required for the operation of the low dropout linear regulator 7 (LDO). The fourteenth MOS transistor M14 copies the current from the self-bias circuit 3, and injects the current into the diode formed by the thirteenth MOS transistor M13, thereby generating a voltage of about 1V. BG _ OK is an operation signal of a Bandgap voltage reference block (Bandgap). At this time, the bandgap voltage reference module 8 does not yet start to operate, so BG _ OK is low, and therefore the gate-source voltage of the thirteenth MOS transistor M13 is input to the reference voltage LDO _ REF through the sixteenth MOS transistor M16.
The low dropout linear regulator 7(LDO) can start to operate and generate a supply voltage after having a bias current and a reference voltage. After the supply voltage is generated, the bandgap voltage reference starts to operate and the BG _ OK signal goes high. At this moment, the BG _ OK signal turns off the sixteenth MOS transistor M16 and turns on the seventeenth MOS transistor M17, and VBG is the 1.2V reference voltage of the bandgap voltage reference, replacing the preliminary reference voltage of the thirteenth MOS transistor M13.
When the EN voltage drops, the chip starts to be disabled, the EN _ LV and the power supply voltage rail are both low, the ninth MOS transistor M9 and the tenth MOS transistor M10 cannot be turned on, the low dropout regulator 7(LDO) cannot obtain the bias current required by operation, the power supply to the inside of the chip is stopped, and the chip stops working.
The invention can also realize power-on and power-off under the condition that the VIN voltage is as low as 3V. At this time, the voltage of the power supply voltage rail is higher than 2V, the self-bias circuit 3 can work normally and generate reference voltage and bias current, and the low dropout regulator 7(LDO) works. At this time, the regulating tube of the low dropout regulator 7(LDO) enters the linear region, and the output VDD is slightly lower than VIN by 10mV, which is enough for the bandgap voltage reference to work.
In conclusion, the invention can successfully realize the power-on and power-off processes of the chip.
The above examples are only for illustrating the technical solutions of the present invention and not for limiting the same. It will be understood by those skilled in the art that any modifications and equivalents may be made thereto without departing from the spirit and scope of the present invention as set forth in the appended claims.
Claims (10)
1. A low voltage power supply enable control circuit, comprising:
the first subcircuit is connected to the EN signal input end;
a second shunt circuit;
a self-biasing circuit connected between the first subcircuit and the second subcircuit;
and the output circuit is connected to the second subcircuit.
2. The low voltage power supply enable control circuit of claim 1, wherein the first subcircuit comprises:
the grid electrode of the first MOS tube is connected to the EN signal input end;
the drain electrode of the second MOS tube is connected to the drain electrode of the first MOS tube, the grid electrode of the second MOS tube is connected to the drain electrode of the second MOS tube, and the source electrode of the second MOS tube is connected to the voltage input end;
a grid electrode of the third MOS tube is connected to the grid electrode of the second MOS tube, and a source electrode of the third MOS tube is connected to the voltage input end;
the anode of the third diode is connected to the drain electrode of the third MOS tube;
and the anode of the fourth diode is connected to the cathode of the third diode, and the cathode of the fourth diode is grounded.
3. The low voltage power supply enable control circuit of claim 2, wherein the first subcircuit further comprises:
one end of the first resistor is connected to the source electrode of the first MOS tube, and the other end of the first resistor is grounded.
4. A low voltage supply enable control circuit as claimed in claim 2, wherein said second subcircuit comprises:
the source electrode of the eighth MOS tube is grounded;
a source electrode of the ninth MOS tube is connected to a drain electrode of the eighth MOS tube, and a gate electrode of the ninth MOS tube is connected to a gate electrode of the first MOS tube;
a source electrode of the tenth MOS transistor is connected to the drain electrode of the ninth MOS transistor, and a gate electrode of the tenth MOS transistor is connected to the drain electrode of the third MOS transistor;
a source electrode of the eleventh MOS transistor is connected to the voltage input end, a gate electrode of the eleventh MOS transistor is connected to a drain electrode of the eleventh MOS transistor, and a drain electrode of the eleventh MOS transistor is connected to a drain electrode of the tenth MOS transistor;
a grid electrode of the twelfth MOS tube is connected to a grid electrode of the eleventh MOS tube, and a source electrode of the twelfth MOS tube is connected to the voltage input end;
a thirteenth MOS tube, wherein the source electrode of the thirteenth MOS tube is grounded, and the grid electrode of the thirteenth MOS tube is connected to the drain electrode of the thirteenth MOS tube;
a drain electrode of the fourteenth MOS tube is connected to a drain electrode of the thirteenth MOS tube, and a source electrode of the fourteenth MOS tube is connected to a gate electrode of the tenth MOS tube.
5. The low voltage power supply enable control circuit of claim 4, wherein the self-biasing circuit comprises:
a source electrode of the fourth MOS tube is grounded, a grid electrode of the fourth MOS tube is connected to a drain electrode of the fourth MOS tube, and a grid electrode of the fourth MOS tube is connected to a grid electrode of the eighth MOS tube;
a drain electrode of the fifth MOS tube is connected to a drain electrode of the fourth MOS tube, and a source electrode of the fifth MOS tube is connected to a drain electrode of the third MOS tube;
one end of the second resistor is grounded;
a source electrode of the sixth MOS tube is connected to the other end of the second resistor, and a grid electrode of the sixth MOS tube is connected to a grid electrode of the fourth MOS tube;
the drain electrode of the seventh MOS tube is connected to the drain electrode of the sixth MOS tube, the gate electrode of the seventh MOS tube is connected to the drain electrode of the seventh MOS tube, the gate electrode of the seventh MOS tube is connected to the gate electrode of the fifth MOS tube, the source electrode of the seventh MOS tube is connected to the source electrode of the fifth MOS tube, and the gate electrode of the seventh MOS tube is connected to the gate electrode of the fourteenth MOS tube.
6. The low voltage power supply enable control circuit of claim 4, wherein the output circuit comprises:
a fifteenth MOS tube, wherein the source electrode of the fifteenth MOS tube is grounded, and the drain electrode of the fifteenth MOS tube is connected with the drain electrode of the thirteenth MOS tube;
a sixth MOS transistor, a drain of which is connected to a drain of the fifth MOS transistor, and a gate of which is connected to a gate of the fifth MOS transistor;
and the source electrode of the seventeenth MOS tube is connected to the source electrode of the sixteenth MOS tube, and the grid electrode of the seventeenth MOS tube is connected to the grid electrode of the sixteenth MOS tube.
7. The low voltage power supply enable control circuit of claim 3, further comprising a third sub-circuit, wherein the third sub-circuit comprises:
one end of the third resistor is connected to the EN signal input end, and the other end of the third resistor is connected to the grid electrode of the first MOS tube;
the anode of the second diode is connected to the other end of the third resistor;
and the anode of the first diode is connected to the cathode of the second diode, and the cathode of the first diode is grounded.
8. The low-voltage power supply enabling control circuit according to claims 1 to 6, wherein the first MOS transistor, the fourth MOS transistor, the sixth MOS transistor, the eighth MOS transistor, the ninth MOS transistor, the tenth MOS transistor, the thirteenth MOS transistor, the fifteenth MOS transistor, and the seventeenth MOS transistor are all NMOS transistors; the second MOS transistor, the third MOS transistor, the fifth MOS transistor, the seventh MOS transistor, the eleventh MOS transistor, the twelfth MOS transistor, the fourteenth MOS transistor, and the sixteenth MOS transistor are all PMOS transistors.
9. An enabling module comprising a low voltage supply enable control circuit as claimed in any one of claims 1 to 8, further comprising:
the bias current output end is connected to the drain electrode of the twelfth MOS tube;
a BG _ OK signal end connected to the gate of the seventeenth MOS transistor;
the BG voltage end is connected to the drain electrode of the seventeenth MOS tube;
and the reference voltage output end is connected to the source electrode of the seventeenth MOS tube.
10. A low voltage control chip comprising an enable module according to claim 9, further comprising:
the first input end of the low dropout regulator is connected to the voltage input end, the second input end of the low dropout regulator is connected to the bias current output end, and the third input end of the low dropout regulator is connected to the reference voltage output end;
the input end of the band-gap voltage reference module is connected to the output end of the low dropout linear regulator, and the output end of the band-gap voltage reference module is connected to the reference voltage output end;
and the input ends of the other modules are connected to the output end of the band-gap voltage reference module.
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| CN112803762B CN112803762B (en) | 2024-05-07 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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