CN112802836A

CN112802836A - Integrated circuit and electrostatic discharge protection method

Info

Publication number: CN112802836A
Application number: CN201911107421.3A
Authority: CN
Inventors: 曹太和; 颜承正
Original assignee: Realtek Semiconductor Corp
Current assignee: Realtek Semiconductor Corp
Priority date: 2019-11-13
Filing date: 2019-11-13
Publication date: 2021-05-14

Abstract

An integrated circuit includes a load circuit and an electrostatic discharge protection circuit. The load circuit comprises a first input-output end and a second input-output end. The ESD protection circuit is coupled to the first and second input/output terminals. The electrostatic discharge protection circuit comprises a first protection circuit. The first protection circuit is used for conducting a first electrostatic discharge current from the first input/output end to the second input/output end. The first protection circuit includes a first, a second, a third doped region and a well. The first doped region is coupled to the first input/output terminal. The well is coupled to the first doped region. The second doped region is coupled to the well. The third doped region is coupled to the second doped region and the second input/output terminal. The first doped region and the second doped region have a first type conductivity. The well and the third doped region have a second type of conductivity. The second type of conductivity is different from the first type of conductivity.

Description

Integrated circuit and electrostatic discharge protection method

Technical Field

The present disclosure relates to an integrated circuit, and more particularly, to an integrated circuit with ESD protection.

Background

As the technology of integrated circuits is becoming more and more advanced, the spacing between devices in the integrated circuits is becoming smaller, so that the electrostatic charges accumulated in the integrated circuits due to various causes are likely to affect the surrounding devices, and the electrostatic processing function in the integrated circuits is becoming more and more critical in order to avoid the electrostatic effect.

Disclosure of Invention

One embodiment of the present disclosure relates to an integrated circuit including a load circuit and an ESD protection circuit. The load circuit comprises a first input-output end and a second input-output end. The ESD protection circuit is coupled to the first and second input/output terminals. The electrostatic discharge protection circuit comprises a first protection circuit. The first protection circuit is used for conducting a first electrostatic discharge current from the first input/output end to the second input/output end. The first protection circuit includes a first, a second, a third doped region and a well. The first doped region is coupled to the first input/output terminal. The well is coupled to the first doped region. The second doped region is coupled to the well. The third doped region is coupled to the second doped region and the second input/output terminal. The first doped region and the second doped region have a first type conductivity. The well and the third doped region have a second type of conductivity. The second type of conductivity is different from the first type of conductivity.

One embodiment of the present disclosure relates to an electrostatic discharge protection method, which includes the following operations. Conducting a first ESD current from the first input/output terminal to the second input/output terminal by the PNPN structure; and conducting a second ESD current from the first input-output terminal to the first power rail via the first FinFET diode. The PNPN structure is a fin structure.

In summary, the integrated circuit and the electrical discharge protection method provided by some embodiments of the present disclosure can increase the electrostatic discharge protection function without changing the layout area of the integrated circuit. Thus, the problem of greatly increasing the circuit area due to the addition of new functions in the integrated circuit can be avoided.

Drawings

The disclosure may be more completely understood in consideration of the following detailed description of exemplary embodiments in connection with the accompanying drawings, in which:

FIG. 1 is a schematic diagram of an integrated circuit according to some embodiments of the present disclosure;

FIG. 2 is a detailed schematic diagram of the integrated circuit shown in FIG. 1 in accordance with some embodiments of the present disclosure;

FIG. 3 is a schematic diagram of a portion of the integrated circuit shown in FIG. 1 in accordance with some embodiments of the present disclosure;

FIG. 4A is a schematic diagram of a protection circuit according to some embodiments of the present disclosure;

FIG. 4B is a schematic diagram of a protection circuit according to some embodiments of the present disclosure;

FIG. 5 is a detailed schematic diagram of an integrated circuit according to further embodiments of the present disclosure; and

fig. 6 is a flow chart of an esd protection method according to some embodiments of the disclosure.

Description of the symbols

100 … integrated circuit

110 … load circuit

110a … load circuit

110b … load circuit

120a … input/output terminal

120b … input/output terminal

345 … electrostatic discharge protection circuit

130 … protection circuit

140 … protection circuit

140a … protection circuit

140b … protection circuit

150 … protection circuit

150a … protection circuit

150b … protection circuit

160 … Power Rail

160a … Power Rail

160b … Power Rail

VDD … supply voltage

VSS … supply voltage

300 … circuit

V1 … via

V2 … via

V3 … via

1301 … doped region

1302 … well

1303 … doped region

1304 … doped region

1305 … insulating region

M1 … metal wire

M2 … metal wire

1401 … doped region

1402 … well

1403 … doped region

1405 … insulating region

600 … method

S610 … operation

S620 … operation

Detailed Description

The following embodiments are described in detail with reference to the accompanying drawings, but the embodiments are only for explaining the embodiments and not for limiting the embodiments, the description of the structural operation is not for limiting the execution sequence, and any structure obtained by recombining the elements has equivalent functions and is covered by the disclosure of the embodiments.

As used herein, coupled or connected means that two or more elements are in direct or indirect physical or electrical contact with each other, and that two or more elements are in operation or act with each other.

Refer to fig. 1. FIG. 1 is a schematic diagram of an integrated circuit 100 according to the present disclosure. As shown in FIG. 1, the integrated circuit 100 includes a load circuit 110, an ESD protection circuit 345, and a power rail 160. In some embodiments, the integrated circuit 100 has an electrostatic discharge function, which prevents electrostatic damage to the integrated circuit 100.

As shown in fig. 1, the load circuit 110 includes an input/output end 120a and an input/output end 120b, the input/output end 120a and the input/output end 120b are coupled to an esd protection circuit 345, and the esd protection circuit 345 is further coupled to the power rail 160.

In some embodiments, the load circuit 110 transmits power and/or signals through the input/output end 120a and the input/output end 120 b. In some embodiments, the power and/or signals transmitted through the input/output end 120a are the same as those transmitted through the input/output end 120 b. In other embodiments, the power and/or signals transmitted through the input/output end 120a are different from those transmitted through the input/output end 120 b.

In some embodiments, the esd protection circuit 345 is used to connect the input/

output terminals

120a and 120b of the load circuit 110 to the power rail 160. The esd protection circuit 345 is used to protect the load circuit 110 from esd. The esd protection circuit 345 includes the protection circuit 130, the protection circuit 140, and the protection circuit 150. The details of the esd protection circuit 345 will be discussed later with reference to fig. 2, fig. 3, fig. 4A, fig. 4B, fig. 5, and fig. 6.

In some embodiments, the power rail 160 is provided as a metal line for receiving a supply voltage.

Refer to fig. 2. FIG. 2 is a detailed diagram of the integrated circuit 100 shown in FIG. 1 according to some embodiments of the present disclosure. As shown in fig. 2, the integrated circuit 100 includes a load circuit 110a, a load circuit 110b, a protection circuit 130, a protection circuit 140a, a protection circuit 140b, a protection circuit 150a, a protection circuit 150b, a power rail 160a, and a power rail 160 b. The load circuit 110 includes a load circuit 110a and a load circuit 110b, the protection circuit 140 includes a protection circuit 140a and a protection circuit 140b, the protection circuit 150 includes a protection circuit 150a and a protection circuit 150b, and the power rail 160 includes a power rail 160a and a power rail 160 b.

As shown in fig. 2, the load circuit 110a includes an input/output terminal 120a, and the load circuit 110b includes an input/output terminal 120 b. The protection circuit 130 is coupled between the input/output end 120a and the input/output end 120 b. The

protection circuits

140a and 140b respectively couple the input/

output terminals

120a and 120b to the power rail 160 a. The

protection circuits

150a and 150b respectively couple the input/

output terminals

120a and 120b to the power rail 160 b.

In some embodiments, the protection circuit 130 is configured to conduct the esd current from the input/output terminal 120a to the input/output terminal 120b to protect the load circuit 110a and its nearby components from being damaged by the static electricity accumulated on the load circuit 110 a. The protection circuit 130 is also used to conduct the esd current from the input/output terminal 120b to the input/output terminal 120a to protect the load circuit 110b and its nearby components from being damaged by the static electricity accumulated on the load circuit 110 b.

In some embodiments, the protection circuit 140a and the protection circuit 150a are respectively configured to conduct the esd current from the input/output terminal 120a and the input/output terminal 120b to the power rail 160a, and the protection circuit 140b and the protection circuit 150b are respectively configured to conduct the esd current from the input/output terminal 120a and the input/output terminal 120b to the power rail 160 b.

In some embodiments, power rail 160a is configured to receive a supply voltage VDD and power rail 160b is configured to receive a supply voltage VSS. In some embodiments, the supply voltage VDD is a system high voltage and the supply voltage VSS is ground.

Refer to fig. 3. FIG. 3 is a schematic diagram of a portion of a circuit 300 of the integrated circuit 100 shown in FIG. 1 according to some embodiments of the present disclosure. As shown in fig. 3, the circuit 300 includes an input/output terminal 120a, an input/output terminal 120b, a power rail 160a, a protection circuit 130, a protection circuit 140a, and a protection circuit 150 a.

In some embodiments, the input/output end 120a and the input/output end 120b include a plurality of contacts, wherein each contact is coupled to one of the protection circuit 130, the protection circuit 140a and the protection circuit 150 a. In some embodiments, each of the contacts in the input and

output terminals

120a and 120b are shorted with each other. In fig. 2, the

protection circuits

140b and 150b couple the input/

output terminals

120a and 120b to the power rail 160b, respectively, similar to the

protection circuits

140a, 150a and 160 a. For ease of understanding, only the protection circuit 140a, the protection circuit 150a, and the power rail 160a are shown in fig. 3.

In some embodiments, the protection circuit 130 comprises a plurality of independent portions, each portion coupling one of the input/output terminals 120a to one of the input/output terminals 120 b. In some embodiments, each portion of the protection circuit 130 has directivity, as shown in fig. 3, the uppermost portion of the protection circuit 130 is used to conduct the esd current from the input/output terminal 120b to the input/output terminal 120a, and the middle portion of the protection circuit 130 is used to conduct the esd current from the input/output terminal 120a to the input/output terminal 120b, wherein the arrows in the figure indicate the conducting direction.

In some embodiments, the protection circuit 140a and the protection circuit 150a are implemented by diodes. In other words, the protection circuit 140a and the protection circuit 150a are also directional. The diode shown in FIG. 3 is for illustrative purposes only. Various types of diodes are within the scope and contemplation of the present disclosure. For example, the diode is implemented as a fin field effect diode.

Refer to fig. 4A. Fig. 4A is a schematic structural diagram of a protection circuit 130 according to some embodiments of the disclosure. As shown in fig. 4A, the protection circuit 130 includes a doped region 1301, a well 1302, a doped region 1303, a doped region 1304, an insulating region 1305, a via hole V1, a via hole V2, a metal line M1, and a metal line M2.

As shown in fig. 4A,

doped regions

1301, 1303 and an insulating region 1305 are disposed over the well 1302. An insulating region 1305 is disposed between the doped region 1301 and the doped region 1303. The doped region 1304 is disposed between the well 1302 and the doped region 1303, and the doped region 1304 is not in direct contact with the doped region 1301. The doped region 1301 is coupled to the metal line M1 through a via V1. The doped region 1303 is coupled to the metal line M2 through a via V2.

In some embodiments, the doped regions 1301, the wells 1302, the doped regions 1303 and the doped regions 1304 are semiconductors, and a current path is formed in the protection circuit 130, which sequentially passes through the metal line M1, the via hole V1, the doped regions 1301, the wells 1302, the doped regions 1304, the doped regions 1303, the via holes V2 and the metal line M2. The protection circuit 130 is coupled to the input/output terminal 120a and the input/output terminal 120b via a metal line M1 and a metal line M2.

In some embodiments,

doped regions

1301 and 1304 have a first type of conductivity and wells 1302 and doped regions 1303 have a second type of conductivity. In some embodiments, the first type conductivity is P-type and the second type conductivity is N-type, i.e., the protection circuit 130 is a PNPN structure. In some other embodiments, the first type conductivity is N-type and the second type conductivity is P-type, i.e., the protection circuit 130 is an NPNP structure.

In some embodiments, the doping concentration of the doped region 1301 is greater than that of the well 1302, and the doping concentration of the doped region 1303 is greater than that of the well 1302. In some embodiments, the doped region 1304 is formed by performing an ion implantation process on the surface of the well 1302, and the doping concentration of the doped region 1304 is greater than the doping concentrations of the doped regions 1303 and the well 1302.

In some embodiments, the protection circuit 130 is a Fin (Fin) structure, wherein the doped region 1301, the insulating region 1305 and the doped region 1303 form a Fin of the Fin structure. In some other embodiments, protection circuit 130 does not include insulation region 1305. In some embodiments, the isolation regions 1305 are formed by a Shallow Trench Isolation (STI) process. Fig. 4A shows only one fin structure, but the disclosure is not limited thereto. In some embodiments, the protection circuit 130 is composed of a plurality of fin structures, for example, each of the plurality of portions of the protection circuit 130 shown in fig. 3 is composed of one fin structure.

Refer to fig. 4B. Fig. 4B is a schematic structural diagram of the protection circuit 140 according to some embodiments of the disclosure. As shown in fig. 4B, the protection circuit 140 includes a doped region 1401, a well 1402, a doped region 1403, an insulating region 1405, a via hole V1, a via hole V3, and a metal line M1.

As shown in fig. 4B,

doped regions

1401, 1403 and insulating regions 1405 are disposed over the well 1402. An insulating region 1405 is disposed between doped region 1401 and doped region 1403. The doped region 1401 is coupled to the metal line M1 through a via V1. The doped region 1403 is coupled to the power rail 160 through the via V3.

In some embodiments, doped region 1401, well 1402, doped region 1403, insulating region 1405, via V1 and metal line M1 are similar to doped region 1301, well 1302, doped region 1303, insulating region 1305, via V1 and metal line M1 in fig. 4A. Therefore, the details thereof are not described herein.

In some embodiments, a current path is formed in the protection circuit 140, which sequentially passes through the metal line M1, the via V1, the doped region 1401, the well 1402, the doped region 103, and the via V3 to the power rail 160. The protection circuit 140 is coupled to the input/output terminal 120a via a metal line M1.

Compared to the protection circuit 130 in fig. 4A, the power rail 160 and the metal line M1 coupled to the protection circuit 140 are disposed at different heights. As shown in FIG. 4B, the via V3 is longer than the via V1.

In some embodiments, the protection circuit 140 is a fin structure, wherein the doped region 1401, the insulating region 1405 and the doped region 1403 form a fin of the fin structure. In some embodiments, protection circuit 140 is implemented as a finfet diode.

The protection circuit 150 is substantially the same as the protection circuit 140 shown in fig. 4B. Compared to the protection circuit 140 in fig. 4B, the protection circuit 150 is coupled to the input/output terminal 120B by a metal line M1. Further details are not described herein.

Refer to fig. 5. FIG. 5 is a detailed diagram of an integrated circuit 100 according to other embodiments of the disclosure. As shown in FIG. 5, the integrated circuit 100 includes an input/output terminal 120a, an input/output terminal 120b, a protection circuit 130, a protection circuit 140, a protection circuit 150, and a power rail 160.

In some embodiments, the protection circuit 130, the protection circuit 140 and the protection circuit 150 are a plurality of fin structures, which are disposed in parallel and have substantially the same area. As shown in fig. 5, the input/output terminal 120a is coupled to the input/output terminal 120b through the protection circuit 130, and is coupled to the power rail 160 through the protection circuit 140. The input/output terminal 120b is coupled to the input/output terminal 120a through the protection circuit 130, and is coupled to the power rail 160 through the protection circuit 150. The power rail 160 is disposed perpendicular to the fin structures.

In some embodiments, the protection circuit 130 and the protection circuit 140 respectively conduct the esd current from the input/output terminal 120a to the input/output terminal 120b and the power rail 160, and the protection circuit 130 and the protection circuit 150 respectively conduct the esd current from the input/output terminal 120b to the input/output terminal 120a and the power rail 160. In some embodiments, the electrostatic discharge currents flowing through the different paths are different from each other. In other embodiments, at least some of the electrostatic discharge currents flowing through the different paths are the same.

In some embodiments, the protection circuit 130 and the protection circuit 140/150 are the same structure, and in the manufacturing process, the protection circuit 130 is formed by performing an ion implantation process on the well 1402 in the protection circuit 140 and/or the protection circuit 150.

For easy understanding, the paths coupled between the input/output terminal 120a and the input/output terminal 120b are illustrated outside the fin structure (the protection circuit 130, the protection circuit 140, and the protection circuit 150) in fig. 5, but the disclosure is not limited thereto. For example, in some embodiments, the paths coupling the input/

output terminals

120a and 120b to each other do not cover additional areas outside the

protection circuits

130, 140 and 150.

In some implementations, the ESD protection circuit disposed between the two output terminals uses extra layout area, thereby increasing the area of the integrated circuit. In contrast to the above, the protection circuit 130 is formed by adding an ion implantation process to the protection circuit 140/150, and additional devices occupy the original layout area, so the area of the integrated circuit is not increased.

Refer to fig. 6. Fig. 6 is a flow chart of an esd protection method 600 according to some embodiments of the present disclosure. The esd protection method 600 includes operations S610 and S620.

In operation S610, an electrostatic discharge current is conducted from the input and

output terminals

120a and 120 b. By using the PNPN fin structure as the protection circuit 130, the electrostatic charge accumulated on the input/output terminal 120a of the load circuit 110 is conducted to the input/output terminal 120b to protect the input/output terminal 120a and the devices nearby from electrostatic damage.

In some embodiments, the esd current is also conducted from the input/output terminal 120b to the input/output terminal 120a in operation S610. The operation and function of the device are similar to those of the device for conducting ESD current from the input/output terminal 120a to the input/output terminal 120 b. And will not be described in detail herein.

In operation S620, an esd current is conducted from the input/output terminal 120a to the power rail 160. By using a plurality of finfet diodes as the protection circuit 140 and the protection circuit 150, the electrostatic charges accumulated on the input/output terminal 120a of the load circuit 110 are conducted to the power rail 160 to protect the input/output terminal 120a and the devices nearby from electrostatic damage.

In some embodiments, conducting the accumulated electrostatic charge to power rail 160 includes conducting electrostatic discharge current from input/output 120a to power rail 160a and power rail 160b, respectively, by different finfets.

In some embodiments, the esd current is also conducted from the input/output terminal 120b to the power rail 160 in operation S620. It operates similarly to a function to conduct esd current from the i/o terminal 120a to the power rail 160. And will not be described in detail herein.

The figures include exemplary operations, but the operations are not limited to the order shown. Operations may be added, substituted, changed in order, and/or omitted as appropriate, according to the considerations and scope of embodiments of the present disclosure.

Although embodiments of the present disclosure have been described above, it should be understood that they may be embodied in many different forms and that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the embodiments of the disclosure.

Claims

1. An integrated circuit, comprising:

a load circuit including a first input/output terminal and a second input/output terminal; and

an ESD protection circuit coupled to the first input/output terminal and the second input/output terminal, wherein the ESD protection circuit comprises a first protection circuit,

wherein the first protection circuit is used for conducting a first electrostatic discharge current from the first input/output terminal to the second input/output terminal, and the first protection circuit comprises:

a first doped region coupled to the first input/output terminal, wherein the first doped region has a first type conductivity;

a well coupled to the first doped region, wherein the well has a second type of conductivity, wherein the second type of conductivity is different from the first type of conductivity;

a second doped region coupled to the well, wherein the second doped region has the first type conductivity; and

a third doped region coupled to the second doped region and the second input/output terminal, wherein the third doped region has the second type conductivity.

2. The integrated circuit of claim 1, further comprising:

a power rail coupled to the ESD protection circuit,

wherein the ESD protection circuit further comprises:

a second protection circuit for conducting a second ESD current from the first input/output terminal to the power rail; and

a third protection circuit for conducting a third ESD current from the second I/O terminal to the power rail.

3. The integrated circuit of claim 2, wherein the ESD protection circuit comprises a plurality of fin structures, and the first protection circuit, the second protection circuit, and the third protection circuit comprise different three fin structures of the fin structures.

4. The integrated circuit of claim 2, wherein the second protection circuit and the third protection circuit are FinFETs.

5. The integrated circuit of claim 1, wherein the first type of conductivity is P-type and the second type of conductivity is N-type.

6. The integrated circuit of claim 1, wherein a doping concentration of the first doped region is greater than a doping concentration of the well, a doping concentration of the third doped region is greater than the doping concentration of the well, and a doping concentration of the second doped region is greater than the doping concentration of the third doped region.

7. The integrated circuit of claim 1, wherein the second doped region is formed by performing an ion implantation on a surface of the well.

8. The integrated circuit of claim 1, further comprising:

a first power rail coupled to the ESD protection circuit; and

a second power rail coupled to the ESD protection circuit,

wherein the ESD protection circuit further comprises:

a second protection circuit for conducting a second ESD current from the first I/O terminal to the first power rail; and

a third protection circuit for conducting a third ESD current from the first I/O terminal to the second power rail.

9. The integrated circuit of claim 8, wherein the first protection circuit, the second protection circuit, and the third protection circuit are respectively formed by three different fin structures of a plurality of fin structures, wherein the fin structures are disposed perpendicular to the first power rail and the fin structures are disposed perpendicular to the second power rail.

10. An electrostatic discharge protection method, comprising:

conducting a first ESD current from a first input/output terminal to a second input/output terminal by a PNPN structure; and

conducting a second ESD current from the first input/output terminal to a first power rail by a first FinFET diode,

wherein the PNPN structure is a fin structure.