CN112800385A - Data processing method, device, terminal equipment and storage medium - Google Patents
Data processing method, device, terminal equipment and storage medium Download PDFInfo
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Abstract
The invention discloses a data processing method, which is used for terminal equipment, wherein the terminal equipment comprises an FPGA (field programmable gate array) with a reconfigurable area; the data processing method comprises the following steps: receiving first target data; determining a transform length of a fast Fourier transform of the first target data based on the first target data; reconstructing the reconfigurable area by using the fast Fourier transform corresponding to the transform length to obtain a target operation area; and in the target operation area, performing fast Fourier transform on the first target data to obtain first result data. The invention also discloses a data processing device, terminal equipment and a computer readable storage medium. By using the data processing method of the invention, the technical effect of reducing the power consumption of the terminal equipment is achieved.
Description
Technical Field
The present invention relates to the field of data processing technologies, and in particular, to a data processing method, an apparatus, a terminal device, and a computer-readable storage medium.
Background
Fast Fourier Transform (FFT) is widely used in the fields of signal processing, image processing, and data compression. Due to different application scenarios and application conditions, the required FFT length is different, for example, 64-point FFT, 1024-point FFT, or 2048-point FFT may be required.
The related art center discloses a data processing method, which is used for terminal equipment, wherein the terminal equipment is provided with an FPGA (field programmable gate array), and FFT (fast Fourier transform) operation is carried out by utilizing the FPGA to obtain result data.
However, with the existing data processing method, the power consumption of the terminal device is high.
Disclosure of Invention
The invention mainly aims to provide a data processing method, a data processing device, terminal equipment and a computer readable storage medium, and aims to solve the technical problem that the power consumption of the terminal equipment is higher when the existing data processing method is adopted in the prior art.
In order to achieve the above object, the present invention provides a data processing method for a terminal device, wherein the terminal device includes an FPGA having a reconfigurable area; the data processing method comprises the following steps:
receiving first target data;
determining a transform length of a fast Fourier transform of the first target data;
reconstructing the reconfigurable area by using the fast Fourier transform corresponding to the transform length to obtain a target operation area;
and in the target operation area, performing fast Fourier transform on the first target data to obtain first result data.
Optionally, before the step of reconstructing the reconfigurable region by using the fast fourier transform corresponding to the transform length to obtain the target operation region, the method further includes:
determining an operation architecture of fast Fourier transform corresponding to the first target data;
the step of reconstructing the reconfigurable area by using the fast Fourier transform corresponding to the transform length to obtain the target operation area comprises the following steps:
and reconstructing the reconfigurable region by using the transformation length and the fast Fourier transform corresponding to the operation framework to obtain a target operation region.
Optionally, before the step of reconstructing the reconfigurable region by using the transform length and the fast fourier transform corresponding to the operation architecture to obtain the target operation region, the method further includes:
determining a butterfly algorithm of fast Fourier transform corresponding to the first target data;
the step of reconstructing the reconfigurable area by using the transform length and the fast fourier transform corresponding to the operation architecture to obtain the target operation area comprises the following steps:
and reconstructing the reconfigurable region by using the transformation length, the operation framework and the fast Fourier transform corresponding to the butterfly algorithm to obtain a target operation region.
Optionally, before the step of reconstructing the reconfigurable region by using the transform length, the operation architecture, and the fast fourier transform corresponding to the butterfly algorithm to obtain the target operation region, the method further includes:
judging whether the reconfigurable area is in an idle state or not;
the step of reconstructing the reconfigurable region by using the transform length, the operation framework and the fast Fourier transform corresponding to the butterfly algorithm to obtain the target operation region comprises the following steps:
and when the reconfigurable area is in an idle state, reconstructing the reconfigurable area by using the transformation length, the operation framework and the fast Fourier transform corresponding to the butterfly algorithm to obtain a target operation area.
Optionally, the terminal device further includes a processor; after the step of determining whether the reconfigurable area is in an idle state, the method further includes:
and when the reconfigurable area is not in an idle state, performing fast Fourier transform on the first target data in the processor to obtain second result data.
Optionally, after the step of performing fast fourier transform on the first target data in the target operation region to obtain first result data, the method further includes:
when second target data are received, obtaining a target reconstruction algorithm based on the second target data;
reconstructing the target operation area by using the target reconstruction algorithm to obtain a target reconstruction area;
and processing the second target data in the target reconstruction region to obtain third result data.
Optionally, the operation architecture is one of a serial architecture, a parallel pipeline architecture and a hybrid architecture; the butterfly algorithm is one of Radix-2 and Radix-4.
In addition, in order to achieve the above object, the present invention further provides a data processing apparatus for a terminal device, the terminal device including an FPGA having a reconfigurable region; the device comprises:
the receiving module is used for receiving first target data;
a determining module for determining a transform length of a fast Fourier transform of the first target data;
the reconstruction module is used for reconstructing the reconfigurable area by utilizing the fast Fourier transform corresponding to the transform length to obtain a target operation area;
and the obtaining module is used for performing fast Fourier transform on the first target data in the target operation area to obtain first result data.
In addition, to achieve the above object, the present invention further provides a terminal device, including: an FPGA having a reconfigurable area, a memory, a processor, and a data processing program stored on the memory and running on the processor, the data processing program when executed by the processor implementing the steps of the data processing method as claimed in any one of the above.
Furthermore, to achieve the above object, the present invention also proposes a computer-readable storage medium having stored thereon a data processing program which, when executed by a processor, implements the steps of the data processing method as described in any one of the above.
The technical scheme of the invention provides a data processing method which is used for terminal equipment, wherein the terminal equipment comprises an FPGA with a reconfigurable area; the data processing method comprises the following steps: receiving first target data; determining a transform length of a fast Fourier transform of the first target data; reconstructing the reconfigurable area by using the fast Fourier transform corresponding to the transform length to obtain a target operation area; and in the target operation area, performing fast Fourier transform on the first target data to obtain first result data. Because an FPGA in an existing terminal device has a plurality of operation regions (each operation region corresponds to a fast fourier transform of a transform length) or an operation region (the operation region integrates fast fourier transforms of all transform lengths) in order to adapt to fast fourier transform operations of different transform lengths, when the terminal device performs data processing, if the FPGA has a plurality of operation regions, the plurality of operation regions all need power supply, and if the FPGA has one operation region, because the operation region needs to support all transform lengths at the same time, the operation region needs extra power consumption and the power consumption is also high; the FPGA of the terminal equipment only needs to set a reconfigurable area, and the reconfigurable area is reconfigured based on the transformation length of the target data so as to obtain a target operation area, wherein the target area only comprises a fast Fourier transform with the transformation length, and the fast Fourier transform is carried out on the first target data in the target operation area; compared with the existing FPGA with a plurality of operation areas, the terminal equipment only needs to supply power to one operation area included by the FPGA, and the power consumption of the terminal equipment is low; meanwhile, compared with an operation area (the operation area integrates the fast Fourier transform of all transform lengths) of the existing FPGA, the target operation area is only configured for the fast Fourier transform of one transform length, and the power consumption of the terminal equipment is low, so that the technical effect of reducing the power consumption of the terminal equipment is achieved by using the data processing method provided by the invention.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the structures shown in the drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a terminal device in a hardware operating environment according to an embodiment of the present invention;
FIG. 2 is a flowchart illustrating a data processing method according to a first embodiment of the present invention;
FIG. 3 is a block diagram of a data processing apparatus according to a first embodiment of the present invention.
The implementation, functional features and advantages of the objects of the present invention will be further explained with reference to the accompanying drawings.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the related art, the terminal device is installed with an FFT operation program, and the FFT operation program can flexibly configure the FFT change length, the operation architecture, the butterfly algorithm, and the like, but the FFT operation is computation-intensive operation, and when the FFT operation program is used for data processing, a processor needs to have a higher operation speed, and meanwhile, the FFT operation program is used for data processing, and the FFT occupies a large amount of processor resources.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a terminal device in a hardware operating environment according to an embodiment of the present invention.
The terminal device may be a User Equipment (UE) such as a Mobile phone, a smart phone, a laptop, a digital broadcast receiver, a Personal Digital Assistant (PDA), a tablet computer (PAD), a handheld device, a vehicle mounted device, a wearable device, a computing device or other processing device connected to a wireless modem, a Mobile Station (MS), etc. The terminal device may be referred to as a user terminal, a portable terminal, a desktop terminal, etc.
In general, a terminal device includes: at least one processor 301, a memory 302 and a data processing program stored on said memory and executable on said processor, said data processing program being configured to implement the steps of the data processing method as described before. The terminal device further comprises an FPGA307 having a reconfigurable region, wherein the FPGA307 may further comprise other reconfigurable regions or non-reconfigurable regions, which are respectively used for implementing different functions and different operations.
The processor 301 may include one or more processing cores, such as a 4-core processor, an 8-core processor, and so on. The processor 301 may be implemented in at least one hardware form of a DSP (Digital Signal Processing), an FPGA (Field-Programmable Gate Array), and a PLA (Programmable Logic Array). The processor 301 may also include a main processor and a coprocessor, where the main processor is a processor for processing data in an awake state, and is also called a Central Processing Unit (CPU); a coprocessor is a low power processor for processing data in a standby state. In some embodiments, the processor 301 may be integrated with a GPU (Graphics Processing Unit), which is responsible for rendering and drawing the content required to be displayed on the display screen. Processor 301 may also include an AI (Artificial Intelligence) processor for processing relevant data processing method operations such that the data processing method model may be trained autonomously for learning, improving efficiency and accuracy.
In some embodiments, the terminal may further include: a communication interface 303 and at least one peripheral device. The processor 301, the memory 302 and the communication interface 303 may be connected by a bus or signal lines. Various peripheral devices may be connected to communication interface 303 via a bus, signal line, or circuit board. Specifically, the peripheral device includes: at least one of radio frequency circuitry 304, a display screen 305, and a power source 306.
The communication interface 303 may be used to connect at least one peripheral device related to I/O (Input/Output) to the processor 301 and the memory 302. In some embodiments, processor 301, memory 302, and communication interface 303 are integrated on the same chip or circuit board; in some other embodiments, any one or two of the processor 301, the memory 302 and the communication interface 303 may be implemented on a single chip or circuit board, which is not limited in this embodiment.
The Radio Frequency circuit 304 is used for receiving and transmitting RF (Radio Frequency) signals, also called electromagnetic signals. The radio frequency circuitry 304 communicates with communication networks and other communication devices via electromagnetic signals. The rf circuit 304 converts an electrical signal into an electromagnetic signal to transmit, or converts a received electromagnetic signal into an electrical signal. Optionally, the radio frequency circuit 304 comprises: an antenna system, an RF transceiver, one or more amplifiers, a tuner, an oscillator, a digital signal processor, a codec chipset, a subscriber identity module card, and so forth. The radio frequency circuitry 304 may communicate with other terminals via at least one wireless communication protocol. The wireless communication protocols include, but are not limited to: metropolitan area networks, various generation mobile communication networks (2G, 3G, 4G, and 5G), Wireless local area networks, and/or WiFi (Wireless Fidelity) networks. In some embodiments, the rf circuit 304 may further include NFC (Near Field Communication) related circuits, which are not limited in this application.
The display screen 305 is used to display a UI (User Interface). The UI may include graphics, text, icons, video, and any combination thereof. When the display screen 305 is a touch display screen, the display screen 305 also has the ability to capture touch signals on or over the surface of the display screen 305. The touch signal may be input to the processor 301 as a control signal for processing. At this point, the display screen 305 may also be used to provide virtual buttons and/or a virtual keyboard, also referred to as soft buttons and/or a soft keyboard. In some embodiments, the display screen 305 may be one, the front panel of the electronic device; in other embodiments, the display screens 305 may be at least two, respectively disposed on different surfaces of the electronic device or in a folded design; in still other embodiments, the display screen 305 may be a flexible display screen disposed on a curved surface or a folded surface of the electronic device. Even further, the display screen 305 may be arranged in a non-rectangular irregular figure, i.e. a shaped screen. The Display screen 305 may be made of LCD (liquid crystal Display), OLED (Organic Light-Emitting Diode), and the like.
The power supply 306 is used to power various components in the electronic device. The power source 306 may be alternating current, direct current, disposable or rechargeable. When the power source 306 includes a rechargeable battery, the rechargeable battery may support wired or wireless charging. The rechargeable battery may also be used to support fast charge technology.
Those skilled in the art will appreciate that the configuration shown in fig. 1 does not constitute a limitation of the terminal device and may include more or fewer components than those shown, or some components may be combined, or a different arrangement of components.
Furthermore, an embodiment of the present invention further provides a computer-readable storage medium, on which a data processing program is stored, and the data processing program, when executed by a processor, implements the steps of the data processing method as described above. Therefore, a detailed description thereof will be omitted. In addition, the beneficial effects of the same method are not described in detail. For technical details not disclosed in embodiments of the computer-readable storage medium referred to in the present application, reference is made to the description of embodiments of the method of the present application. Determining by way of example, the program instructions may be deployed to be executed on one terminal device, or on multiple terminal devices located at one site, or distributed across multiple sites and interconnected by a communication network.
It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by a computer program, which can be stored in a computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. The computer-readable storage medium may be a magnetic disk, an optical disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), or the like.
Based on the above hardware structure, an embodiment of the data processing method of the present invention is provided.
Referring to fig. 2, fig. 2 is a schematic flowchart of a first embodiment of a data processing method according to the present invention, where the method is used for a terminal device, and the terminal device includes an FPGA with a reconfigurable area; the method comprises the following steps:
step S11: first target data is received.
It should be noted that the main execution unit of the present invention is a terminal device, and the structure of the terminal device refers to the above description, which is not described herein again. The first target data may be sent by the user, may also be sent by other electronic devices connected to the terminal device, and may also be sent by other programs of the terminal device, which is not limited in the present invention. Generally, a terminal device performs fast fourier transform (hereinafter, referred to as FFT) on original data (e.g., an original signal, an original image, data to be compressed, etc.) to obtain result data after the original data is processed, generally, a data flow may be a data source, the original data, intermediate data (data subjected to fast fourier transform), the result data, subsequent processing data, etc., the data processing of the present invention refers to a fast fourier transform portion corresponding to the intermediate data, and generally, the obtained first target data is the original data to be subjected to fast fourier transform.
When the first target data is subjected to FIR (Finite Impulse Response) filtering, the data processing method of the present invention may be referred to, that is, the FFT may be replaced with the FIR, and another method may be used to perform adaptive adjustment.
Step S12: determining a transform length of a fast Fourier transform of the first target data.
It should be noted that the transform length of the fast fourier transform may include 64 points, 128 points, 512 points, 1024 points, 2048 points, 4096 points, and the like, and different fourier transform lengths correspond to different fast fourier transforms, so that the transform length of the fast fourier transform corresponding to the first target data needs to be determined.
Step S13: and reconstructing the reconfigurable area by using the fast Fourier transform corresponding to the transform length to obtain a target operation area.
In this case, the reconfigurable area needs to be reconfigured to obtain the target operation area, and the target operation area is reconfigured by the fast fourier transform corresponding to the transform length, so that the target operation area can process the first target data.
Further, before step S13, the method further includes: determining an operation architecture of fast Fourier transform corresponding to the first target data; accordingly, step S13 includes: and reconstructing the reconfigurable region by using the transformation length and the fast Fourier transform corresponding to the operation framework to obtain a target operation region.
It should be noted that, the FFT has different operation architectures, and the corresponding FFT has different values, and the corresponding FFT needs to be determined according to the operation architecture and the transform length, where the operation architecture of the FFT may include a serial architecture, a parallel pipeline architecture, or a hybrid architecture (a combination form of a partial serial architecture and a partial parallel pipeline architecture), and in specific application, only one operation architecture needs to be determined, that is, one of three is selected, that is, the FFT at this time needs two parameters to be determined: operation architecture and transform length.
Further, before step S13, the method further includes: determining a butterfly algorithm of fast Fourier transform corresponding to the first target data; accordingly, step S13 includes: and reconstructing the reconfigurable region by using the transformation length, the operation framework and the fast Fourier transform corresponding to the butterfly algorithm to obtain a target operation region.
It should be noted that, butterfly algorithms of FFT operations are different, corresponding FFTs are different, a butterfly algorithm of fast fourier transform corresponding to first target data needs to be determined according to the first target data, and the reconfigurable region of the FPGA is reconfigured by using the transform length, the operation architecture, and the fast fourier transform corresponding to the butterfly algorithm together, where the butterfly algorithm includes Radix-2 and Radix-4, and in specific application, only one butterfly algorithm needs to be determined, that is, the FFT at this time needs three parameters to determine: transform length, arithmetic architecture and butterfly algorithm.
For example, if the conversion length corresponding to the first target data is 64 points, the operation architecture is a serial architecture, and the butterfly algorithm is Radix-4, the reconfigurable area of the FPGA is reconfigured by using the 64 points, the serial architecture and the type-a FFT corresponding to Radix-4 to obtain a target operation area; if the conversion length corresponding to the first target data is 2048 points, the operation architecture is a hybrid architecture, and the butterfly algorithm is Radix-2, the reconfigurable area of the FPGA is reconfigured by using the 2048 points, the hybrid architecture and the B-type FFT corresponding to Radix-2, so as to obtain the target operation area.
Therefore, various functions of the FFT corresponding to the combination of various transform lengths, various operation architectures and various butterfly algorithms can be realized only by one reconstruction region, the manufacturing cost and the power consumption cost of the FPGA are reduced, and meanwhile, the flexibility is high.
Further, before the step of reconstructing the reconfigurable region by using the transform length, the operation architecture and the fast fourier transform corresponding to the butterfly algorithm to obtain the target operation region, the method further includes: judging whether the reconfigurable area is in an idle state or not; correspondingly, the step of reconstructing the reconfigurable region by using the transform length, the operation architecture and the fast fourier transform corresponding to the butterfly algorithm to obtain the target operation region includes: and when the reconfigurable area is in an idle state, reconstructing the reconfigurable area by using the transformation length, the operation framework and the fast Fourier transform corresponding to the butterfly algorithm to obtain a target operation area.
When the reconfigurable area is in an idle state, the reconfigurable area is reconfigured, adverse effects on the operation or data processing of terminal equipment cannot be caused, and at the moment, the reconfigurable area is reconfigured by utilizing the transformation length, the operation framework and the fast Fourier transformation corresponding to the butterfly algorithm to obtain a target operation area.
Step S14: and in the target operation area, performing fast Fourier transform on the first target data to obtain first result data.
After the target operation area is obtained, corresponding fast fourier transform may be performed on the first target data to obtain first result data.
The technical scheme of the embodiment provides a data processing method, which is used for terminal equipment, wherein the terminal equipment comprises an FPGA with a reconfigurable area; the data processing method comprises the following steps: receiving first target data; determining a transform length of a fast Fourier transform of the first target data; reconstructing the reconfigurable area by using the fast Fourier transform corresponding to the transform length to obtain a target operation area; and in the target operation area, performing fast Fourier transform on the first target data to obtain first result data. Because an FPGA in an existing terminal device has a plurality of operation regions (each operation region corresponds to a fast fourier transform of a transform length) or an operation region (the operation region integrates fast fourier transforms of all transform lengths) in order to adapt to fast fourier transform operations of different transform lengths, when the terminal device performs data processing, if the FPGA has a plurality of operation regions, the plurality of operation regions all need power supply, and if the FPGA has one operation region, because the operation region needs to support all transform lengths at the same time, the operation region needs extra power consumption and the power consumption is also high; the FPGA of the terminal equipment only needs to set a reconfigurable area, and the reconfigurable area is reconfigured based on the transformation length of the target data so as to obtain a target operation area, wherein the target area only comprises a fast Fourier transform with the transformation length, and the fast Fourier transform is carried out on the first target data in the target operation area; compared with the existing FPGA with a plurality of operation areas, the terminal equipment only needs to supply power to one operation area included by the FPGA, and the power consumption of the terminal equipment is low; meanwhile, compared with an operation area (the operation area integrates the fast Fourier transform of all transform lengths) of the existing FPGA, the target operation area is only configured for the fast Fourier transform of one transform length, and the power consumption of the terminal equipment is low, so that the technical effect of reducing the power consumption of the terminal equipment is achieved by using the data processing method provided by the invention.
Meanwhile, the consumed processor resource is avoided when the processor utilizes the FFT operation program to carry out FFT operation, so that the processor load of the terminal equipment is reduced, and the processor running speed of the terminal equipment is increased.
Further, the terminal device further comprises a processor; after the step of determining whether the reconfigurable area is in an idle state, the method further includes: and when the reconfigurable area is not in an idle state, performing fast Fourier transform on the first target data in the processor to obtain second result data.
Generally, the terminal device is installed with an FFT operation program, and when the FFT operation program is executed by the processor, FFT operations of different transform lengths, different operation architectures and different butterfly algorithms can be performed, that is, the FFT operation program can flexibly configure the transform lengths, the operation architectures and the butterfly algorithms. When the reconfigurable area is not in an idle state, that is, the reconfigurable area is being used for processing other matters, and if the reconfigurable area is reconfigured, adverse effects may be generated on the operation or data processing of the terminal device, at this time, the reconfigurable area cannot be reconfigured, and the processor needs to configure a corresponding transform length, an operation architecture and a butterfly algorithm by using an FFT operation program, and perform FFT operation by using the configured FFT operation program to obtain second result data.
The terminal equipment has better flexibility, can perform FFT operation through the FPGA, can also perform FFT operation through the processor, and improves user experience.
Further, after step S14, the method further includes: when second target data are received, obtaining a target reconstruction algorithm based on the second target data; reconstructing the target operation area by using the target reconstruction algorithm to obtain a target reconstruction area; and processing the second target data in the target reconstruction region to obtain third result data.
It should be noted that, when obtaining the second target data, the target reconstruction algorithm corresponding to the second target data may be an FFT or other types of algorithms, and generally, the algorithm corresponding to the second target data in the embodiment of the present invention is a non-FFT, and at this time, the target operation region (obtained by reconstructing the reconfigurable region using the FFT) needs to be reconstructed again by using the target reconstruction algorithm corresponding to the second target data, so as to obtain the target reconstruction region, so that the second target data is processed in the target reconstruction region, and the third result data is obtained.
The reconfigurable area in the FPGA of the terminal equipment can be reconfigured by using a non-FFT algorithm to obtain a new target reconfigurable area so as to perform other types of data processing, and the flexibility of the terminal equipment is better.
Referring to fig. 3, fig. 3 is a block diagram of a first embodiment of the data processing apparatus according to the present invention, the apparatus including:
a receiving module 10, configured to receive first target data;
a determining module 20, configured to determine a transform length of a fast fourier transform of the first target data;
the reconstruction module 30 is configured to reconstruct the reconfigurable region by using fast fourier transform corresponding to the transform length to obtain a target operation region;
an obtaining module 40, configured to perform fast fourier transform on the first target data in the target operation region to obtain first result data.
The above description is only an alternative embodiment of the present invention, and not intended to limit the scope of the present invention, and all modifications and equivalents of the present invention, which are made by the contents of the present specification and the accompanying drawings, or directly/indirectly applied to other related technical fields, are included in the scope of the present invention.
Claims (10)
1. The data processing method is characterized by being used for terminal equipment, wherein the terminal equipment comprises an FPGA with a reconfigurable area; the data processing method comprises the following steps:
receiving first target data;
determining a transform length of a fast Fourier transform of the first target data;
reconstructing the reconfigurable area by using the fast Fourier transform corresponding to the transform length to obtain a target operation area;
and in the target operation area, performing fast Fourier transform on the first target data to obtain first result data.
2. The data processing method according to claim 1, wherein before the step of reconstructing the reconfigurable region by using the fast fourier transform corresponding to the transform length to obtain the target operation region, the method further comprises:
determining an operation architecture of fast Fourier transform corresponding to the first target data;
the step of reconstructing the reconfigurable area by using the fast Fourier transform corresponding to the transform length to obtain the target operation area comprises the following steps:
and reconstructing the reconfigurable region by using the transformation length and the fast Fourier transform corresponding to the operation framework to obtain a target operation region.
3. The data processing method according to claim 2, wherein before the step of reconstructing the reconfigurable region by using the transform length and the fast fourier transform corresponding to the operation architecture to obtain the target operation region, the method further comprises:
determining a butterfly algorithm of fast Fourier transform corresponding to the first target data;
the step of reconstructing the reconfigurable area by using the transform length and the fast fourier transform corresponding to the operation architecture to obtain the target operation area comprises the following steps:
and reconstructing the reconfigurable region by using the transformation length, the operation framework and the fast Fourier transform corresponding to the butterfly algorithm to obtain a target operation region.
4. The data processing method according to claim 3, wherein before the step of reconstructing the reconfigurable region by using the transform length, the operation architecture, and the fast fourier transform corresponding to the butterfly algorithm to obtain the target operation region, the method further comprises:
judging whether the reconfigurable area is in an idle state or not;
the step of reconstructing the reconfigurable region by using the transform length, the operation framework and the fast Fourier transform corresponding to the butterfly algorithm to obtain the target operation region comprises the following steps:
and when the reconfigurable area is in an idle state, reconstructing the reconfigurable area by using the transformation length, the operation framework and the fast Fourier transform corresponding to the butterfly algorithm to obtain a target operation area.
5. The data processing method of claim 4, wherein the terminal device further comprises a processor; after the step of determining whether the reconfigurable area is in an idle state, the method further includes:
and when the reconfigurable area is not in an idle state, performing fast Fourier transform on the first target data in the processor to obtain second result data.
6. The data processing method of claim 4, wherein after the step of performing a fast fourier transform on the first target data within the target operation region to obtain first result data, the method further comprises:
when second target data are received, obtaining a target reconstruction algorithm based on the second target data;
reconstructing the target operation area by using the target reconstruction algorithm to obtain a target reconstruction area;
and processing the second target data in the target reconstruction region to obtain third result data.
7. The data processing method of claim 6, wherein the operational architecture is one of a serial architecture, a parallel pipeline architecture, and a hybrid architecture; the butterfly algorithm is one of Radix-2 and Radix-4.
8. A data processing device is characterized by being used for a terminal device, wherein the terminal device comprises an FPGA with a reconfigurable area; the device comprises:
the receiving module is used for receiving first target data;
a determining module for determining a transform length of a fast Fourier transform of the first target data;
the reconstruction module is used for reconstructing the reconfigurable area by utilizing the fast Fourier transform corresponding to the transform length to obtain a target operation area;
and the obtaining module is used for performing fast Fourier transform on the first target data in the target operation area to obtain first result data.
9. A terminal device, characterized in that the terminal device comprises: an FPGA having reconfigurable areas, a memory, a processor, and a data processing program stored on the memory and running on the processor, the data processing program when executed by the processor implementing the steps of the data processing method of any one of claims 1 to 7.
10. A computer-readable storage medium, characterized in that a data processing program is stored thereon, which when executed by a processor implements the steps of the data processing method according to any one of claims 1 to 7.
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| CN113611292A (en) * | 2021-08-06 | 2021-11-05 | 思必驰科技股份有限公司 | Short-time Fourier change optimization method and system for voice separation and recognition |
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