CN112799329B - Control system for accessing SRAM in sub-clock mode and heterogeneous SOC chip - Google Patents
Control system for accessing SRAM in sub-clock mode and heterogeneous SOC chip Download PDFInfo
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Abstract
The invention discloses a control system for accessing SRAM by a sub-clock and a heterogeneous SOC chip, wherein the control system is divided into two frequency synthesizers, and realizes the sequential control of the read-write operation of a first SRAM particle and a second SRAM particle by controlling the same-frequency and same-phase (synchronous) access mode of a corresponding output clock through a logic gate, so that the second SRAM particle is controlled to stop the read-write operation to enter a dormant state in the process of writing data into the first SRAM particle, and the read-write operation is controlled to start through a clock signal processed by a logic gate after the first SRAM particle is filled or all data in the first SRAM particle is read out, thereby realizing the technical effect that the control system accesses and processes the data into batch sensor data by sub-memory areas in a low-power consumption time-sharing mode, and enhancing the cruising ability of the system when being applied to a positioning system of a plurality of sensors.
Description
Technical Field
The invention relates to the technical field of SRAM application control, in particular to a control system for accessing an SRAM in a time-sharing mode and a heterogeneous SOC chip.
Background
The intelligent sweeping robot needs to monitor and know the surrounding environment through a sensor continuously acquiring data in the sweeping process. With the increasing requirements of the robot on the navigation and obstacle avoidance functions, more and more sensors are integrated on the surface of the robot body, so that a large amount of periodic data is generated in a circuit of a main control board, and therefore, a more powerful Central Processing Unit (CPU) is necessarily integrated to perform more and more calculations.
In the process of executing more and more calculations, the on-chip SRAM of the chip is a module with the highest use frequency and is also a module consuming more power in a circuit system, the larger the capacity of the SRAM memory chip is, the more and more the number to be managed is, the higher the manufacturing cost is, the yield cannot be guaranteed, and the economic efficiency is not good; in order to meet the requirements of "always running" sensor access and the cruising ability of the robot, it is common practice to connect the sensors with a small CPU core. However, the chip processing device in the prior art has the following defects that in the process of periodically processing the sensing data which is read and written in the SRAM by the bus, the SRAM with large capacity cannot sleep in a proper data transmission state, which will increase the power consumption of the system and reduce the cruising ability of the whole sensor system.
Disclosure of Invention
In order to control the SRAM to enter a sleep state in non-working time, the invention discloses a control system for accessing the SRAM by a clock, which controls the open-close logic state of the clock of the read-write SRAM through a simple logic circuit so as to adapt to the trend that the current mobile robot consumer market requires long endurance time of automatic navigation positioning.
The invention discloses a control system for accessing SRAM by clock, comprising: the SRAM comprises a first frequency synthesizer, a first clock gating module, a second frequency synthesizer, an AND gate, a second clock gating module, a first SRAM particle and a second SRAM particle; the output end of the first frequency synthesizer is connected with the input end of the first clock gating module, the first clock gating module is used for dividing a first modulation clock input by the first frequency synthesizer into a path of first sub-clock signals, and then sending the first sub-clock signals into the first SRAM particles, so that after the first SRAM particles finish the read operation or write operation of the sensor data of a preset batch transmitted by the sensor element read-write module, the first frequency synthesizer feeds back an end clock signal to the first frequency synthesizer, and then the first frequency synthesizer adjusts the first modulation clock output by the first frequency synthesizer, and the adjusted first modulation clock and a second modulation clock output by the second frequency synthesizer are in the same frequency and phase; the output end of the first frequency synthesizer and the output end of the second frequency synthesizer are respectively connected with two input ends of an AND gate, the AND gate is used for performing AND logic operation on a first modulation clock output by the first frequency synthesizer and a second modulation clock output by the second frequency synthesizer, and then outputting the AND logic operation result of the two clocks to a second clock gating module, so that before the first frequency synthesizer receives the ending clock signal, the first modulation clock output by the first frequency synthesizer and the second modulation clock output by the second frequency synthesizer are subjected to AND logic operation to output a zero logic level; after the first frequency synthesizer receives the ending clock signal, performing AND logic operation on a first modulation clock output by the first frequency synthesizer in an adjusting way and a second modulation clock output by the second frequency synthesizer to output a third modulation clock, wherein the third modulation clock and the adjusted first modulation clock have the same frequency and phase; the output end of the AND gate is connected with the input end of a second clock gating module, and the second clock gating module is used for dividing a third modulation clock transmitted by the AND gate into a preset number of second sub-clock signals with the same frequency and respectively sending the second sub-clock signals into corresponding second SRAM particles so that the second sub-clock signals start to control the read-write operation of the corresponding second SRAM particles; or, respectively outputting the zero logic level to the corresponding second SRAM granules when receiving the zero logic level transmitted by the and gate, so as to stop the read-write operation on all the second SRAM granules.
Compared with the prior art, the technical scheme divides two frequency synthesizers, and realizes the sequential control of the read-write operation of the first SRAM particle and the second SRAM particle in a mode of controlling the same-frequency and same-phase (synchronous) access to the corresponding output clock through a logic gate, so that the second SRAM particle is controlled to stop the read-write operation to enter a dormant state in the process of writing data into the first SRAM particle, and the second SRAM particle is controlled to start the read-write operation through a clock signal processed by the logic gate after the first SRAM particle is filled or all data in the first SRAM particle are read out, thereby realizing the technical effect that the control system accesses and processes sensor data into batches in a low-power-consumption time-sharing memory-sharing area mode, and enhancing the cruising ability of the system when the control system is applied to a positioning system of a plurality of sensors. On the other hand, the technical scheme can reduce the use of large-capacity SRAM memory chips and reduce the hardware cost.
Further, the control system also comprises a sensor element read-write module; the first frequency synthesizer is used for transmitting a first modulation clock to one input end of the AND gate from power-on oscillation starting; the second frequency synthesizer is used for transmitting a second modulation clock to the other input end of the AND gate from the beginning of receiving the modulation trigger signal output by the sensor element read-write module; the input end of the second frequency synthesizer is connected with the clock output end of the sensor element read-write module and is used for sending a modulation trigger signal to the second frequency synthesizer after a specific batch of sensor data is read from an external sensor of the control system; the data output end of the sensor element read-write module is respectively connected with the data input ends of the first SRAM particles and all the data input ends of the second SRAM particles, and is used for respectively controlling the read-write operation of the corresponding first SRAM particles and the corresponding second SRAM particles according to the clock signal output by the first clock gating module and the clock signal output by the second clock gating module, so that the SRAM particles are configured to cache sensor data for constructing batches of map coordinate information in a time zone needing caching processing. Therefore, the second SRAM particles with larger quantity stop working in the time zone without the need of cache processing, namely, the clock signal input into the second clock gating module is disabled (closed).
Further, the first SRAM grain is coupled to the processor unit, and the data output terminals of the second SRAM grain are connected to the bus interface, so as to ensure that the first SRAM grain and the second SRAM grain receive independent access from the processor unit; wherein the control system comprises a processor unit and a bus interface; wherein the memory capacity of one of the first SRAM particles is a multiple of a preset number of memory capacities of one of the second SRAM particles, the preset number being determined according to the number of types of sensors to be processed. According to the technical scheme, parallel distribution load of multiple SRAM particles is reduced by receiving independent access of the processor unit, the problem that cache contents among multiple second SRAM particles are complex in synchronization is solved by using the bus interface, the use of large-capacity SRAM memory chips is avoided, the manufacturing cost is reduced, and the yield is improved.
Further, before the first frequency synthesizer receives the ending clock signal, a rising edge of a first modulation clock of the modulation output of the first frequency synthesizer is aligned with a falling edge of a second modulation clock of the modulation output of the second frequency synthesizer, and a falling edge of the first modulation clock of the modulation output of the first frequency synthesizer is aligned with a rising edge of the second modulation clock of the modulation output of the second frequency synthesizer, so that the first modulation clock of the modulation output of the first frequency synthesizer and the second modulation clock of the modulation output of the second frequency synthesizer are subjected to AND logic operation to output a zero logic level. The control logic flow of the clock signal is simplified.
Further, the sensor element read-write module is configured to generate an address signal available to the first SRAM particle and an address signal available to the second SRAM particle, so that the first SRAM particle reserved space stores sensor data and a positioning program code to be executed first, and then the second SRAM particle stores the remaining sensor data and the positioning program code to be executed. And the read-write access requirements of the related interface modules are met.
Further, the first frequency synthesizer is configured to, after receiving the ending clock signal, turn off a power supply of an internal phase-locked loop if receiving a third modulation clock fed back by the output end of the and gate, and switch a clock source input by the first clock gating module to a reference clock of an oscillator external to the control system, so as to reduce overall power consumption of the control system.
Furthermore, the second clock gating module is further configured with a clock bus on the interposer, and the clock routing is performed on each second SRAM granule in the interposer, so as to realize data transmission between all the second SRAM granules and the bus interface. Various timings required by the SRAM are satisfied.
Furthermore, a special register is arranged inside the sensor element read-write module and used for receiving an instruction of the processor unit, so that the processor unit can address the sensor data transmitted into the first SRAM particle, and a bus interface can address the sensor data transmitted into the second SRAM particle, so that the whole control system is still integral for an operating system built in the processor unit; the sensor element reading and writing module is further connected with a speedometer, a gyroscope, a visual sensor and a laser sensor. Hardware cost is saved.
The heterogeneous SOC chip is characterized in that the heterogeneous SOC chip integrates a package-level circuit module corresponding to the control system, the technical effect that the control system accesses and processes sensor data in batches in a memory area at low power consumption and time intervals is achieved, and power consumption of the chip is reduced. And the use of large-capacity SRAM particles is reduced, the manufacturing cost of the chip is reduced, and the yield is improved.
Further, the second SRAM grains are all disposed on the same interposer, the first SRAM grains are not disposed on the aforementioned interposer, each second SRAM grain is interconnected with a corresponding dedicated processor unit through a bus, and the dedicated processor units are all disposed on the same interposer. The realization is as follows: stress concentration in the via conductors of the bus interface can be well alleviated even when a preset number of second SRAM particles generate heat during the execution of read-write operations, so that the plurality of SRAM particles can adapt to the warping phenomenon caused by the difference of thermal expansion coefficients between the semiconductor element and the interposer.
Further, hardware accelerated positioning operation executed by each special processor unit is different, so that the heterogeneous SOC chip is installed on the multi-core SOC module of the mobile robot, and the mobile robot is guaranteed to be compatible with and call the inertial sensor, the visual sensor and the laser sensor. Therefore, a large core chip is not required to be manufactured, the yield is greatly improved, and the economy is better.
Drawings
Fig. 1 is a block diagram of a control system for accessing an SRAM with a time-sharing clock according to an embodiment of the present invention.
Detailed Description
The following further describes embodiments of the present invention with reference to the accompanying drawings:
as shown in fig. 1, an embodiment of the present invention discloses a control system for accessing an SRAM in a divided clock manner, the control system including: the SRAM comprises a first frequency synthesizer, a first clock gating module, a second frequency synthesizer, an AND gate, a second clock gating module, a first SRAM particle and a second SRAM particle; the output end of the first frequency synthesizer is connected with the input end of the first clock gating module, the first clock gating module is used for dividing a first modulation clock input by the first frequency synthesizer into a path of first sub-clock signals, specifically, a clock switch circuit in the first clock gating module divides the first modulation clock generated by the first frequency synthesizer into a path of first sub-clock signals, and then the first sub-clock signals are sent to the first SRAM particles, the first sub-clock signals are specially used for driving one first SRAM particle to finish data read-write caching operation according to pre-configured address information or bus read address information, so that the first SRAM particle finishes read operation or write operation on sensor data of a preset batch transmitted by the sensor element read-write module, and then feeds back an end clock signal to the first frequency synthesizer, wherein the sensor data of the preset batch is set aiming at the maximum memory capacity of the first SRAM particle to ensure that enough data are firstly The first modulation clock output by the first frequency synthesizer needs to be adjusted by the first frequency synthesizer, so that the adjusted first modulation clock and the second modulation clock output by the second frequency synthesizer have the same frequency and phase.
In this embodiment, before the clock signal is fed back, the first modulation clock and the second modulation clock output by the second frequency synthesizer are not necessarily in the same frequency and phase, and at this stage, the first SRAM particle may perform a first read operation or a first write operation; after the clock signal is fed back, the first modulation clock and the second modulation clock output by the second frequency synthesizer have the same frequency and phase (that is, the rising edge of the first modulation clock is aligned with the rising edge of the second modulation clock output by the second frequency synthesizer, and the falling edge of the first modulation clock is aligned with the falling edge of the second modulation clock output by the second frequency synthesizer), so that the first modulation clock and the second modulation clock output by the second frequency synthesizer are ensured to be synchronous, and subsequent logic processing is facilitated. The sensor element read-write module is also used for configuring an enable signal, a chip selection signal and an address signal for other circuit modules so as to assist the read-write cache operation of the first SRAM particles and the second SRAM particles and assist the clock generation of the first frequency synthesizer and the second frequency synthesizer.
As shown in fig. 1, the output end of the first frequency synthesizer and the output end of the second frequency synthesizer are respectively connected to two input ends of an and gate, and the and gate is configured to perform an and logic operation on a first modulation clock output by the first frequency synthesizer and a second modulation clock output by the second frequency synthesizer, and output an and logic operation result of the two clocks to the second clock gating module, so that before the first frequency synthesizer receives the end clock signal, the first modulation clock output by the first frequency synthesizer and the second modulation clock output by the second frequency synthesizer perform an and logic operation to output a zero logic level. After the first frequency synthesizer receives the ending clock signal, the first modulation clock regulated and output by the first frequency synthesizer and the second modulation clock output by the second frequency synthesizer are subjected to AND logic operation to output a third modulation clock, wherein the third modulation clock and the adjusted first modulation clock have the same frequency and phase, at the moment, the output end of the AND gate is connected with the input end of the second clock gating module, the third modulation clock transmitted by the and gate is divided into a preset number of second sub-clock signals with the same frequency, and actually, the clock switch unit inside the second clock gating module is turned on to send the second sub-clock signals into the corresponding second SRAM particles respectively, and enabling the second sub-clock signals to start controlling the read-write operation of the corresponding second SRAM granules, and starting the first read-write operation of the second SRAM granules in the process. When receiving the zero logic level transmitted by the and gate, respectively outputting the zero logic level to the corresponding second SRAM particles to stop the read-write operation on all the second SRAM particles, and a preferred example of the and gate outputting the zero logic level is: the rising edge of the first modulation clock output by the first frequency synthesizer is aligned with the falling edge of the second modulation clock output by the second frequency synthesizer, the falling edge of the first modulation clock output by the first frequency synthesizer is aligned with the rising edge of the second modulation clock output by the second frequency synthesizer, wherein the pulse width of the normal logic level ('1') of the first modulation clock is equal to the pulse width of the zero logic level of the second modulation clock, so that the first modulation clock output by the first frequency synthesizer and the second modulation clock output by the second frequency synthesizer are subjected to AND logic operation to output the zero logic level in the same read-write clock period, and the second clock gating module closes the clock switching units corresponding to all the second SRAM particles in the second clock gating module to stop the read-write operation of all the second SRAM particles, therefore, compared with the common knowledge in the corresponding technical field, the complex control logic flow of the clock signal is simplified, the switching control of the read-write state of the second SRAM grain is more direct, and the time sequence logic with excessive transmission is reduced.
Compared with the prior art, the embodiment of fig. 1 is divided into two frequency synthesizers, and the read-write operation of the first SRAM grain and the second SRAM grain is sequentially controlled in a manner of controlling same-frequency and same-phase (synchronous) access to corresponding output clocks through logic gates, so that the second SRAM grain is controlled to stop the read-write operation to enter a sleep state in the process of writing data into the first SRAM grain, and the second SRAM grain is controlled to start the read-write operation through clock signals processed by the logic gates after the first SRAM grain is filled or all data in the first SRAM grain is read out, thereby achieving the technical effect that the control system accesses and processes sensor data into batches in a low-power-consumption time-sharing memory-sharing area, and enhancing the cruising ability of the system when being applied to a positioning system of a plurality of sensors. On the other hand, the control system for accessing the SRAM in a time-sharing manner disclosed in this embodiment can reduce the use of large-capacity SRAM memory chips, and reduce hardware cost.
As an embodiment, as shown in fig. 1, the control system further includes a sensor element read-write module; the first frequency synthesizer is used for transmitting a first modulation clock to one input end of the AND gate from power-on oscillation starting; the second frequency synthesizer is used for transmitting a second modulation clock to the other input end of the AND gate from the beginning of receiving the modulation trigger signal output by the sensor element read-write module; the input end of the second frequency synthesizer is connected with the clock output end of the sensor element read-write module, and the second frequency synthesizer is used for sending a modulation trigger signal to the second frequency synthesizer after a specific batch of sensor data is read from an external sensor of the control system, wherein the frequency of the modulation output of the first frequency synthesizer is not influenced by the modulation trigger signal. The data output end of the sensor element read-write module is respectively connected with the data input end of the first SRAM particle and the data input ends of all the second SRAM particles, and is used for respectively controlling the read-write cache operations of the corresponding first SRAM particle and the corresponding second SRAM particle according to the clock signal output by the first clock gating module and the clock signal output by the second clock gating module, in the process, the first SRAM particle and all the second SRAM particles feed back the read-write state signal of the corresponding SRAM particle to the sensor element read-write module, but the embodiment does not control the second SRAM particle to enter the read-write operation state, but keeps the first SRAM particle to enter the read-write operation state so as to preferentially cache the sensor data to be processed in the sensor element read-write module, so that the first SRAM particle alone is configured to cache the sensor data used for constructing the batch of map coordinate information in the time zone needing cache processing, therefore, the second SRAM particles with larger quantity stop working in the time zone without the need of cache processing, namely, the clock signal input into the second clock gating module is disabled (closed). It should be noted that, in this embodiment, after the sensor data transmitted by the sensor element read-write module completes the write operation of the first SRAM particle, the end clock signal is fed back to the first frequency synthesizer, and the first frequency synthesizer adjusts the first modulation clock output by the first frequency synthesizer, so that the first modulation clock and the second modulation clock have the same frequency and the same phase.
The frequency synthesizer can realize the modulation step length lower than the lMHz, the output frequency modulation range is larger than 10GHz, accurate frequency is provided for the first clock gating module, the second clock gating module and the AND gate logic circuit, and the output clock signal which has a wider frequency band, high resolution and high conversion rate can be synthesized. The frequency synthesizer used in the embodiment has good expandability, can flexibly change the output frequency according to the requirements of application environments, receives the control signal of the external bus and adjusts the corresponding output frequency.
Preferably, the first SRAM granule is coupled to the processor unit, and the data output terminal of the second SRAM granule is connected to the bus interface, so as to ensure that the first SRAM granule and the second SRAM granule receive independent access from the processor unit; wherein the exterior of the control system includes a processor unit and a bus interface, the second SRAM particle receiving individual access control of the processor unit through the bus interface. The parallel distribution load of a plurality of SRAM particles is reduced by receiving the independent access of the processor unit, the problem that cache content is complex in synchronization among multiple second SRAM particles is solved by using the bus interface, the use of partial memory space is controlled by periodically polling different SRAM particles, and then the use of the rest memory space is controlled, so that the large-capacity SRAM storage chip is prevented from being used once, the manufacturing cost is reduced, and the maintenance of the yield of the chip module is facilitated. In this embodiment, the memory capacity of one of the first SRAM grains is a multiple of a preset number of the memory capacities of one of the second SRAM grains, and the preset number is determined according to the type number of the sensors to be processed, so that the control system can adjust parameters according to actual acquisition requirements. As shown in fig. 1, the control system disclosed in this embodiment includes a preset number of second SRAM particles, corresponding to N (in this embodiment, explained as a preset number) second SRAM particles of the SRAMs 101_1, 101_2, …, and 101_ N of fig. 1, where each second SRAM particle corresponds to a second sub-clock signal output by the second clock gating module.
It should be noted that the sensor element read-write module is configured to generate an address signal available to the first SRAM particle and an address signal available to the second SRAM particle, so that the first SRAM particle reserved space stores sensor data and a to-be-executed location program code, and then the second SRAM particle stores remaining sensor data and the to-be-executed location program code, thereby meeting the read-write access requirement of the relevant interface module. The specific processing mode for different types of sensing data can be preset, and certainly, the processing mode for the sensing data can be reset or adjusted according to actual requirements so as to meet different actual requirements.
In the foregoing embodiment, the first frequency synthesizer is configured to, after receiving the ending clock signal, turn off a power supply of an internal phase-locked loop if receiving a third modulation clock fed back by the output end of the and gate, switch a clock source input by the first clock gating module to a reference clock of an oscillator external to the control system, and provide a lower-frequency operating clock signal for the first frequency synthesizer to reduce power, so as to further reduce overall power consumption of the control system.
Preferably, a dedicated register is arranged inside the sensor element read-write module, and is used for receiving an instruction of the processor unit, so that the processor unit can address the sensor data transmitted into the first SRAM particle, so that a bus interface can address the sensor data transmitted into the second SRAM particle, and also can transmit the program code of the SRAM particle in a manner of addressing by the processor unit and support the execution of the code in the SRAM particle, so that the whole control system is still integral to an operating system built in the processor unit, and the use efficiency of the processor unit is also improved. The sensor element reading and writing module is further connected with a speedometer, a gyroscope, a vision sensor and a laser sensor, and the positioning function of the control system is expanded.
Based on the foregoing embodiment, the embodiment of the present invention further discloses a heterogeneous SOC chip, which integrates the package-level circuit modules corresponding to the control system of the foregoing embodiment. The technical effect that the control system accesses sensor data processed into batches in a time-sharing memory area mode with low power consumption is achieved, and the power consumption of a chip is reduced under a read-write cache mode for reducing energy cost through a selection mechanism of working states of different SRAM particles. And the use of large-capacity SRAM particles is reduced, the manufacturing cost of the chip is reduced, and the yield is improved.
In this embodiment, the second SRAM grains are all disposed on the same interposer, the first SRAM grains are not disposed on the interposer, each second SRAM grain is interconnected with a corresponding dedicated processor unit through a bus, and the dedicated processor units are all disposed on the same interposer, so as to implement: stress concentration in the via conductors of the bus interface can be well alleviated even when a preset number of second SRAM particles generate heat during the execution of read-write operations, so that the plurality of SRAM particles can adapt to the warping phenomenon caused by the difference of thermal expansion coefficients between the semiconductor element and the interposer. The dedicated processor units can all select individual chiplets, the chiplets are interconnected by adopting a ring bus, and are packaged on the interposer together with SRAM particles, for example, a BGA surface mounting mode and the like; then, a wiring for routing under the SRAM grain is formed by using a fine wiring, and a second SRAM grain and a dedicated processor unit are formed by using a wiring having a small wiring resistance, and a wiring having a long and thick distance between the first SRAM grain and the processor unit can be formed. Thus, a package-level heterogeneous SOC chip, that is, a chip including a CPU and the control system (representing a low-power logic control device and a memory array) is realized, in which a semiconductor component mounted on an interposer is densified.
In the embodiment, the hardware accelerated positioning operation executed by each special processor unit is different, so that the heterogeneous SOC chip is installed on the multi-core SOC module of the mobile robot, so as to ensure that the mobile robot can compatibly call the inertial sensor, the visual sensor and the laser sensor, each sensing element is in communication connection with the control system, the control system is used for acquiring sensing data acquired by the sensing elements, and read-write caching is carried out on the sensing data and then the sensing data is sent to a processor unit for processing, only the first SRAM particles are cached independently at first, after the first SRAM particle completes the corresponding cache task, the second SRAM particle is woken up from the dormant state to start executing the cache task, or the first SRAM particles and the second SRAM particles execute the caching task in parallel, so that the overall power consumption of the control system is effectively reduced.
The above-described embodiments of the apparatus are merely schematic, where the units described as separate parts may or may not be physically separate, and the parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the embodiment. One of ordinary skill in the art can understand and implement it without inventive effort.
Claims (10)
1. A control system for clock-divided access to SRAM, the control system comprising: the SRAM comprises a first frequency synthesizer, a first clock gating module, a second frequency synthesizer, an AND gate, a second clock gating module, a first SRAM particle and a second SRAM particle;
the output end of the first frequency synthesizer is connected with the input end of the first clock gating module, the first clock gating module is used for dividing a first modulation clock input by the first frequency synthesizer into a path of first sub-clock signals, and then sending the first sub-clock signals into the first SRAM particles, so that after the first SRAM particles finish the read operation or write operation of the sensor data of a preset batch transmitted by the sensor element read-write module, the first frequency synthesizer feeds back an end clock signal to the first frequency synthesizer, and then the first frequency synthesizer adjusts the first modulation clock output by the first frequency synthesizer, and the adjusted first modulation clock and a second modulation clock output by the second frequency synthesizer are in the same frequency and phase;
the output end of the first frequency synthesizer and the output end of the second frequency synthesizer are respectively connected with two input ends of an AND gate, the AND gate is used for performing AND logic operation on a first modulation clock output by the first frequency synthesizer and a second modulation clock output by the second frequency synthesizer, and then outputting the AND logic operation result of the two clocks to a second clock gating module, so that before the first frequency synthesizer receives the ending clock signal, the first modulation clock output by the first frequency synthesizer and the second modulation clock output by the second frequency synthesizer are subjected to AND logic operation to output a zero logic level; after the first frequency synthesizer receives the ending clock signal, performing AND logic operation on a first modulation clock output by the first frequency synthesizer in an adjusting way and a second modulation clock output by the second frequency synthesizer to output a third modulation clock, wherein the third modulation clock and the adjusted first modulation clock have the same frequency and phase;
the output end of the AND gate is connected with the input end of a second clock gating module, and the second clock gating module is used for dividing a third modulation clock transmitted by the AND gate into a preset number of second sub-clock signals with the same frequency and respectively sending the second sub-clock signals into corresponding second SRAM particles so that the second sub-clock signals start to control the read-write operation of the corresponding second SRAM particles; or, respectively outputting the zero logic level to the corresponding second SRAM granules when receiving the zero logic level transmitted by the and gate, so as to stop the read-write operation on all the second SRAM granules.
2. The control system of claim 1, further comprising a sensor element read-write module;
the first frequency synthesizer is used for transmitting a first modulation clock to one input end of the AND gate from power-on oscillation starting;
the second frequency synthesizer is used for transmitting a second modulation clock to the other input end of the AND gate from the beginning of receiving the modulation trigger signal output by the sensor element read-write module;
the input end of the second frequency synthesizer is connected with the clock output end of the sensor element read-write module and is used for sending a modulation trigger signal to the second frequency synthesizer after a specific batch of sensor data is read from an external sensor of the control system;
the data output end of the sensor element read-write module is respectively connected with the data input ends of the first SRAM particles and all the data input ends of the second SRAM particles, and is used for respectively controlling the read-write operation of the corresponding first SRAM particles and the corresponding second SRAM particles according to the clock signal output by the first clock gating module and the clock signal output by the second clock gating module, so that the SRAM particles are configured to cache sensor data for constructing batches of map coordinate information in a time zone needing caching processing.
3. The control system of claim 1 or 2, wherein the first SRAM grain is coupled to the processor unit, and the data output of the second SRAM grain is connected to the bus interface to ensure that the first SRAM grain and the second SRAM grain receive separate accesses from the processor unit;
wherein the control system comprises a processor unit and a bus interface;
wherein the memory capacity of one of the first SRAM particles is a multiple of a preset number of memory capacities of one of the second SRAM particles, the preset number being determined according to the number of types of sensors to be processed.
4. The control system of claim 3, wherein prior to the first frequency synthesizer receiving the end clock signal, a rising edge of the first modulation clock of the first frequency synthesizer modulation output is aligned with a falling edge of the second modulation clock of the second frequency synthesizer modulation output, and a falling edge of the first modulation clock of the first frequency synthesizer modulation output is aligned with a rising edge of the second modulation clock of the second frequency synthesizer modulation output to logically AND the first modulation clock of the first frequency synthesizer output and the second modulation clock of the second frequency synthesizer output to output a zero logic level.
5. The control system of claim 4, wherein the sensor element read/write module is configured to generate an address signal available to the first SRAM granule and an address signal available to the second SRAM granule, such that the first SRAM granule reserved space stores the sensor data and the location program code to be executed first, and then the second SRAM granule stores the remaining sensor data and the location program code to be executed.
6. The control system of claim 5, wherein the first frequency synthesizer is configured to, after receiving the end clock signal, turn off a power supply of an internal phase-locked loop if receiving a third modulation clock fed back from the output of the and gate, and switch a clock source input by the first clock gating module to a reference clock of an oscillator external to the control system, so as to reduce overall power consumption of the control system.
7. The control system of claim 6, wherein the sensor element read-write module is internally provided with a special register for receiving an instruction of the processor unit, so that the processor unit can address the sensor data transmitted into the first SRAM particle, and can address the sensor data transmitted into the second SRAM particle through a bus interface, so that the whole control system is still integral to an operating system built in the processor unit;
the sensor element reading and writing module is further connected with a speedometer, a gyroscope, a visual sensor and a laser sensor.
8. A heterogeneous SOC chip integrating a package-level circuit module corresponding to the control system of any one of claims 1 to 7.
9. The heterogeneous SOC chip of claim 8, wherein the second SRAM dies are disposed on a same interposer, the first SRAM dies are not disposed on the interposer, each second SRAM die is interconnected to a corresponding dedicated processor unit via a bus, and the dedicated processor units are disposed on a same interposer.
10. The heterogeneous SOC chip of claim 9, wherein the hardware accelerated positioning operations performed by each dedicated processor unit are different, such that the heterogeneous SOC chip is installed on a multi-core SOC module of a mobile robot to ensure that the mobile robot is compatible with invoking inertial sensors, visual sensors and laser sensors.
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