CN112789799A

CN112789799A - Control system for medium-voltage variable-frequency drive

Info

Publication number: CN112789799A
Application number: CN201880098211.XA
Authority: CN
Inventors: P.马拉佩尔; J.A.布基; S.丘恩; A.赖特; G.普赫卡雷夫
Original assignee: Siemens AG
Current assignee: Yinmengda Co ltd
Priority date: 2018-08-29
Filing date: 2018-08-29
Publication date: 2021-05-11
Also published as: WO2020046287A1; CA3111189C; CA3111189A1; US11677329B2; US20210313904A1

Abstract

Disclosed herein is a drive system (300) comprising power cells (312) providing power to one or more output phases (A, B, C), each power cell (312) having a plurality of switching devices (315a-d) comprising semiconductor switches; and a control system (400) in communication with the plurality of power cells (312) and controlling operation of the plurality of power cells (312), wherein the control system (400) comprises a system-on-chip (410) including one or more central processing units (412, 414) and a field programmable gate array (416) in communication with the one or more central processing units (412, 414).

Description

Control system for medium-voltage variable-frequency drive

Technical Field

Aspects of the present disclosure relate generally to control systems for Drive systems, and more particularly to control systems for Medium Voltage Variable Frequency Drive (Medium Voltage Variable Frequency Drive). Throughout the specification, the terms "drive," "drive system," "converter," and "power supply" may be used interchangeably.

Background

Because a single power semiconductor device cannot withstand High voltages, Medium Voltage (MV) variable frequency drives (e.g., multilevel power converters) are used in applications of Medium Voltage Alternating Current (AC) drives, flexible AC transmission systems (FACTS), and High Voltage Direct Current (HVDC) transmission systems. Multilevel power converters typically include multiple power cells for each phase, each power cell including an inverter circuit with semiconductor switches that can vary the voltage output of the individual cells.

One example of a multilevel power converter is a cascaded H-bridge converter system having a plurality of H-bridge cells, as described, for example, in U.S. patent No.5,625,545 to Hammond, which is incorporated herein by reference in its entirety. Another example of a multilevel power converter is a modular multilevel converter system with multiple M2C or M2LC subsystems.

Medium voltage drives contain a purpose specific digital control system. Currently, digital control systems divide the control loop commands and status, power cell control information, and external communication interface into three separate components. The three separate main components are: a control processor/host central processing unit for control loop command, status and non-drive interfaces; a Field Programmable Gate Array (FPGA) for power cell control and communication; and an Electronic Programmable Logic Device (EPLD) for external communication. The primary components require a dedicated data bus on a Printed Circuit Board (PCB) so that the primary components can exchange information between them for successful operation of the drive system.

However, current control system architectures require a significant amount of physical space for the PCB data bus wiring design as well as for the three components themselves, and the PCB wiring needs to be carefully designed for the data communications to operate properly/consistently. Furthermore, the use of three separate devices increases the likelihood of overall system failure due to manufacturing defects or general use.

Disclosure of Invention

Briefly described, aspects of the present disclosure relate to drive systems, such as embodied as medium voltage variable frequency drives, and more particularly to control systems for drive systems. Specifically, aspects of the present disclosure provide a drive system comprising: a plurality of power cells providing power to one or more output phases, each power cell including a plurality of switching devices including semiconductor switches; and a control system in communication with and controlling operation of the plurality of power cells, wherein the control system comprises a system-on-chip including one or more central processing units and a field programmable gate array in communication with the one or more central processing units.

Drawings

Fig. 1 shows a schematic diagram of a known basic configuration of a cascaded H-bridge converter system according to an exemplary embodiment of the present disclosure.

Fig. 2 shows a schematic diagram of another known basic configuration of a cascaded H-bridge converter system according to an exemplary embodiment disclosed herein.

FIG. 3 shows a schematic diagram of a drive system in accordance with an exemplary embodiment disclosed herein.

Fig. 4 shows a schematic diagram of an architecture of a control system of a drive system according to an exemplary embodiment disclosed herein.

Fig. 5 shows a perspective view of various control system devices in accordance with exemplary embodiments disclosed herein.

Detailed Description

For the purposes of promoting an understanding of the embodiments, principles and features of the invention, reference will now be made to the embodiments illustrated in the drawings. In particular, they are described in the context of being control systems for variable frequency drives, in particular Medium Voltage (MV) variable frequency drives comprising a multi-cell power supply, such as a modular multilevel converter system and a cascaded H-bridge converter system. Embodiments of the invention, however, are not limited to use in the described devices or methods.

As used herein, "medium voltage" is a voltage greater than about 690V and less than about 69kV, and "low voltage" is a voltage less than about 690V. Those of ordinary skill in the art will appreciate that other voltage levels may be designated as "medium voltage" or "low voltage". For example, in some embodiments, the "medium voltage" may be a voltage between about 3kV to about 69kV, and the "low voltage" may be a voltage less than about 3 kV.

The components and materials described below as making up the various embodiments are intended to be illustrative and not limiting. Many suitable components and materials that can perform the same or similar functions as the materials described herein are also intended to be included within the scope of embodiments of the present invention.

Fig. 1 and 2 each show a schematic diagram of a known multi-cell power supply 10, in particular, a cascaded H-bridge converter system, that receives three-phase power from an Alternating Current (AC) source and delivers the power to a load 12 (e.g., a three-phase AC motor).

Referring to fig. 1, a multi-cell power supply 10 includes a transformer 14, a power circuit 16, and a controller 18, also referred to herein as a control system. The transformer 14 includes primary windings (primary windings) that excite nine secondary windings (secondary windings), and the power circuit 16 includes a plurality of Printed Circuit Board (PCB) power cells 26, referred to herein simply as power cells 26, that are each operatively coupled to the secondary windings of the transformer 14. Since the power supply 10 includes 9 secondary windings and the power cells 26 are operably coupled to each secondary winding, the power supply 10 includes 9 power cells 26. Of course, the power supply 10 may include more or less than 9 power cells 26 and/or more or less than 9 secondary windings depending on the type of power supply 10 and/or the type of load 12 coupled to the power supply 10.

The power unit 26 may be rated for a lower voltage and configured to provide a medium voltage output to the load 12. Each output phase A, B, C of power circuit 16 is powered by a group of series-connected power cells 26. The output of the power cells 26 is coupled in series in a first phase bank 30, a second phase bank 32, and a third phase bank 34. Each phase output voltage is the sum of the output voltages of the power cells 26 in the

respective phase group

30, 32, and 34. For example, the first phase group includes power cells 26 labeled a1, a2, and A3, where the phase output voltage of output phase a is the sum of the output voltages of power cells a1, a2, and A3. The same applies to output phase B and power cells B1, B2, B3, and output phase C and power cells C1, C2, C3. In this regard, power circuit 16 delivers medium voltage output to load 12 using lower voltage rated power cells 26, which include components rated to a lower voltage standard. Each power cell 26 is coupled (e.g., via a fiber optic communication link) to the controller 18, and the controller 18 may use current feedback and voltage feedback to control the operation of the power cells 26.

As shown in fig. 2, the multi-cell power supply 10 includes a three-phase AC power supply 20, a power circuit 16, and a controller 18. The three-phase AC power supply 20 includes two diode bridges 22, each connected on the AC voltage side to a secondary winding of a power converter transformer 24, and electrically connected in series on the Direct Current (DC) voltage side. The parallel connection of these phase groups provides positive and negative DC voltage buses. The power circuit 16 includes a power cell 28 coupled to a DC voltage bus drawn (produced) by the power supply 20. For example, power unit 28 is rated for a lower voltage and is configured to provide a medium voltage output to load 12. Although load 12 may be illustrated as being in multi-cell power supply 10, load 12 is not part of multi-cell power supply 10. Conversely, as shown more clearly in fig. 1, the load 12 is independent of the multi-cell power supply 10 and is connected to the multi-cell power supply 10.

Each output phase A, B, C of power circuit 16 is powered by a group of series-connected power cells 28, and the reference output phases are labeled A1-A4, B1-B4, and C1-C4. The power cells 28 are coupled in series in a first phase group 30, a second phase group 32, and a third phase group 34. Each phase output voltage is the sum of the output voltages of the power cells 28 in the

phase groups

30, 32 and 34 as previously described with reference to fig. 1. Power circuit 16 delivers medium voltage output to load 12 using a lower voltage rated power cell 28, where power cell 28 includes components rated to a lower voltage standard. Each power cell 28 is coupled (e.g., via a fiber optic communication link) to the controller 18, which may use current feedback and voltage feedback to control the operation of the power cells 28.

It should be noted that in fig. 1 and 2, the number of

power cells

26, 28 in each

phase group

30, 32, 34 may be between 2 and 12 to provide different medium voltage outputs according to the requirements of the load 12. As previously mentioned, in the embodiment of fig. 1, the number of secondary windings of the transformer 14 matches the number of power cells 26. In the embodiment of fig. 2, the number of diode bridges and transformer secondary windings may vary from 1 to 6 to allow for harmonic cancellation on the primary side of the transformer 24. It will be appreciated by those of ordinary skill in the art that other cell numbers and diode bridge numbers may be used depending on the application, and that the configurations shown and described herein are intended to be exemplary in nature.

Fig. 3 shows a schematic diagram of a drive system 300 comprising a cascaded H-bridge multilevel converter 310 having a seven-stage topology, comprising three phases with three power cells per phase, which additionally contains a control system 400, in accordance with an aspect of the present invention. An example of a cascaded H-bridge multilevel converter 310 is Perfect harmonic produced by Siemens Industry, Inc (Siemens industries, Inc)

And (5) driving.

In the example of fig. 3, the system 300 is a medium voltage drive that includes a three phase power source (power source) that provides a power input 302 via lines L1, L2, and L3. The multilevel converter 310 is connected to the AC power input 302 and generates a three-phase AC power supply as the output 303 via the output phases A, B and C. The AC output 303 may be connected to a load 320, which in this example comprises a motor. The motor 320 may be operated by controlling the frequency and/or amplitude of the output voltage generated by the multilevel converter 310.

Each phase of the multilevel converter 310 includes a respective phase leg formed from a plurality of power cells 312 arranged in a cascaded manner. In the example of fig. 1, phase legs a, B are each formed from the same number (i.e., 3) of power cells 312 connected in series. Each power cell 321 of a phase is connected to the power input 302 via input lines L1, L2, and L3, respectively. For example, power to the input lines L1, L2, L3 may be provided via a multi-phase winding transformer.

The three-phase power cells 312 are respectively labeled as cell A₁To unit A₃Unit B₁To unit B₃And a unit C₁To cell C₃. Each power cell 312 is responsive to control signals from the control system 400, including, for example, Pulse Width Modulation (PWM) signals to vary the voltage level and/or frequency output, forming a multi-level voltage waveform for each phase. The power cells 312 typically include power semiconductor switching devices, passive components (inductors, capacitors), control circuitry, processors, interfaces, and other components for communicating with the control system 400 (i.e., the power cells operate based on signals from the control system 400).

Each power cell 312 includes a single phase inverter circuit connected via input lines L1, L2, L3 to an independent Direct Current (DC) source resulting from the rectification of the AC power input to each power cell 312. In this example, the rectification is performed by diode rectifiers 313a-f arranged in a bridge rectifier configuration. The present example also uses a filter circuit including, for example, a capacitor 314 for smoothing the output voltage ripple from the rectified DC power.

The inverter circuit of each cell 312 includes power semiconductor switching devices 315a-d arranged in an H-bridge (also referred to as full-bridge) configuration. Switching devices 315a-d may include, for example, but are not limited to, power transistors (e.g., insulated-gate bipolar transistors (IGBTs)). The

switching devices

315a, 315b are connected to the cell output line 316a, while the

switching devices

315c, 315d are connected to the cell output line 316 b. Transistors 315a-d receive a pulse width modulated signal, for example, in the form of a gate input signal 318 controlled by control system 400 based on pulse width modulation. The control system 400 selects either of the

transistors

315a or 315b to be conductive via the first switch leg 317a and either of the

transistors

315c or 315d to be conductive via the second switch leg 317b, which will allow power to pass to the load 320 via

lines

316a or 316b, respectively. In other words, the controller of the switch leg 317a triggers a switching event such that one of the

transistors

315a, 315b is in a conducting state and the other is in a blocking state. Likewise, the controller of switch leg 317b triggers a switching event such that one of

transistors

315c, 315d is in a conducting state and the other is in a blocking state. In the illustrated embodiment, the switch legs 317a, 317B of an individual cell 312 are referred to simply as switch leg a and switch leg B of the individual cell 312.

Although each power cell 312 is included in medium voltage device drive 300, each power cell 312 may be built internally to a low voltage standard. For example, each power cell 312 may have a nominal voltage of 600 volts. Thus, the maximum voltage level that can be output by each power cell 312 is approximately 600 VDC. The output voltage on the

cell output line

316a, 316b of each power cell 312 may be either polar or zero, depending on which transistor is on. Thus, each power cell 312 may have three output states: +600VDC, -600VDC, or 0 VDC. Due to the serial connection between the three power cells 312 in each phase output line (e.g., cell A of output phase A)₁、A₂、A₃) A maximum output voltage magnitude of about 1800VDC may be produced for the respective phase output lines. Each power cell 312 may operate independently of the other. Thus, at least seven voltage levels per phase may be provided for the motor 320. Approximate values of these line neutral voltage states include +/-1800VDC, +/-1200VDC, +/-600VDC and 0 VDC.

The motor 320 may comprise any type of AC type motor, for example, synchronous, asynchronous, permanent magnet, and may be rated for low, medium, or high voltage. For example, medium voltage AC motors (such as those used for industrial process control) may operate in the range of 4.16kV to 13.8 kV. Greater or lesser voltages may be used. More than one motor 320 may be connected. Other loads may be used in place of motor 320 or in addition to motor 320. The motor 320 increases, decreases, or maintains speed or position in response to the voltage applied to the three phases by the multilevel converter, for example.

Fig. 4 shows a schematic diagram of an architecture of a control system 400 of a drive system according to an exemplary embodiment disclosed herein. The control system 400 will be described with reference to the drive system 300 of fig. 3. However, it should be noted that other types of drive systems may be used in connection with the control system 400, such as modular multilevel converter systems having M2C or M2LC subsystems.

In an example, drive system 300 including control system 400 having SOC410 may be embodied as a medium voltage variable frequency drive including an output voltage between about 2.3kV and about 11 kV.

As previously mentioned, the control system of current drive systems divides the control tasks (e.g., control loop commands and status, power cell control information, and external communication interface) into 3 separate components that require a dedicated data bus on the printed circuit board. Accordingly, an improved control system 400, described in detail with reference to FIG. 4, will be provided.

In accordance with an exemplary embodiment, control system 400 includes a system on a chip (SOC)410 that integrates the primary control components into a single integrated circuit instead of a stand-alone device. A system-on-chip (also referred to as a chip-level system) is an integrated circuit that integrates all or most of the components of a computer or other electronic system on a single substrate.

The SOC410 includes one or more Central Processing Units (CPUs) 412, 414, and a Field Programmable Gate Array (FPGA)416 in communication with the one or more

central processing units

412, 414. Specifically, the embodiment provides a first central processing unit (CPU1)412 and a second central processing unit (CPU2)414, each performing different tasks. However, it should be noted that the first and second

central processing units

412, 414 may be combined into a single central processing unit.

The first central processing unit 412 may be referred to as a "system manager", wherein the second central processing unit 414 may be referred to as a "controller". Each

central processing unit

412, 414 includes a microprocessor and other circuitry to perform control and processing tasks.

The first processing unit 412 (system manager) is configured to communicate with an ethernet interface 420, a file system interface 422, one or more USB interfaces 424, and an analog-to-digital interface 426. The various interfaces may be considered 'non-driving' interfaces and the information provided by the interfaces may be considered 'non-driving' information or commands and status information.

The second processing unit 414 (controller) is configured to receive the power unit control information and generate operating commands for the power unit 312. The second processing unit 414, in conjunction with the FPGA416, controls the operation of the power cell 312 and thus provides functionality to control a load (e.g., the motor 320 of the drive system 300). The second processing unit 414 may be operatively coupled to memory 430, such as non-volatile random access memory (NVRAM), a keyboard 432 (e.g., for inputting parameters of a drive system), and a MODBUS I/O (input/output) module 434. Modbus is a serial communication protocol used to connect industrial electronic devices.

The first and second

central processing units

412, 414 are in communication with each other via an interprocess communication link 436, and both processing

units

412, 414 may be configured to communicate with a memory 438, which may be a random access memory. The components described with respect to the first and second

central processing units

412, 414 and the FPGA416 are included on the SOC 410.

Referring to a further embodiment, the SOC includes a dedicated data bus 440 labeled as a parallel interface, which is used for communication purposes between the

central processing units

412, 414 and the FPGA 416.

The FPGA416 is configured to communicate with: one or more analog-to-digital converters (ADCs) 442, a power cell bypass system 444, a plurality of power cells 446 (e.g., power cells 312 of fig. 3), an encoder 448, one or more input/output interfaces (critical I/os) 450, and an internal network (driver/driver) 452.

One or more analog-to-digital converters 442 may be utilized to convert a plurality of analog signals (e.g., voltage amplitude, current amplitude, cell temperature, etc.) into digital signals. The power cell bypass system 444 may be utilized to bypass one or more failed power cells of the drive system. Each power cell 446 sends operational information to the FPGA416 and receives operational commands via the FPGA 416. The encoder 448 is associated with the motor 320 of the system 300 and translates the rotational movement or position of the motor into a code of electronic pulses and transmits the electronic pulses to the FPGA 416. The one or more input/output interfaces 450 may be embodied as, for example, switches, potentiometers, etc., which allow an operator of the drive system to provide certain parameters. An internal network 452 may be utilized to facilitate interconnection of multiple drive systems. The information provided by the

devices

442, 444, 446, 448, 450, 452 may be considered as 'driving' information, which includes specific information related to power cell control.

In operation, the FPGA416 performs logical operations on the received drive information and then passes the resulting information to the second central processing unit (controller) 414. The second processing unit 414 processes the resulting information and, based on the processed information, generates operational commands for the FPGA416 to distribute to the appropriate interfaces, e.g., the power unit 446 and the encoder 448. Basically, the FPGA416 handles internal management (housekeeping) and unique communications to the appropriate interface.

SOC410 may include additional components. These components may include, for example: a real-time clock 472; a Read Only Memory (ROM) 474; one or more sensors 474, 476 (e.g., temperature, humidity, or pressure sensors); and a power management bus (PMBus) 480. The

components

472, 474, 476, 478, 480 communicate via an integrated circuit bus (I2C).

In another exemplary embodiment, as shown in fig. 4, the control system 400 further includes a communication board 460 for external communication. The communication board 460 may be external to the SOC410, where the SOC and communication board 460 communicate via a data BUS (BUS) 462. The communications board 460 may include an additional field programmable gate array 464, the additional field programmable gate array 464 configured to perform external communications 466 and communicate with devices external to the SOC (e.g., an interface 468 for connecting, for example, a motor module, a terminal module, or a sensor module to a drive system).

However, by using the SOC410 and the FPGA416 having a sufficiently large logic density, an external communication function (communication board 460) can also be included in the SOC 410. In this case, the FPGA416 is also configured to communicate with devices or systems external to the SOC410, such as an external network.

Further, the control system 400 also stores and executes specific instructions to implement Pulse Width Modulation (PWM) control. By pulse width modulating the voltage reference for each phase, the control system 400 (and in particular the second processing unit 414) controls each power cell 446 (power cells 312 of fig. 3), and thus the amplitude and frequency of the voltage output between the

output lines

316a, 316b of each power cell 312. Local control circuits or control boards in the respective power cells 312 may receive the voltage reference and generate the gate pulses for the power switching devices using appropriate vector control and pulse width modulation. Alternatively, processing unit 414 may output a strobe for unit 312 based on the reference voltage.

Fig. 5 shows a perspective view of various control system devices in accordance with exemplary embodiments disclosed herein. In particular, fig. 5 illustrates an improved control system 400 including an SOC410 as compared to an existing control system 500. The control system 500 comprises, for example, a radiator 510, which is necessary for cooling purposes and which transfers heat generated mainly by the internal central processing unit. The control system 400 does not require such a heat sink because it contains a SOC410 that includes a central processing unit and many other components.

The SOC410, including all its components, is etched on a silicon wafer (silicon wafer). By using a SOC, a single device is used that contains one or more

central processing units

412, 414 and FPGA logic 416 and a dedicated data bus. Thus, the physical space for the control system 400 is reduced. Instead of three or four separate devices, only one device, SOC410, is needed. The reduced size provides additional space to add electrical features to the existing form factor (form factor) of the control system 400. Due to the data bus 440 inside the SOC410, PCB data bus routing interconnects need not be carefully designed. Further, reducing the number of components increases the robustness of the control system to faults.

Claims

1. A drive system (300), comprising:

a plurality of power cells (312) providing power to one or more output phases (A, B, C), each power cell (312) including a plurality of switching devices (315a-d) including semiconductor switches, and

a control system (400) in communication with the plurality of power cells (312) and controlling operation of the plurality of power cells (312),

wherein the control system (400) comprises a system on chip (410) comprising:

one or more central processing units (412, 414), and

a field programmable gate array (416) in communication with the one or more central processing units (412, 414).

2. The drive system (300) of claim 1,

wherein the system on chip (410) further comprises a dedicated data bus (440) between the one or more central processing units (412, 414) and the field programmable gate array (416).

3. The drive system (300) of claim 1 or 2,

wherein the system on chip (410) comprises a first and a second central processing unit (412, 414) communicating with each other,

wherein the second central processing unit (414) is configured to receive power cell control information and generate a first operation command, an

Wherein the first central processing unit (412) is configured to receive a command and status information and to generate at least one instruction based on the command and status information, the at least one instruction configured to instruct the second processing unit (414) to generate a second operation command.

4. The drive system (300) of claim 3,

wherein the field programmable gate array (416) is in communication with the plurality of power cells (312) and is configured to

Receiving the power cell control information from each of the plurality of power cells (312),

sending the power cell control information to the second central processing unit (414), and

the first and second operating commands are received from the second central processing unit (414) for allocation to the plurality of power cells (312).

5. The drive system (300) of any of the preceding claims,

wherein the field programmable gate array (416) is configured to assign the first and/or second operation command to at least one of an analog-to-digital converter (442), a power cell bypass system (444), a power cell (312, 446), an encoder (448), an input-output interface (450), and an internal network (452).

6. The control system (300) of any of the preceding claims,

wherein the field programmable gate array (416) is further configured to communicate with a device external to the system-on-chip (410).

7. The control system (300) of any of the preceding claims,

wherein one of the central processing units (412, 414) is configured to communicate with at least one of an Ethernet interface (420), a file system interface (422), a universal serial bus interface (424), and an analog-to-digital converter interface (426).

8. The control system (300) of any of the preceding claims,

wherein one of the central processing units (412, 414) is operatively coupled to the memory (430), the keyboard (432), and the MODBUS input/output module (434).

9. The drive system (300) of claim 3,

wherein the system on chip (410) further comprises a memory (438), the first and second central processing units (412, 414) being configured to communicate with the memory (438).

10. The drive system (300) of claim 1,

wherein the control system (400) further comprises a communication board (460) external to the system-on-chip (410), the system-on-chip (410) and the communication board (460) communicating via a further data bus (462).

11. The drive system (300) of claim 10,

wherein the communication board (460) includes a further field programmable gate array (464) configured to communicate with a device external to the system-on-chip (410).

12. The drive system (300) of any of the preceding claims,

wherein the system-on-chip (410) is etched on a silicon wafer.

13. The drive system (300) of any of the preceding claims,

embodied as a medium voltage variable frequency drive comprising an output voltage of between about 2.3kV and about 11 kV.

14. The drive system (300) of any of the preceding claims,

a cascaded H-bridge converter system (310) is also included.