CN112787755B - Decoding method and device based on backward error correction mechanism and electronic equipment - Google Patents
Decoding method and device based on backward error correction mechanism and electronic equipment Download PDFInfo
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Abstract
The invention provides a decoding method and a device based on a backward error correction mechanism, wherein the method comprises the following steps: generating a first baseband signal and a second baseband signal, wherein the duty ratio information of the first baseband signal is complete, and the pulse edge information of the second baseband signal is complete; generating a frame synchronization signal and a decoding start signal by detecting the characteristic sequences of the first baseband signal and the second baseband signal, and starting a time base counter; reconstructing the first baseband signal according to the pulse width information of the first baseband signal and the second baseband signal; according to whether the pulse width of the first baseband signal accords with an FM0 coding rule or not, performing pre-decoding and fuzzy decoding on the first baseband signal; and acquiring a reconstructed first baseband signal corresponding to the fuzzy decoded position information, decoding and updating the fuzzy decoding. The invention can reduce hardware cost, improve decoding capability, improve adaptability in complex environment, improve RSU decoding sensitivity and improve same-frequency inhibition capability.
Description
Technical Field
The invention relates to a baseband decoding technology of FM0 coding in the field of station type RSU, in particular to a decoding method, a decoding device and electronic equipment based on a backward error correction mechanism in an FM0 coding mode.
Background
The FM0 code is called as bidirectional interval code, and features easy bit sync extraction, narrow frequency band, simple circuit, high real-time performance and reliability and wide application in short-range communication. For example, the coding method is used for communication between an On Board Unit (OBU) and a Road Side Unit (RSU) of the ETC system. In order to increase the communication distance of the device, the RSU needs to increase the index of the decoding sensitivity, and the key factor affecting the index is the quality of the baseband signal.
Disclosure of Invention
The purpose of the invention is realized by the following technical scheme.
The invention provides a decoding method aiming at a low-cost hardware scheme, which can correct errors of decoding information, further improve the success rate of decoding and achieve the purposes of improving the sensitivity of RSU decoding and improving the same-frequency inhibition capability.
An embodiment of a first aspect of the present application provides a decoding method based on a backward error correction mechanism, where the method includes:
generating a first baseband signal and a second baseband signal, wherein the duty ratio information of the first baseband signal is complete, and the pulse edge information of the second baseband signal is complete;
generating a frame synchronization signal and a decoding start signal by detecting the characteristic sequences of the first baseband signal and the second baseband signal, and starting a time base counter;
reconstructing the first baseband signal according to the pulse width information of the first baseband signal and the second baseband signal;
according to whether the pulse width of the first baseband signal accords with an FM0 coding rule or not, performing pre-decoding and fuzzy decoding on the first baseband signal;
and acquiring a reconstructed first baseband signal corresponding to the fuzzy decoded position information, decoding and updating the fuzzy decoding.
In some embodiments of the present application, the first and second baseband signals are generated by controlling a comparator chopping level threshold of an intermediate frequency processing circuit.
In some embodiments of the present application, the time delay between the first baseband signal and the second baseband signal is within one half symbol period of FM0 encoding.
In some embodiments of the present application, the timebase counter is used for synchronization of the first baseband signal with the second baseband signal and for timeout determination.
In some embodiments of the present application, reconstructing the first baseband signal according to the pulse width information of the first baseband signal and the second baseband signal includes:
if the pulse width of the first baseband signal is lower than a first threshold value, combining the pulse width of the first baseband signal with the pulse width adjacent to the pulse width of the first baseband signal;
if the pulse width of the first baseband signal is higher than a second threshold value, acquiring the corresponding pulse width of a second baseband signal according to the time base counter; and updating the pulse width of the first baseband signal according to the pulse width of the corresponding second baseband signal.
In some embodiments of the present application, predecoding and blur decoding the first baseband signal according to whether the pulse width of the first baseband signal complies with the FM0 encoding rule comprises:
predecoding the first baseband signal according to the condition that the pulse width of the first baseband signal accords with an FM0 coding rule;
and according to the fact that the pulse width of the first baseband signal does not accord with the FM0 coding rule, combining the pulse width quantities before and after the pulse width which does not accord with the FM0 coding rule until the total pulse width quantity after combination is integral multiple of the width of the FM0 code element, carrying out fuzzy decoding on the combined pulse width, and recording the position of the fuzzy decoding.
In some embodiments of the present application, the ambiguous decoding is a predictive symbol, comprising 01 and 10.
An embodiment of a second aspect of the present application provides a decoding apparatus based on a backward error correction mechanism, the apparatus comprising;
the double-path baseband generating module is used for generating a first baseband signal and a second baseband signal, wherein the duty ratio information of the first baseband signal is complete, and the pulse edge information of the second baseband signal is complete;
the frame synchronization module is used for generating a frame synchronization signal and a decoding start signal by detecting the characteristic sequences of the first baseband signal and the second baseband signal and starting a time base counter;
a baseband reconstruction module, configured to reconstruct the first baseband signal according to pulse width information of the first baseband signal and the second baseband signal;
the pre-decoding module is used for performing pre-decoding and fuzzy decoding on the first baseband signal according to whether the pulse width of the first baseband signal conforms to the FM0 coding rule or not;
and the decoding error correction module is used for acquiring the reconstructed first baseband signal corresponding to the fuzzy decoding position information, decoding and updating the fuzzy decoding.
Embodiments of the third aspect of the present application provide an electronic device, which includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the method of the first aspect.
An embodiment of a fourth aspect of the present application provides a computer-readable storage medium having a computer program stored thereon, the program being executable by a processor to implement the method of the first aspect.
The invention has the advantages that: the hardware cost can be reduced, the decoding capability is improved, the adaptability in a complex environment is improved, the RSU decoding sensitivity is improved, and the same-frequency inhibition capability is improved. By the method, two paths of baseband signals can be generated only by processing the signals of the mirror path in intermediate frequency processing, the scheme is simple, the hardware cost cannot be increased, and the communication load cannot be increased; the method is low in implementation complexity, can be implemented by a CPU (central processing unit) of a serial processing mechanism or a simple FPGA (field programmable gate array), and controls the manufacturing cost of equipment; compared with the conventional method, the RSU decoding sensitivity is improved by 10dB to 15dB, the communication distance is directly improved by 1.5-2 times, and the performance index requirement of a high-cost hardware scheme can be met.
Drawings
Various additional advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to refer to like parts throughout the drawings. In the drawings:
FIG. 1 is a flowchart illustrating a decoding method based on a backward error correction mechanism according to an embodiment of the present invention;
FIG. 2 is a schematic diagram illustrating a decoding method according to an embodiment of the present invention;
FIG. 3 shows a flow diagram of a baseband reconstruction process according to an embodiment of the invention;
FIG. 4 illustrates a pre-decoding and error correction flow diagram according to an embodiment of the present invention;
FIG. 5 is a block diagram of a decoding apparatus based on a backward error correction mechanism according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of an electronic device according to an embodiment of the present application;
fig. 7 is a schematic diagram of a storage medium provided by an embodiment of the present application.
Detailed Description
Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
In the emerging field station type RSU application, because the electromagnetic environment of an application scene is more complex and the cost control is more severe, after a low-cost hardware scheme is adopted in baseband processing, the performance of hardware in the aspect of common-frequency rejection is reduced, the effective communication distance of the RSU is shortened, and in order to solve the problems that the waveform quality of a baseband signal of FM0 coding is deteriorated due to external electromagnetic strong interference, and even the communication quality is reduced due to the introduction of burrs, the purpose of improving the decoding sensitivity of RSU equipment and the performance index of common-frequency rejection is achieved, the FM0 decoding method of the backward error correction mechanism is provided.
The invention has proposed a decoding based on mechanism of backward error correction, this method produces two routes of baseband signals through the hardware, one is that the duty cycle condition is better, but will lose the jump edge (define as the baseband 1 here), another is that the duty cycle condition is worse, but the information edge keeps intact (define as the baseband 2 here), two routes of baseband signals realize the production of different baseband through controlling the comparator chopping level threshold value of the intermediate frequency processing circuit, can guarantee the duty cycle of the baseband signal is better when the threshold value level is higher (but because chopping is higher, will not exceed the pulse of the cut-off level to cut off, this kind of pulse may be useful information, may also be the burr noise); when the threshold level is low, it is ensured that the edge information of the baseband signal is complete (but since the cut-off level is low, the redundant glitch information will remain). The two paths of base bands are processed, the base band signal 1 with the good duty ratio and the base band signal 2 with the complete pulse edge are subjected to pattern recognition, a pattern recognition library is built in real time, useless burrs are filtered, complete duty ratio information is reserved, and reconstruction of the base band signals is completed. Under the environment that the electromagnetic environment is clean, the baseband 1 signal can basically complete normal functions in the pre-decoding stage, when the electromagnetic environment is complex, because the traditional single baseband processing causes duty cycle distortion or leads to the introduction of unnecessary burr information edges, both the two conditions can cause decoding failure, after the two types of baseband are processed, the reconstructed baseband signal can process and filter the two extreme error conditions, and the error correction is carried out on the place where the pre-decoding is wrong (both the duty cycle distortion and the burr pulse can cause decoding errors), so that the decoding is completed.
Example 1
The invention provides a decoding method of FM0 coding based on a backward error correction mechanism aiming at a field station type RSU of a low-cost radio frequency scheme, the whole flow of the method is shown in the attached figure 1, and the method comprises the following 5 steps:
s1, a two-way baseband generation step: and generating a first baseband signal and a second baseband signal, wherein the duty ratio information of the first baseband signal is complete, and the pulse edge information of the second baseband signal is complete.
As shown in fig. 2, the generation of the two baseband signals is realized by controlling the difference of the chopping voltages of the intermediate frequency processing portion, the step is realized by a hardware circuit, and the standard of the realization needs to meet the requirement that the delay of the two baseband signals is controlled within a half FM0 code element period, so as to ensure that the time base alignment of the two baseband signals can be performed in the subsequent processing step.
S2, frame synchronization: a frame synchronization signal and a decoding start signal are generated by detecting a characteristic sequence of the first baseband signal and the second baseband signal, and a time base counter is started.
The method comprises the steps of finishing initial detection of a frame signal, finishing generation of a synchronous signal by detecting a characteristic sequence 1100000000 of a baseband, generating a decoding start signal by the synchronous signal, starting a time base counter to work, and triggering work of a subsequent baseband reconstruction step, a decoding step and a decoding error correction step. The time base counter is used for synchronizing a baseband 1 buffer and a baseband 2 buffer RAM (random access memory) or FIFO (First in First out) memory at the back, and is used for overtime judgment to prevent error decoding caused by error synchronization, because abnormal frame data can also cause decoding to start if FM0 coding characteristics exist, but the data frame cannot detect the sequences of a frame head 01111110 and a frame tail 01111110.
S3, baseband reconstruction: and reconstructing the first baseband signal according to the pulse width information of the first baseband signal and the second baseband signal. If the pulse width of the first baseband signal is lower than a first threshold value, combining the pulse width of the first baseband signal and the pulse width adjacent to the pulse width of the first baseband signal; if the pulse width of the first baseband signal is higher than a second threshold value, acquiring the corresponding pulse width of a second baseband signal according to a time base counter; and updating the pulse width of the first baseband signal according to the corresponding pulse width of the second baseband signal.
The step and the pre-decoding step can be carried out synchronously or successively, and mainly distinguishes whether the pulse width of the baseband 1 is too narrow or too wide, if the too narrow pulse width is possibly a burr, the burr information is merged to the pulse width on the left side and the pulse width on the right side which are nearest to the burr information. If the pulse width of the baseband 1 is too wide, which may be the case that the information edge is lost, under such a condition, edge repair and supplementation are performed according to the baseband 2 with the complete information edge of another path (the baseband image is not good in duty ratio with the baseband 1 signal, but the information edge is completely preserved), and the baseband signal is reconstructed through the method.
As shown in fig. 3, when the decoding starts, the pulse width information of two paths of baseband signals with different characteristics is buffered and stored after detecting the frame synchronization signal. When the number of the pulse widths reaches a set value, the pulse width information detection is started, the stored width information of the baseband 1 is read, if the width information is smaller than a set minimum threshold value, the stored width information is considered to be a burr caused by interference, and then the pulse width information is added with the width values of the left side and the right side (actually, the burr information is removed in the baseband 1, and the addition is still needed here because the burr may still be the burr, namely, the pulse width should not appear there, and then the function of removing the burr is realized by adding the pulse width information with the left pulse width and the right pulse width). If the left side and the right side are low level, generating new low level pulse width, otherwise, generating new high level pulse width and storing; if the read pulse width information is larger than the set maximum value, the pulse width is considered to lose part of the information edge in the middle, a time base counter synchronously stored with the pulse width is read at the moment, the pulse width information in the RAM (or FIFO) of the access baseband 2 is read according to the time base counter, the information edge lost in the middle is repaired, the repairing principle is that the FM0 coding rule can be met after repairing, the matching is carried out on the part which does not meet the rule, and therefore the baseband signal of the problem point is reconstructed.
In the step of baseband reconstruction, the role of the base counter is crucial. The principle that the base counter ensures signal synchronization of the baseband 1 and the baseband 2 is as follows: because two paths of baseband signals can ensure the same phase on hardware, namely almost 0 time delay, after the frame synchronization is started, the time base counter can indicate the decoding position of the current baseband 1, the pulse width in the baseband 2 is read and added according to the current time base, and the decoding position of the current baseband 1 is the time base counter, so that the time base counter only needs to finish reconstructing the baseband corresponding to the position of the baseband 1. The difference between the two paths of baseband is explained as follows: in the baseband 1, because the chopping level threshold value is high, the pulse width which does not exceed the chopping level threshold value can be filtered out on hardware, but sometimes the pulse width is actually useful coded information; similarly, baseband 2 will retain the filtered pulse width in baseband 1 in baseband 2 because of the low threshold chopping level, but glitch information will also be retained in baseband 2 because of the low threshold chopping level. The glitch information is useless to be filtered out, the glitch information is filtered out, the baseband 1 is realized on hardware, and in order to guarantee the decoding correctness, a glitch judgment mechanism is added logically in the decoding method, so the baseband 2 can only provide jump edge information when the baseband is reconstructed, for example, the baseband 1 has normal code element information which is filtered out because the hardware does not reach the threshold value of the chopping level of the baseband, the information edge of the baseband 1 is lost, the pulse width of the lost part is too wide, at the moment, the same position of the baseband 2 is read, the lost rising edge or the falling edge can be found, the baseband 1 is repaired according to the edge, and the error correction method can be realized, and the true meaning of 'backward' is also realized.
S4, predecoding: and according to whether the pulse width of the first baseband signal accords with the FM0 coding rule or not, performing pre-decoding and fuzzy decoding on the first baseband signal, and recording position information of the fuzzy decoding.
The step and the baseband reconstruction step can be carried out synchronously or successively, the initial baseband 1 signal is subjected to preliminary decoding attempt, and decoding information and decoding position synchronization information are cached.
As shown in fig. 4, the predecoding step predecodes the baseband 1 signal, if the pulse width information conforms to the FM0 encoding rule during the judgment process, the decoding continues, when a serious overrun pulse width is found (if the overrun pulse width occurs, it is determined that the loss information is along, the reconstructed baseband signal can make up for the defect because the reconstructed baseband has already processed the overrun pulse width and the glitch pulse width), the pulse width quantities before and after the overrun pulse width are combined until the total quantity of the combined pulse width is an integral multiple of the FM0 symbol width, the segment is subjected to the fuzzy decoding, the fuzzy decoding position is recorded, the decoding information is cached, and the position information of the fuzzy decoding is sent to the decoding error correction step for decoding and correction.
In this step, the meaning of the fuzzy decoding, i.e. the estimated symbols, is only possible in two ways: 01 and 10, because the FM0 code in the hardware processing stage only has the overrun pulse width when the 0 code jumps to 1 or the 1 code jumps to 0, and the pulse width is in the normal code element period in the rest time, the error correction processing is carried out according to the reconstructed baseband signal if the specific decoded result is 01 or 10.
S5, decoding and correcting errors: and acquiring a reconstructed first baseband signal corresponding to the fuzzy decoded position information, decoding and updating the fuzzy decoding.
As shown in fig. 4, the step reads the position information of the fuzzy decoding in the pre-decoding step, reads the reconstructed pulse width information according to the position information to the same position of the baseband 1 reconstructed in the baseband reconstruction step, decodes the partial information, and replaces and updates the fuzzy decoding at the corresponding position in the pre-decoding step of the baseband 1, thereby completing the decoding and error correction functions.
In the decoding and error correcting step, the baseband pulse width information of different decoding parts is reanalyzed by comparing with the reconstructed baseband decoding information, then which path of decoding information has the highest confidence coefficient is determined, and the decoding output is updated.
The core of the decoding method of the invention comprises two parts: 1. chopping is carried out on the processing of the intermediate frequency carrier on a hardware circuit, so that the generation of two paths of baseband signals is realized, and a generation circuit is used for ensuring that the time delay between two paths of baseband signals is within half a code element period of FM0 coding, so that the time base alignment is conveniently carried out by the following method; 2. the baseband signals with complete duty ratio information and complete pulse edge information are processed, and the processed standard is adjusted according to the FM0 coding code element rate to reconstruct the baseband signals. By the method, the generation of two paths of baseband signals can be realized only by processing the signals of the mirror image path in intermediate frequency processing, the scheme is simple, and the increase of hardware cost can not be caused; the communication load is not increased, the method is low in implementation complexity, a CPU (central processing unit) of a serial processing mechanism or a simple FPGA (field programmable gate array) can be implemented, and the manufacturing cost of equipment is controlled; compared with the conventional method, the RSU decoding sensitivity is improved by 10dB to 15dB, the communication distance is directly improved by 1.5-2 times, and the performance index requirement of a high-cost hardware scheme can be met.
Example 2
The invention is a decoding device of FM0 coding based on backward error correction mechanism proposed for station type RSU of low cost radio frequency scheme, the whole structure of the device is shown in figure 5, the device includes the following 5 modules:
a two-way baseband generating module 501, configured to generate a first baseband signal and a second baseband signal, where duty cycle information of the first baseband signal is complete, and pulse edge information of the second baseband signal is complete;
a frame synchronization module 502, configured to generate a frame synchronization signal and a decoding start signal by detecting the feature sequences of the first baseband signal and the second baseband signal, and start a time-base counter;
a baseband reconstructing module 503, configured to reconstruct the first baseband signal according to the pulse width information of the first baseband signal and the second baseband signal;
a predecoding module 504, configured to perform predecoding and fuzzy decoding on the first baseband signal according to whether a pulse width of the first baseband signal conforms to an FM0 encoding rule;
and a decoding error correction module 505, configured to acquire the reconstructed first baseband signal corresponding to the position information of the blur decoding, perform decoding, and update the blur decoding.
The embodiment of the present application further provides an electronic device corresponding to the decoding method based on the backward error correction mechanism provided in the foregoing embodiment, so as to execute the above decoding method based on the backward error correction mechanism. The embodiments of the present application are not limited.
Please refer to fig. 6, which illustrates a schematic diagram of an electronic device according to some embodiments of the present application. As shown in fig. 6, the electronic device 2 includes: the system comprises a processor 200, a memory 201, a bus 202 and a communication interface 203, wherein the processor 200, the communication interface 203 and the memory 201 are connected through the bus 202; the memory 201 stores a computer program that can be executed on the processor 200, and the processor 200 executes the decoding method based on the backward error correction mechanism provided by any one of the foregoing embodiments when executing the computer program.
The Memory 201 may include a high-speed Random Access Memory (RAM) and may further include a non-volatile Memory (non-volatile Memory), such as at least one disk Memory. The communication connection between the network element of the system and at least one other network element is realized through at least one communication interface 203 (which may be wired or wireless), and the internet, a wide area network, a local network, a metropolitan area network, and the like may be used.
The processor 200 may be an integrated circuit chip having signal processing capabilities. In implementation, the steps of the above method may be performed by integrated logic circuits of hardware or instructions in the form of software in the processor 200. The Processor 200 may be a general-purpose Processor, and includes a Central Processing Unit (CPU), a Network Processor (NP), and the like; but may also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), an off-the-shelf programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components. The various methods, steps, and logic blocks disclosed in the embodiments of the present application may be implemented or performed. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like. The steps of the method disclosed in connection with the embodiments of the present application may be directly implemented by a hardware decoding processor, or implemented by a combination of hardware and software modules in the decoding processor. The software module may be located in ram, flash memory, rom, prom, or eprom, registers, etc. storage media as is well known in the art. The storage medium is located in the memory 201, and the processor 200 reads the information in the memory 201 and completes the steps of the method in combination with the hardware thereof.
The electronic device provided by the embodiment of the present application and the decoding method based on the backward error correction mechanism provided by the embodiment of the present application have the same inventive concept and the same beneficial effects as the method adopted, operated or implemented by the electronic device.
Referring to fig. 7, the illustrated computer-readable storage medium is an optical disc 30, on which a computer program (i.e., a program product) is stored, and when the computer program is executed by a processor, the computer program will execute the decoding method based on the backward error correction mechanism provided in any of the foregoing embodiments.
It should be noted that examples of the computer-readable storage medium may also include, but are not limited to, a phase change memory (PRAM), a Static Random Access Memory (SRAM), a Dynamic Random Access Memory (DRAM), other types of Random Access Memories (RAM), a Read Only Memory (ROM), an Electrically Erasable Programmable Read Only Memory (EEPROM), a flash memory, or other optical and magnetic storage media, which are not described in detail herein.
The computer-readable storage medium provided by the above-mentioned embodiment of the present application and the decoding method based on the backward error correction mechanism provided by the embodiment of the present application have the same beneficial effects as the method adopted, run or implemented by the application program stored in the computer-readable storage medium.
It should be noted that:
the methods and displays presented herein are not inherently related to any particular computer, virtual machine, or other apparatus. Various general purpose devices may also be used with the teachings herein. The required structure for constructing an arrangement of this type will be apparent from the description above. Moreover, this application is not intended to refer to any particular programming language. It will be appreciated that a variety of programming languages may be used to implement the teachings of the present application as described herein, and any descriptions of specific languages are provided above to disclose the best modes of the present application.
In the description provided herein, numerous specific details are set forth. However, it is understood that embodiments of the application may be practiced without these specific details. In some instances, well-known methods, structures and techniques have not been shown in detail in order not to obscure an understanding of this description.
Similarly, it should be appreciated that in the foregoing description of exemplary embodiments of the application, various features of the application are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the application and aiding in the understanding of one or more of the various inventive aspects. However, the disclosed method should not be interpreted as reflecting an intention that: this application is intended to cover such departures from the present disclosure as come within known or customary practice in the art to which this invention pertains. Rather, as the following claims reflect, inventive aspects lie in less than all features of a single foregoing disclosed embodiment. Thus, the claims following the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of this application.
Those skilled in the art will appreciate that the modules in the devices in an embodiment may be adaptively changed and arranged in one or more devices different from the embodiment. The modules or units or components in the embodiments may be combined into one module or unit or component, and furthermore, may be divided into a plurality of sub-modules or sub-units or sub-components. All of the features disclosed in this specification (including any accompanying claims, abstract and drawings), and all of the processes or elements of any method or apparatus so disclosed, may be combined in any combination, except combinations where at least some of such features and/or processes or elements are mutually exclusive. Each feature disclosed in this specification (including any accompanying claims, abstract and drawings) may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise.
Moreover, those of skill in the art will understand that although some embodiments described herein include some but not other features included in other embodiments, combinations of features of different embodiments are meant to be within the scope of the application and form different embodiments. For example, in the following claims, any of the claimed embodiments may be used in any combination.
Various component embodiments of the present application may be implemented in hardware, or in software modules running on one or more processors, or in a combination thereof. Those skilled in the art will appreciate that a microprocessor or Digital Signal Processor (DSP) may be used in practice to implement some or all of the functions of some or all of the components in the creation apparatus of a virtual machine according to embodiments of the present application. The present application may also be embodied as apparatus or device programs (e.g., computer programs and computer program products) for performing a portion or all of the methods described herein. Such programs implementing the present application may be stored on a computer readable medium or may be in the form of one or more signals. Such a signal may be downloaded from an internet website or provided on a carrier signal or in any other form.
It should be noted that the above-mentioned embodiments illustrate rather than limit the application, and that those skilled in the art will be able to design alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps not listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The application may be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed computer. In the unit claims enumerating several means, several of these means may be embodied by one and the same item of hardware. The usage of the words first, second and third, etcetera do not indicate any ordering. These words may be interpreted as names.
The above description is only for the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (9)
1. A decoding method based on a backward error correction mechanism, the method comprising:
processing the signal of the mirror image channel to generate a first baseband signal and a second baseband signal, wherein the duty ratio information of the first baseband signal is complete, and the pulse edge information of the second baseband signal is complete;
generating a frame synchronization signal and a decoding start signal by detecting the characteristic sequences of the first baseband signal and the second baseband signal, and starting a time base counter;
reconstructing the first baseband signal according to the pulse width information of the first baseband signal and the second baseband signal, including: if the pulse width of the first baseband signal is lower than a first threshold value, combining the pulse width of the first baseband signal with the pulse width adjacent to the pulse width of the first baseband signal; if the pulse width of the first baseband signal is higher than a second threshold value, acquiring the corresponding pulse width of a second baseband signal according to the time base counter; updating the pulse width of the first baseband signal according to the pulse width of the corresponding second baseband signal;
according to whether the pulse width of the first baseband signal accords with an FM0 coding rule or not, performing pre-decoding and fuzzy decoding on the first baseband signal;
and acquiring a reconstructed first baseband signal corresponding to the fuzzy decoded position information, decoding and updating the fuzzy decoding.
2. The method of claim 1,
and generating the first baseband signal and the second baseband signal by controlling a chopper level threshold of a comparator of the intermediate frequency processing circuit.
3. The method according to claim 1 or 2,
the time delay between the first baseband signal and the second baseband signal is within one half symbol period of the FM0 encoding.
4. The method of claim 1,
the time base counter is used for synchronizing the first baseband signal and the second baseband signal and for judging timeout.
5. The method of claim 1,
pre-decoding and fuzzy decoding the first baseband signal according to whether the pulse width of the first baseband signal conforms to the FM0 coding rule, comprising:
predecoding the first baseband signal according to the condition that the pulse width of the first baseband signal accords with an FM0 coding rule;
and according to the fact that the pulse width of the first baseband signal does not accord with the FM0 coding rule, combining the pulse width quantities before and after the pulse width which does not accord with the FM0 coding rule until the total pulse width quantity after combination is integral multiple of the width of the FM0 code element, carrying out fuzzy decoding on the combined pulse width, and recording the position of the fuzzy decoding.
6. The method of claim 1,
the ambiguous decoding is a predicted symbol comprising 01 and 10.
7. An apparatus for decoding based on a backward error correction mechanism, the apparatus comprising;
the double-path baseband generation module is used for processing the signal of the mirror image channel to generate a first baseband signal and a second baseband signal, wherein the duty ratio information of the first baseband signal is complete, and the pulse edge information of the second baseband signal is complete;
the frame synchronization module is used for generating a frame synchronization signal and a decoding start signal by detecting the characteristic sequences of the first baseband signal and the second baseband signal and starting a time base counter;
a baseband reconstruction module, configured to reconstruct the first baseband signal according to pulse width information of the first baseband signal and the second baseband signal, including: if the pulse width of the first baseband signal is lower than a first threshold value, combining the pulse width of the first baseband signal and the pulse width adjacent to the pulse width of the first baseband signal; if the pulse width of the first baseband signal is higher than a second threshold value, acquiring the corresponding pulse width of a second baseband signal according to the time base counter; updating the pulse width of the first baseband signal according to the pulse width of the corresponding second baseband signal;
the pre-decoding module is used for performing pre-decoding and fuzzy decoding on the first baseband signal according to whether the pulse width of the first baseband signal conforms to the FM0 coding rule or not;
and the decoding error correction module is used for acquiring the reconstructed first baseband signal corresponding to the fuzzy decoding position information, decoding and updating the fuzzy decoding.
8. An electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, wherein the processor executes the computer program to implement the method of any one of claims 1-6.
9. A computer-readable storage medium, on which a computer program is stored, characterized in that the program is executed by a processor to implement the method according to any of claims 1-6.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101273563A (en) * | 2005-09-26 | 2008-09-24 | 讯宝科技公司 | Method and apparatus for preamble synchronization in wireless radio frequency identification (RFID) systems |
| CN106921462A (en) * | 2015-12-25 | 2017-07-04 | 航天信息股份有限公司 | The method and apparatus decoded to FM0 codings |
| CN107818279A (en) * | 2017-11-03 | 2018-03-20 | 武汉万集信息技术有限公司 | A kind of coding/decoding method and device for RFID reader |
| CN110380821A (en) * | 2019-07-15 | 2019-10-25 | 西安电子科技大学 | A kind of RFID answer signal decoding system and method based on machine learning |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7991080B2 (en) * | 2006-07-20 | 2011-08-02 | Broadcom Corporation | RFID decoding subsystem with decode module |
| JP2011053057A (en) * | 2009-09-01 | 2011-03-17 | Seiko Epson Corp | Time correction circuit and electronic device |
-
2020
- 2020-12-30 CN CN202011619853.5A patent/CN112787755B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101273563A (en) * | 2005-09-26 | 2008-09-24 | 讯宝科技公司 | Method and apparatus for preamble synchronization in wireless radio frequency identification (RFID) systems |
| CN106921462A (en) * | 2015-12-25 | 2017-07-04 | 航天信息股份有限公司 | The method and apparatus decoded to FM0 codings |
| CN107818279A (en) * | 2017-11-03 | 2018-03-20 | 武汉万集信息技术有限公司 | A kind of coding/decoding method and device for RFID reader |
| CN110380821A (en) * | 2019-07-15 | 2019-10-25 | 西安电子科技大学 | A kind of RFID answer signal decoding system and method based on machine learning |
Non-Patent Citations (2)
| Title |
|---|
| ETC中FM0解码器的设计;姚渭箐等;《电子设计工程》;20110505(第09期);全文 * |
| 一种基于维特比解码的超高频RFID读写器解码器设计;王贺等;《复旦学报(自然科学版)》;20170615(第03期);全文 * |
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