CN112786455A - Embedded type packaging modular preparation method - Google Patents
Embedded type packaging modular preparation method Download PDFInfo
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- CN112786455A CN112786455A CN201911085676.4A CN201911085676A CN112786455A CN 112786455 A CN112786455 A CN 112786455A CN 201911085676 A CN201911085676 A CN 201911085676A CN 112786455 A CN112786455 A CN 112786455A
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 18
- 238000002360 preparation method Methods 0.000 title claims abstract description 6
- 239000000463 material Substances 0.000 claims abstract description 77
- 239000000758 substrate Substances 0.000 claims abstract description 56
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 27
- 229910052802 copper Inorganic materials 0.000 claims abstract description 27
- 239000010949 copper Substances 0.000 claims abstract description 27
- 238000003825 pressing Methods 0.000 claims abstract description 17
- 229910052751 metal Inorganic materials 0.000 claims abstract description 16
- 239000002184 metal Substances 0.000 claims abstract description 16
- 238000007747 plating Methods 0.000 claims abstract description 14
- 238000010030 laminating Methods 0.000 claims abstract description 4
- 239000010410 layer Substances 0.000 claims description 37
- 238000000034 method Methods 0.000 claims description 32
- 238000004519 manufacturing process Methods 0.000 claims description 17
- 239000000919 ceramic Substances 0.000 claims description 12
- 238000005553 drilling Methods 0.000 claims description 7
- 238000002844 melting Methods 0.000 claims description 4
- 230000008018 melting Effects 0.000 claims description 4
- 238000004080 punching Methods 0.000 claims description 4
- 238000005530 etching Methods 0.000 claims description 3
- 239000011247 coating layer Substances 0.000 claims description 2
- 230000017525 heat dissipation Effects 0.000 abstract description 10
- 230000003071 parasitic effect Effects 0.000 abstract description 4
- 239000004065 semiconductor Substances 0.000 description 5
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 229910052709 silver Inorganic materials 0.000 description 3
- 239000004332 silver Substances 0.000 description 3
- 229910010293 ceramic material Inorganic materials 0.000 description 2
- 238000012536 packaging technology Methods 0.000 description 2
- 238000005245 sintering Methods 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- 229910052582 BN Inorganic materials 0.000 description 1
- PZNSFCLAULLKQX-UHFFFAOYSA-N Boron nitride Chemical compound N#B PZNSFCLAULLKQX-UHFFFAOYSA-N 0.000 description 1
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 241001391944 Commicarpus scandens Species 0.000 description 1
- 238000007792 addition Methods 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000011231 conductive filler Substances 0.000 description 1
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 1
- 230000032798 delamination Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 229910021389 graphene Inorganic materials 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000010295 mobile communication Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000008520 organization Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000005507 spraying Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
An embedded package modular preparation method comprises the following steps: pressing the chip and the component into a first material to prepare a first prefabricated part; arranging at least two first through holes in each first material area, and arranging conductive connection on the first prefabricated parts provided with the first through holes to form a first substrate; pressing at least one multi-layer plate into a second material to prepare a second prefabricated member; the multilayer plate comprises a first metal layer, an insulating layer and a second metal layer which are arranged from top to bottom; arranging a conductive connection on the second prefabricated part to form a second substrate; and placing the second substrate, the first substrate and the second substrate from top to bottom, and laminating to obtain the embedded packaging device. The invention solves the technical problems of limited heat dissipation and electric conduction capability and overlarge parasitic inductance of a copper plating layer caused by limited thickness and overlong electric conduction line of the traditional embedded package, and improves key performances such as heat conductivity, dielectric property and the like, reliability, electric conductivity and the like.
Description
Technical Field
The invention relates to the technical field of semiconductor chip packaging, in particular to an embedded packaging method
Background
The power electronic technology is a technology for converting input direct current or alternating current electric energy into a required electric energy form and outputting the electric energy form, and is realized by controlling switches of a plurality of groups of power semiconductor chips. In recent years, the power electronic technology is driven by markets of hot door applications such as electric vehicles, high-speed rails, mobile communication and the like to develop at a high speed, so that the performance of a power semiconductor chip is continuously improved, which is mainly reflected in that: the power density is continuously improved, the switching frequency is gradually improved, and the chip volume is greatly reduced. However, a single power chip cannot realize any function, a certain substrate material is required to support and dissipate heat of the chip, leads are used to interconnect each pole of the power chip with a power supply and a power utilization end, and a certain adhesive material is required to fix each component, which is a semiconductor packaging technology. The package is used as a bridge for connecting materials, chips, devices and applications, and directly provides stable electromagnetic, mechanical and heat dissipation environments for the chips, so that the chips stably and normally work, and the functional range of the chips can be realized and expanded through package integration.
The currently common semiconductor package forms include two broad categories: surface-mounted and embedded. Compared with the traditional packaging technology of surface mounting, the embedded package has the advantages of reducing the packaging thickness, improving the electrical performance, improving the heat dissipation performance, realizing leadless interconnection, 3D stacked packaging, electromagnetic protection and the like. In a conventional embedded package, a chip is embedded in a substrate, a terminal on the surface of the chip is exposed by laser drilling or the like, a copper plating is used to fill a space, and finally, a wire (RDL) is re-wired on the surface to lead out a terminal (e.g., C, E, G pole of an IGBT) of the chip. However, this conventional embedded packaging scheme is very limited, including: the copper plating process has limited thickness, resulting in limited heat dissipation and electrical conductivity of the copper plating layer. If a thicker copper layer is plated, the process time is greatly increased, and the cost cannot be borne by the industry. Meanwhile, the surface of the copper layer is a thin solder mask layer, so that the dielectric property is poor, and the packaging is easy to break down under high voltage, thereby causing failure.
Aiming at the problem of the conventional embedded packaging scheme, a research organization proposes 'ceramic embedding', namely a chip is clamped by an upper core plate and a lower core plate (A and B), a ceramic material is embedded at the contact position of the A and the B and the chip, and the ceramic material has high thermal conductivity (20-180W/Km) and high dielectric property (1.5 kV/mm). But with other derived problems that cannot be ignored: the ceramic embedded package needs copper plating on the front surface and the back surface of the ceramic to realize a conductive circuit, but the bonding force of a copper-plated material and the ceramic is poor, and the delamination failure is easy to occur during high-temperature and low-temperature circulating work. The problem of small thickness of the copper plating layer is still not solved. In addition, most of the current embedded packages are only embedded with chips, and other capacitance resistors and control units are still surface-mounted, so that the wiring between the components is too long, and the parasitic inductance is too large.
Disclosure of Invention
In order to solve the technical problems of limited heat dissipation and electric conduction capability and overlarge parasitic inductance of a copper plating layer caused by limited thickness and overlong electric conduction circuit of the traditional embedded package, the invention provides a modularized preparation method of an embedded package, which comprises the following steps:
s1: pressing the chip and the component into a first material to prepare a first prefabricated member, wherein the first prefabricated member comprises at least two first material areas which are connected at intervals, at least one chip and at least one component;
s2: arranging at least two first through holes in each first material area, and arranging conductive connection on the first prefabricated part provided with the first through holes to form a first substrate;
s3: pressing at least one multi-layer plate into a second material to prepare a second prefabricated member; the multilayer plate comprises a first metal layer, an insulating layer and a second metal layer which are arranged from top to bottom;
s4: arranging a conductive connection on the second prefabricated part to form a second substrate;
s5: and placing the second substrate, the first substrate and the second substrate from top to bottom, and laminating to obtain the embedded packaging device.
Preferably, the first metal layer and the second metal layer are made of copper, and the insulating layer is made of ceramic; the first material and the second material are prepreg or FR4 material or BT material or EMC material.
Preferably, the method for pressing the chip and the component into the first material comprises the following steps:
punching at least one third through hole in the first material according to the sizes of the chip and the component, embedding the at least one chip and the at least one component into the first material, and controlling the temperature and the pressure to solidify and mold the first material and the chip and the component embedded into the first material;
the method for pressing at least one multi-layer plate material into the second material comprises the following steps:
punching at least one fourth through hole in the second material according to the size of the at least one multilayer plate, embedding the at least one multilayer plate into the second material, and controlling the temperature and the pressure to enable the second material and the multilayer plate embedded into the second material to be solidified and molded.
Preferably, the method for pressing the chip and the component into the first material comprises the following steps:
melting the first material, wrapping at least one chip and at least one component by using the melted first material, and solidifying to form a first prefabricated part;
the method for pressing at least one multi-layer plate material into the second material comprises the following steps:
and melting the second material, wrapping at least a plurality of layers of plates by using the melted first material, and solidifying to form a second prefabricated member.
Preferably, the method of preparing at least one first via hole comprises: laser drilling, mechanical drilling, etching.
Preferably, the method for providing the conductive connection comprises the following steps: arranging conductive metal in the first through hole and the second through hole; coating layers are arranged on the upper surface and the lower surface of the first prefabricated part and the upper surface or the lower surface of the second prefabricated part; and manufacturing a preset pattern on the plating layer.
Preferably, the inner wall of the first through hole or the whole area in the first through hole is filled with metal copper, or a plurality of copper columns with the same size as the first through hole are arranged in the first through hole.
Preferably, the S5 includes: placing a second substrate, at least one first prepreg, a first substrate, at least one second prepreg and a second substrate from top to bottom; pressing the structure to form an embedded packaging device; and at least one through hole is formed in the first prepreg and the second prepreg according to the positions of the first substrate and the second substrate.
According to the invention, the chip is directly embedded into the PCB substrate, the original packaging mode of mounting the chip on the PCB substrate is replaced, the thickness of the heat dissipation metal plate directly contacted with the chip is increased, the key performances such as heat conductivity, dielectric property and the like, reliability, electric conductivity and the like are improved, the connection strength is improved by adopting a sintering process, and the heat dissipation capability is greatly improved.
Drawings
FIG. 1 is a side view of a chip and a device that provide a modular manufacturing method for embedded packages according to an embodiment
FIG. 2 is a side view of a copper-clad ceramic substrate for providing an embedded package modular manufacturing method according to an embodiment
FIG. 3 is a side view of a multi-layer board providing an embedded package modular manufacturing method according to an embodiment
FIG. 4 is a side view of a first preform for providing a modular manufacturing process for embedded packages according to one embodiment
FIG. 5 is a side view of a perforated first preform for providing a modular manufacturing process for embedded packages, according to an embodiment
FIG. 6 is a side view of a first substrate providing a modular manufacturing method for embedded packages according to an embodiment
FIG. 7 is a side view of a second substrate providing a modular manufacturing method for embedded packages according to an embodiment
FIG. 8 is a side view of a second substrate pressed against a first substrate to provide a modular manufacturing method for embedded packages according to an embodiment
FIG. 9 is a side view of an embedded packaged device that provides a modular manufacturing method for embedded packages, according to an embodiment
Detailed Description
Reference will now be made in detail to the embodiments of the present invention, the following examples of which are intended to be illustrative only and are not to be construed as limiting the scope of the invention.
Example one
The embodiment provides a method for manufacturing an embedded package module, as shown in fig. 1 to 7.
Fig. 1 shows a side view of the chip 11 and the component 20 used.
As shown in fig. 2, the copper-clad ceramic substrates 1 and 5 are prepared by processes such as DBC, AMB, DPC, etc., wherein 2 is a ceramic layer, which can be a novel ceramic of alumina, aluminum nitride, silicon carbide and high thermal conductive filler (such as graphene, boron nitride, etc.); 3 is the first copper layer for pasting the chip special end, and it is according to electrically conductive, interconnection and heat dissipation demand, designs specific copper layer pattern and thickness, and 4 is the second copper layer, outwards contacts the radiator during encapsulation.
As shown in fig. 3-4, in the laminating step, the chip 11 and the component 20 are pressed into the material 21 under certain temperature and pressure conditions, the material of 21 is prepreg (pp material) or other FR4 material or BT material or EMC material, holes can be punched at corresponding positions of the material 21 according to the sizes of the chip 11 and the component 20, so that the chip 11 and the component 20 can be just embedded into the material 21, and then the whole is cured and molded through temperature and pressure control. In the same manner, the copper-clad ceramic substrate was pressed into the material 6.
As shown in fig. 5, 6 holes are drilled in the area of the material 21 by laser drilling or mechanical drilling or etching, wherein laser alignment or the like is used to ensure accurate alignment.
As shown in fig. 6-7, the plating layer 22 is coated on the exposed surface of the chip, component and molded material 21 by a copper plating process, and then the overall height is made uniform by a grinding process. The copper plating process may include electroless plating, electroplating, sputtering, physical vapor deposition, chemical vapor deposition, and other material deposition techniques. A desired pattern is formed on the plating layer 7 by chemical etching, photolithography, or the like, to form a first substrate 8. Using a similar or identical method, a second substrate 9 is prepared.
As shown in fig. 8, a first substrate is used as the middle substrate, a second substrate is used as the upper substrate and the lower substrate, and the surface of the upper substrate and the surface of the lower substrate are coated with the mounting material 10. Mounting material 10 may be: traditional soldering paste, soldering lug, sintered silver paste, solidified silver paste, sintered silver film, sintered copper paste, sintered copper film, sintered copper prefabricated part and the like; methods of placing the material 10 on the first substrate surface may include screen printing, dispensing, coating, spraying, automated placement machine transfer of preforms, and the like. The upper and lower substrates 8, 9 are placed on the upper and lower sides of the intermediate substrate 27, respectively, and a prepreg 24, 24 is added between the upper substrate 9 and the intermediate substrate 27, and holes are punched at specific positions according to the sizes of the chip and the copper-clad substrate. A prepreg 25, 25 is added between the lower substrate 8 and the intermediate layer 27, and holes are punched at specific positions according to the sizes of the chip and the copper-clad substrate. And finally, pressing and integrating the materials of all layers into a whole by using a curing process to form the final embedded packaging device.
In the embodiment, a copper plating process of a copper-clad substrate is adopted, copper and ceramic are welded, copper and copper are directly bonded, and each surface has strong bonding strength; according to the invention, the parasitic inductance is reduced by embedding the control unit, the capacitor, the resistor, the inductor and other passive devices; according to the invention, the chip is directly embedded into the PCB substrate, the original packaging mode of mounting the chip on the PCB substrate is replaced, the thickness of the heat dissipation metal plate directly contacted with the chip is increased, the key performances such as heat conductivity, dielectric property and the like, reliability, electric conductivity and the like are improved, the connection strength is improved by adopting a sintering process, and the heat dissipation capability is greatly improved.
Although exemplary embodiments of the present invention have been described for illustrative purposes, those skilled in the art will appreciate that various modifications, additions, substitutions and the like can be made in form and detail without departing from the scope and spirit of the invention as disclosed in the accompanying claims, all of which are intended to fall within the scope of the claims, and that various steps in the various sections and methods of the claimed product can be combined together in any combination. Therefore, the description of the embodiments disclosed in the present invention is not intended to limit the scope of the present invention, but to describe the present invention. Accordingly, the scope of the present invention is not limited by the above embodiments, but is defined by the claims or their equivalents.
Claims (8)
1. An embedded package modular preparation method is characterized by comprising the following steps:
s1: pressing the chip and the component into a first material to prepare a first prefabricated member, wherein the first prefabricated member comprises at least two first material areas which are connected at intervals, at least one chip and at least one component;
s2: arranging at least two first through holes in each first material area, and arranging conductive connection on the first prefabricated part provided with the first through holes to form a first substrate;
s3: pressing at least one multi-layer plate into a second material to prepare a second prefabricated member; the multilayer plate comprises a first metal layer, an insulating layer and a second metal layer which are arranged from top to bottom;
s4: arranging a conductive connection on the second prefabricated part to form a second substrate;
s5: and placing the second substrate, the first substrate and the second substrate from top to bottom, and laminating to obtain the embedded packaging device.
2. The method for manufacturing an embedded package module according to claim 1, wherein the first metal layer and the second metal layer are made of copper, and the insulating layer is made of ceramic; the first material and the second material are prepreg or FR4 material or BT material or EMC material.
3. The method for manufacturing the embedded package module according to claim 1, wherein the method for pressing the chip and the component into the first material comprises the following steps:
punching at least one third through hole in the first material according to the sizes of the chip and the component, embedding the at least one chip and the at least one component into the first material, and controlling the temperature and the pressure to solidify and mold the first material and the chip and the component embedded into the first material;
the method for pressing at least one multi-layer plate material into the second material comprises the following steps:
punching at least one fourth through hole in the second material according to the size of the at least one multilayer plate, embedding the at least one multilayer plate into the second material, and controlling the temperature and the pressure to enable the second material and the multilayer plate embedded into the second material to be solidified and molded.
4. The method for manufacturing the embedded package module according to claim 1, wherein the method for pressing the chip and the component into the first material comprises the following steps:
melting the first material, wrapping at least one chip and at least one component by using the melted first material, and solidifying to form a first prefabricated part;
the method for pressing at least one multi-layer plate material into the second material comprises the following steps:
and melting the second material, wrapping at least a plurality of layers of plates by using the melted first material, and solidifying to form a second prefabricated member.
5. The method of making an embedded package modular according to claim 1, wherein the method of making at least one first via comprises: laser drilling, mechanical drilling, etching.
6. The method for preparing the embedded packaging module according to claim 1, wherein the method for providing the conductive connection comprises the following steps: arranging conductive metal in the first through hole; coating layers are arranged on the upper surface and the lower surface of the first prefabricated part and the upper surface or the lower surface of the second prefabricated part; and manufacturing a preset pattern on the plating layer.
7. The method for preparing the embedded package module according to claim 6, wherein the inner wall of the first through hole or the whole area in the first through hole is filled with copper metal, or a plurality of copper pillars with the same size as the first through hole are arranged in the first through hole.
8. The method for modular preparation of embedded packages according to claim 1, wherein the S5 comprises: placing a second substrate, at least one first prepreg, a first substrate, at least one second prepreg and a second substrate from top to bottom; pressing the structure to form an embedded packaging device; and at least one through hole is formed in the first prepreg and the second prepreg according to the positions of the first substrate and the second substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911085676.4A CN112786455A (en) | 2019-11-07 | 2019-11-07 | Embedded type packaging modular preparation method |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201911085676.4A CN112786455A (en) | 2019-11-07 | 2019-11-07 | Embedded type packaging modular preparation method |
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| CN112786455A true CN112786455A (en) | 2021-05-11 |
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| CN201911085676.4A Pending CN112786455A (en) | 2019-11-07 | 2019-11-07 | Embedded type packaging modular preparation method |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116072558A (en) * | 2023-02-20 | 2023-05-05 | 纳宇半导体材料(宁波)有限责任公司 | Novel embedded packaging structure and preparation method thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5843251A (en) * | 1989-03-09 | 1998-12-01 | Hitachi Chemical Co., Ltd. | Process for connecting circuits and adhesive film used therefor |
| CN107078110A (en) * | 2017-01-22 | 2017-08-18 | 乐健科技（珠海）有限公司 | IGBT modules and its manufacture method |
| CN109727969A (en) * | 2018-12-29 | 2019-05-07 | 华进半导体封装先导技术研发中心有限公司 | A kind of substrate flush type power device packaging structure and its manufacturing method |
| CN109841501A (en) * | 2019-03-12 | 2019-06-04 | 深圳第三代半导体研究院 | A kind of high quality semi-polarity two-dimensional ultrathin indium nitrogen/gallium nitrogen laminated construction and preparation method thereof |
-
2019
- 2019-11-07 CN CN201911085676.4A patent/CN112786455A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5843251A (en) * | 1989-03-09 | 1998-12-01 | Hitachi Chemical Co., Ltd. | Process for connecting circuits and adhesive film used therefor |
| CN107078110A (en) * | 2017-01-22 | 2017-08-18 | 乐健科技（珠海）有限公司 | IGBT modules and its manufacture method |
| CN109727969A (en) * | 2018-12-29 | 2019-05-07 | 华进半导体封装先导技术研发中心有限公司 | A kind of substrate flush type power device packaging structure and its manufacturing method |
| CN109841501A (en) * | 2019-03-12 | 2019-06-04 | 深圳第三代半导体研究院 | A kind of high quality semi-polarity two-dimensional ultrathin indium nitrogen/gallium nitrogen laminated construction and preparation method thereof |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116072558A (en) * | 2023-02-20 | 2023-05-05 | 纳宇半导体材料(宁波)有限责任公司 | Novel embedded packaging structure and preparation method thereof |
| CN116072558B (en) * | 2023-02-20 | 2023-09-29 | 纳宇半导体材料(宁波)有限责任公司 | Novel embedded packaging structure and preparation method thereof |
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