CN112782550A - Nanosecond transmission delay testing device and method - Google Patents
Nanosecond transmission delay testing device and method Download PDFInfo
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- CN112782550A CN112782550A CN201911064829.7A CN201911064829A CN112782550A CN 112782550 A CN112782550 A CN 112782550A CN 201911064829 A CN201911064829 A CN 201911064829A CN 112782550 A CN112782550 A CN 112782550A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2882—Testing timing characteristics
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
- G01R1/30—Structural combination of electric measuring instruments with basic electronic circuits, e.g. with amplifier
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R35/00—Testing or calibrating of apparatus covered by the other groups of this subclass
- G01R35/005—Calibrating; Standards or reference devices, e.g. voltage or resistance standards, "golden" references
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Abstract
A nanosecond transmission delay testing device and method can convert transmission delay into voltage test by building a combination of a rising edge early-stage processing circuit, a falling edge early-stage processing circuit and a synthesis post-processing circuit, thereby realizing nanosecond transmission delay testing, for example, transmission delay testing successfully carried out on SGM48000 chips and the like with the transmission delay magnitude of both the rising edge and the falling edge being 10-20 ns.
Description
Technical Field
The invention relates to a transmission delay testing technology of a chip circuit, in particular to a nanosecond transmission delay testing device and a nanosecond transmission delay testing method, which can convert transmission delay into voltage test by building a combination of a rising edge early-stage processing circuit, a falling edge early-stage processing circuit and a synthesis post-processing circuit, thereby realizing nanosecond transmission delay testing, for example, the transmission delay testing of SGM48000 chips and the like with the transmission delay magnitude of both the rising edge and the falling edge being 10-20ns is successfully realized.
Background
For the transmission delay test of the chip circuit, the time is generally directly measured by a tester. However, in practical work, the inventor finds that time measurement cannot be realized by directly using a tester for nanosecond transmission delay test, for example, for an SGM48000 chip with transmission delay magnitudes of both rising edge and falling edge of 10-20ns, the test cannot be performed in mass production, that is, the test cannot be performed by using the tester. The inventor thinks that if a combination of a rising edge early-stage processing circuit, a falling edge early-stage processing circuit and a synthesis post-processing circuit is built, transmission delay can be converted into voltage test, and nanosecond transmission delay test is realized. In view of the above, the present inventors have completed the present invention.
Disclosure of Invention
Aiming at the defects or shortcomings in the prior art, the invention provides a nanosecond transmission delay testing device and method, which can convert transmission delay into voltage test by building a combination of a rising edge early-stage processing circuit, a falling edge early-stage processing circuit and a synthesis post-processing circuit, thereby realizing nanosecond transmission delay test, for example, transmission delay test carried out on SGM48000 chips with the transmission delay magnitude of both the rising edge and the falling edge being 10-20ns is successfully realized.
The technical scheme of the invention is as follows:
a nanosecond-level transmission delay testing device is characterized by comprising a rising edge early-stage processing circuit and a falling edge early-stage processing circuit, wherein the rising edge early-stage processing circuit and the falling edge early-stage processing circuit are respectively connected with a filter circuit, and the filter circuit is connected with a testing machine through an amplifying circuit.
The rising edge early-stage processing circuit comprises a first comparator and a second comparator, wherein the positive input end of the first comparator is connected with an input waveform end to be detected, the negative input end of the first comparator is connected with an input reference voltage end, the output end of the first comparator is connected with the first input end of an AND gate circuit, the positive input end of the second comparator is connected with an output waveform end to be detected, the negative input end of the second comparator is connected with an output reference voltage end, the output end of the second comparator is connected with the second input end of the AND gate circuit through a first odd number of NOT gate circuits, and the output end of the AND gate circuit is connected with the first input end of the filter circuit.
Falling edge earlier stage processing circuit includes third comparator and fourth comparator, the input waveform end that awaits measuring is connected to the positive input of third comparator, the input reference voltage end is connected to the negative input of third comparator, the first input of NOR gate circuit is connected to the output of third comparator, the output waveform end that awaits measuring is connected to the positive input of fourth comparator, the output reference voltage end is connected to the negative input of fourth comparator, the output of fourth comparator passes through the odd number of NOT gate circuit connection the second input of NOR gate circuit, the output of NOR gate circuit is connected the second input of filter circuit.
The first comparator and the third comparator adopt the same entity comparator circuit.
The second comparator and the fourth comparator adopt the same entity comparator circuit.
A nanosecond-level transmission delay test method is characterized by comprising the steps of converting an obliquely upward rising edge IN an input waveform IN to be tested into a vertical rising edge of a waveform A, converting an obliquely upward rising edge IN an output waveform OUT to be tested into a vertical rising edge of a waveform B, converting an obliquely downward falling edge IN the input waveform IN to be tested into a vertical falling edge of the waveform A, converting an obliquely downward falling edge IN the output waveform OUT to be tested into a vertical falling edge of the waveform B, reversing the waveform B into a waveform C, performing logical AND operation on the waveform A and the waveform C to obtain a rising edge transmission delay pulse waveform D, performing logical NOR operation on the waveform A and the waveform C to obtain a falling edge transmission delay pulse waveform H, performing filtering processing on the pulse waveform D and the pulse waveform H to obtain a voltage E, wherein the voltage value of the voltage E is a pulse voltage average value IN transmission delay time, and amplifying the voltage E to obtain a voltage F, and determining the transmission delay time by measuring the voltage value of the voltage F.
The method comprises the steps of inputting an input waveform IN to be detected into a positive input end of a comparator, inputting an input reference voltage Ref _ IN into a negative input end of the comparator, outputting a waveform A by the comparator, inputting an output waveform OUT to be detected into the positive input end of the comparator, inputting an output reference voltage Ref _ OUT into the negative input end of the comparator, outputting a waveform B by the comparator, and generating a waveform C by the waveform B through an odd number of NOT-gate circuits.
And the waveform A and the waveform C generate the rising edge transmission delay pulse waveform D through an AND gate circuit, and the waveform A and the waveform C generate the falling edge transmission delay pulse waveform H through a NOR gate circuit.
The pulse waveform D and the pulse waveform H generate the voltage E through a filter, and the voltage E is amplified by an amplifier to generate the voltage F.
The voltage F is tested by a testing machine, the testing machine is calibrated before testing, the voltage value measured by inputting and outputting the same waveform is the delay error voltage G existing in the testing machine, the value of the voltage F is F ' -G, F ' is a measured value directly obtained by measuring the voltage F by the testing machine, a proportional relation is fitted between the F ' -G and the transmission delay time measured by an actual oscilloscope, and the transmission delay is tested by directly testing a voltage signal on the testing machine according to the proportional relation.
The invention has the following technical effects: according to the nanosecond transmission delay testing device and method, the circuit structure for converting the transmission delay into the voltage test is built, so that the testing machine can effectively test the nanosecond transmission delay, and the problem that the transmission delay test cannot be carried out on the SGM48000 chip in mass production is solved.
Drawings
Fig. 1 is a schematic structural diagram of a nanosecond transmission delay testing device implementing the invention. Fig. 1 includes circuitry for pre-processing the rising and falling edges, respectively (obtaining the rising edge D pulse and the falling edge H pulse), and synthesis post-processing circuitry for filtering, amplifying, and testing into a tester. The rising edge preprocessing circuit comprises a first comparator and a second comparator, a first N NOT gate circuits (N NOT gates are used for increasing transmission delay time and reversing output waveforms, and N is an odd number larger than 1) and a gate circuit. The falling edge early-stage processing circuit comprises a third comparator, a fourth comparator, a second N NOT gate circuit (N NOT gates are used for increasing transmission delay time and reversing output waveforms, and N is an odd number larger than 1) and an NOT gate circuit.
Fig. 2 is a timing diagram of the various nodes in fig. 1. The nodes referred to IN FIG. 2 are Ref _ IN, IN, Ref _ OUT, OUT, A, B, C, D, H, E, F. The abscissa of fig. 2 is time and the ordinate is voltage. The rising edge propagation delay (the rising edge of the waveform IN compared to the rising edge of the waveform OUT) and the falling edge propagation delay (the falling edge of the waveform IN compared to the falling edge of the waveform OUT) are both IN nanoseconds, e.g., 10-20 ns. The waveform a of the a node is obtained by comparing the input waveform IN with the input reference voltage Ref _ IN. The waveform B of the node B is obtained by comparing the output waveform OUT with the output reference voltage Ref _ OUT. Waveform C at node C is the inverse of waveform B. Waveform D is waveform a and waveform C (corresponding to the rising edge propagation delay). And the waveform H is obtained by carrying out NOR operation on the waveform A and the waveform C (corresponding to the falling edge transmission delay). The voltage E is obtained by filtering the pulse signal D and the pulse signal H. Voltage F is an amplification of voltage E (used for testing the value of the voltage by the tester).
Detailed Description
The invention is described below with reference to the accompanying drawings (fig. 1-2).
Fig. 1 is a schematic structural diagram of a nanosecond transmission delay testing device implementing the invention. Fig. 2 is a timing diagram of the various nodes in fig. 1. Referring to fig. 1 and 2, a nanosecond transmission delay testing device includes a rising edge pre-processing circuit and a falling edge pre-processing circuit, where the rising edge pre-processing circuit and the falling edge pre-processing circuit are respectively connected to a filter circuit, and the filter circuit is connected to a testing machine through an amplifying circuit. The rising edge early-stage processing circuit comprises a first comparator and a second comparator, wherein the positive input end (+) of the first comparator is connected with an input waveform end IN to be detected, the negative input end (-) of the first comparator is connected with an input reference voltage end Ref _ IN, the output end of the first comparator is connected with the first input end of an AND gate circuit, the positive input end (+) of the second comparator is connected with an output waveform end OUT to be detected, the negative input end (-) of the second comparator is connected with an output reference voltage end Ref _ OUT, the output end of the second comparator is connected with the second input end of the AND gate circuit through a first odd number of NOT gate circuits, and the output end of the AND gate circuit is connected with the first input end of the filter circuit. The falling edge early-stage processing circuit comprises a third comparator and a fourth comparator, the positive input end (+) of the third comparator is connected with an input waveform end IN to be detected, the negative input end (-) of the third comparator is connected with an input reference voltage end Ref _ IN, the output end of the third comparator is connected with the first input end of an NOR gate circuit, the positive input end (+) of the fourth comparator is connected with an output waveform end OUT to be detected, the negative input end (-) of the fourth comparator is connected with an output reference voltage end Ref _ OUT, the output end of the fourth comparator is connected with the second input end of the NOR gate circuit through odd-numbered NOT gate circuits, and the output end of the NOR gate circuit is connected with the second input end of the filter circuit. The first comparator and the third comparator adopt the same entity comparator circuit. The second comparator and the fourth comparator adopt the same entity comparator circuit.
As shown IN fig. 1 to 2, a nanosecond transmission delay test method includes converting an upward-inclined rising edge IN an input waveform IN to be tested into a vertical rising edge of a waveform a, converting an upward-inclined rising edge IN an output waveform OUT to be tested into a vertical rising edge of a waveform B, converting a downward-inclined falling edge IN the input waveform IN to be tested into a vertical falling edge of the waveform a, converting a downward-inclined falling edge IN the output waveform OUT to be tested into a vertical falling edge of the waveform B, inverting the waveform B into a waveform C, performing a logical and operation on the waveform a and the waveform C to obtain a rising edge transmission delay pulse waveform D, performing a logical nor operation on the waveform a and the waveform C to obtain a falling edge transmission delay pulse waveform H, performing a filtering process on the pulse waveform D and the pulse waveform H to obtain a voltage E, wherein a voltage value of the voltage E is an average value of pulse voltage IN a transmission delay time, and amplifying the voltage E to obtain a voltage F, and determining the transmission delay time by measuring the voltage value of the voltage F. The method comprises the steps of inputting an input waveform IN to be detected into a positive input end of a comparator, inputting an input reference voltage Ref _ IN into a negative input end of the comparator, outputting a waveform A by the comparator, inputting an output waveform OUT to be detected into the positive input end of the comparator, inputting an output reference voltage Ref _ OUT into the negative input end of the comparator, outputting a waveform B by the comparator, and generating a waveform C by the waveform B through an odd number of NOT-gate circuits. And the waveform A and the waveform C generate the rising edge transmission delay pulse waveform D through an AND gate circuit, and the waveform A and the waveform C generate the falling edge transmission delay pulse waveform H through a NOR gate circuit. The pulse waveform D and the pulse waveform H generate the voltage E through a filter, and the voltage E is amplified by an amplifier to generate the voltage F. The voltage F is tested by a testing machine, the testing machine is calibrated before testing, the voltage value measured by inputting and outputting the same waveform is the delay error voltage G existing in the testing machine, the value of the voltage F is F ' -G, F ' is a measured value directly obtained by measuring the voltage F by the testing machine, a proportional relation is fitted between the F ' -G and the transmission delay time measured by an actual oscilloscope, and the transmission delay is tested by directly testing a voltage signal on the testing machine according to the proportional relation.
The working principle of the invention for converting transmission delay into voltage test by building a circuit is described as follows by combining with the figures 1 and 2:
1. the input waveform is compared with Ref _ IN voltage to obtain a waveform A, the output waveform is compared with Ref _ OUT voltage to obtain a waveform B, and Ref _ IN voltage and Ref _ OUT voltage can be properly changed according to actual requirements (Ref _ IN is 50% of IN high level and Ref _ OUT is 50% of OUT high level IN a timing chart);
2. the waveform B passes through N NOT gates to obtain a waveform C, so that the transmission delay time is increased through the NOT gates, and the output waveform is reversed;
3. measuring the transmission delay of the rising edge: sending the waveform A and the waveform C into an AND gate to obtain a waveform D, and converting the transmission delay of the rising edge from IN to OUT into a pulse signal D with the same time;
4. measuring the transmission delay of the falling edge: sending the waveform A and the waveform C into a NOR gate to obtain a waveform D, and converting the transmission delay of the falling edge from IN to OUT into a pulse signal H with the same time;
5. testing the transmission delay of the rising edge, sending the pulse signal D into an RC filter, testing the transmission delay of the falling edge, sending the pulse signal H into the RC filter, and respectively converting the pulse signal into voltage E;
6. after the voltage E is amplified, a testing machine is used for directly testing a voltage signal, and the average value F of the pulse voltage in the corresponding transmission delay time can be obtained;
7. calibration of the equipment before testing is required: the input and the output adopt the same waveform, and the voltage value measured by the testing machine at the moment is the delay error G existing in the equipment;
8. after the delay error of the equipment is removed, the average voltage of the pulse signal in the transmission delay time of the rising edge is F-G;
9. and fitting a proportional relation between the obtained average voltage F-G and the rising edge transmission delay time measured by the oscilloscope actually, so that the voltage signal can be directly tested on a testing machine to test the transmission delay.
It is pointed out here that the above description is helpful for the person skilled in the art to understand the invention, but does not limit the scope of protection of the invention. Any such equivalents, modifications and/or omissions as may be made without departing from the spirit and scope of the invention may be resorted to.
Claims (8)
1. A nanosecond-level transmission delay testing device is characterized by comprising a rising edge early-stage processing circuit and a falling edge early-stage processing circuit, wherein the rising edge early-stage processing circuit and the falling edge early-stage processing circuit are respectively connected with a filter circuit, and the filter circuit is connected with a testing machine through an amplifying circuit.
2. The nanosecond transmission delay testing device according to claim 1, wherein the rising edge pre-processing circuit comprises a first comparator and a second comparator, a positive input terminal of the first comparator is connected to the input waveform terminal to be tested, a negative input terminal of the first comparator is connected to the input reference voltage terminal, an output terminal of the first comparator is connected to a first input terminal of an and circuit, a positive input terminal of the second comparator is connected to the output waveform terminal to be tested, a negative input terminal of the second comparator is connected to the output reference voltage terminal, an output terminal of the second comparator is connected to a second input terminal of the and circuit through a first odd number of not-gate circuits, and an output terminal of the and circuit is connected to the first input terminal of the filter circuit.
3. The nanosecond transmission delay test device according to claim 1, wherein the falling edge pre-processing circuit comprises a third comparator and a fourth comparator, a positive input terminal of the third comparator is connected to the input waveform terminal to be tested, a negative input terminal of the third comparator is connected to the input reference voltage terminal, an output terminal of the third comparator is connected to a first input terminal of the nor circuit, a positive input terminal of the fourth comparator is connected to the output waveform terminal to be tested, a negative input terminal of the fourth comparator is connected to the output reference voltage terminal, an output terminal of the fourth comparator is connected to a second input terminal of the nor circuit through a second odd number of not circuits, and an output terminal of the nor circuit is connected to a second input terminal of the filter circuit.
4. A nanosecond-level transmission delay test method is characterized by comprising the steps of converting an obliquely upward rising edge IN an input waveform IN to be tested into a vertical rising edge of a waveform A, converting an obliquely upward rising edge IN an output waveform OUT to be tested into a vertical rising edge of a waveform B, converting an obliquely downward falling edge IN the input waveform IN to be tested into a vertical falling edge of the waveform A, converting an obliquely downward falling edge IN the output waveform OUT to be tested into a vertical falling edge of the waveform B, reversing the waveform B into a waveform C, performing logical AND operation on the waveform A and the waveform C to obtain a rising edge transmission delay pulse waveform D, performing logical NOR operation on the waveform A and the waveform C to obtain a falling edge transmission delay pulse waveform H, performing filtering processing on the pulse waveform D and the pulse waveform H to obtain a voltage E, wherein the voltage value of the voltage E is a pulse voltage average value IN transmission delay time, and amplifying the voltage E to obtain a voltage F, and determining the transmission delay time by measuring the voltage value of the voltage F.
5. The nanosecond-level transmission delay test method according to claim 4, wherein an input waveform IN to be tested is input to a positive input terminal of a comparator, an input reference voltage Ref _ IN is input to a negative input terminal of the comparator, the comparator outputs the waveform A, an output waveform OUT to be tested is input to the positive input terminal of the comparator, an output reference voltage Ref _ OUT is input to the negative input terminal of the comparator, the comparator outputs the waveform B, and the waveform B generates the waveform C through an odd number of NOT-gate circuits.
6. The nanosecond-level transmission delay test method according to claim 5, wherein the waveform A and the waveform C generate the rising edge transmission delay pulse waveform D through an AND gate circuit, and the waveform A and the waveform C generate the falling edge transmission delay pulse waveform H through a NOR gate circuit.
7. The nanosecond-level transmission delay test method according to claim 6, wherein the voltage E is generated by passing the pulse waveform D and the pulse waveform H through a filter, and the voltage E is amplified by an amplifier to generate the voltage F.
8. The nanosecond-level transmission delay test method according to claim 7, wherein the voltage F is tested by a tester, the tester is calibrated before the test, a voltage value measured by using the same waveform through input and output is a delay error voltage G existing in the tester, the value of the voltage F is F ' -G, F ' is a measurement value directly obtained by measuring the voltage F by the tester, a proportional relationship is fitted between the F ' -G and a transmission delay time measured by an oscilloscope actually, and the transmission delay is tested by directly testing a voltage signal on the tester according to the proportional relationship.
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