CN112782487B - Duty ratio detection system - Google Patents
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Abstract
The present solution provides a duty cycle detection system, which is characterized in that the system includes: the wide-voltage anti-interference shaping unit is used for shaping the PWM signal with wide-voltage folding noise to obtain a digital level PWM signal; and the duty ratio detection unit is used for obtaining the pulse width and the period of the digital level PWM signal by adopting a phase-shifting pulse counting method and determining the duty ratio based on the pulse width and the period. The scheme is not limited by the voltage range of the signal, and has strong anti-interference capability; the wide-voltage anti-interference shaping unit can change voltage in a wide range and effectively, and filter the influence of the superimposed noise signal on the original signal; the detection precision of the pulse width can be effectively improved on the basis of a hardware technology by a phase-shift pulse technology method adopted by the duty ratio detection unit; the scheme has wide popularization range in engineering application, low hardware cost, high efficiency and practicability.
Description
Technical Field
The embodiment of the scheme relates to the technical field of signal processing, in particular to a duty ratio detection system suitable for wide-voltage-superposition-noise PWM signals.
Background
In practical applications, there are many pulse width modulation type motors (hereinafter referred to as motors), such as pulse width modulation type steering engines, and their driving control signals are a series of pulse waveforms with varying duty ratios, i.e., PWM signals. The driving controller can enable the motors to obtain corresponding information such as position, speed, angle and the like by adjusting the duty ratio of the driving control signal; meanwhile, the motor outputs an analog feedback signal to the driving controller, and forms a closed loop with the analog feedback signal.
The motors and the driving controllers thereof are not separable, and in order to save resources in many cases, one driving controller is often designed to be multi-channel and multifunctional so as to drive and control a plurality of motors to act simultaneously. The reliability of the driving controller plays a vital role for the motor, the electrical performance parameters of the motor need to be strictly measured, and the most direct solution is to connect one or more corresponding controlled motors and measure the motor by assisting a power supply with higher power. The power supply with larger power mainly supplies power to the controlled motor, and the power of the motor applied in industry or national defense is generally varied from tens of watts to kilowatts.
In reality, if the method of simultaneously configuring the corresponding motor and the power supply for the mass-produced driving controller is too high in cost, the occupied space is huge. In practice, the interface between the driving controller and the motor is an electrical interface, and the motor simulator can be designed only by finding the relation between the motor feedback signal and the driving control signal, so as to replace the actual measurement of the motor matched with the driving controller. The motor simulator finally becomes a circuit, has small volume and light weight, can solve the problem of space placement, can greatly reduce the cost and shortens the development period. And the multichannel motor simulator can realize the purpose of batch test of the electrical performance of the drive controller in a short time.
Regardless of the relationship between the motor feedback signal and the drive control signal, it is a precondition to extract the duty cycle parameter information in the drive control signal. Because the types and types of motors are quite different, the voltage requirements of driving control signals are quite the same and are sometimes influenced by the use environment factors, and when the driving control signals are output from a driving controller and then reach the motors, a lot of interference noise is superimposed, the PWM signals with wide voltage superposition noise have complicated processing procedures by using the traditional method of conditioning circuit +A/D sampling detection when the duty ratio parameters are measured, the precision is low, and as long as the level of input voltage is changed, the hardware parameters of the conditioning circuit must be correspondingly adjusted, and the existing design scheme cannot adapt to the duty ratio detection of all the PWM signals with wide voltage superposition noise.
Disclosure of Invention
In view of this, the present invention provides a duty ratio detection system suitable for wide-voltage noise PWM signals.
To solve the above problems, according to an embodiment of the present invention, there is provided a duty cycle detection system, including:
the wide-voltage anti-interference shaping unit is used for shaping the PWM signal with wide-voltage folding noise to obtain a digital level PWM signal;
and the duty ratio detection unit is used for obtaining the pulse width and the period of the digital level PWM signal by adopting a phase-shifting pulse counting method and determining the duty ratio based on the pulse width and the period.
In a preferred embodiment, the wide-voltage anti-interference shaping unit comprises: the voltage dividing/stabilizing selection circuit, the reverse hysteresis comparator circuit and the reverse logic isolation digital level conversion circuit are connected in sequence;
the PWM signal with wide voltage superposition noise is processed by a dividing/stabilizing selection circuit, an inverting hysteresis comparator circuit and an inverting logic isolation digital level conversion circuit in sequence, so that a digital level PWM signal is obtained.
In a preferred embodiment, the divide/steady voltage selection circuit includes: a first signal input terminal;
a first signal output terminal;
a first analog switch group connected between the first signal input terminal and the second signal output terminal; each analog switch in the first analog switch group is connected with a first signal input end through a peripheral resistor;
the second analog switch group is connected with the first signal output end and the ground end; each analog switch in the second analog switch group can be selectively connected with the ground through two diodes, peripheral resistors or one diode which are oppositely arranged according to an external control signal.
In a preferred embodiment, the inverting hysteresis comparator circuit comprises:
a second signal input terminal;
a second signal output terminal;
the comparator is connected with the second signal input end and the second signal output end; the negative input end of the comparator is directly connected with the second signal input end; the positive input end of the comparator is connected with the ground end and the reference voltage end sequentially through a first resistor and a selection switch; the positive input end of the comparator is respectively connected with a second signal output end and a ground end through a second resistor, wherein two diodes which are oppositely arranged are connected between the second resistor and the ground end; the output end of the comparator is connected with the second signal output end.
In a preferred embodiment, the inverse logic isolated digital level shift circuit comprises:
a third signal input terminal;
a third signal output terminal;
the high-speed optical coupler is connected between the third signal input end and the third signal output end; a current limiting resistor is connected between the high-speed optocoupler and the third signal input end; and the output end of the high-speed optocoupler is connected with a power supply voltage end through a pull-up resistor.
In a preferred embodiment, the duty cycle detection unit comprises:
the phase-locked loop module is used for generating two paths of clock signals which have the same frequency as the original signals and have phase differences.
In a preferred embodiment, the phase-locked loop module specifically performs the following steps:
processing the clock signal CLK0 based on a phase-shifting pulse counting method, and sequentially shifting phase by 90 degrees to form other three clock signals CLK90, CLK180 and CLK270;
driving four-way counters to measure the pulse to be measured by using the four-way clock signals respectively;
if the frequency of the clock signal CLK0 is f and the period thereof is t=1/f, the count values measured by the four-way clock to-be-measured pulse signals are N1, N2, N3, N4 respectively, and the measured value of the last to-be-measured pulse signal is:
measuring pulse signals to be measured by using four paths of clocks and adding the measurement results, which is equivalent to measuring the pulse to be measured by using a clock signal with the frequency of 4f of 4 times;
the maximum error of the measurement result is the clock period of the equivalent clock, i.e. 1/4 of the clock period of the clock signal CLK 0.
In a preferred embodiment, the duty cycle detection unit comprises:
the calculation module is used for determining the period of the digital level PWM signal according to the obtained width of the high level of the PWM signal and the width of the low level of the PWM signal; the duty cycle is obtained by using the ratio of the high level time of the digital level PWM signal to the period thereof.
In a preferred embodiment, the duty cycle detection unit employs a programmable gate array FPGA.
The technical scheme of the embodiment of the scheme has the following advantages:
the scheme is not limited by the voltage range of the signal, and has strong anti-interference capability; the wide-voltage anti-interference shaping unit can change voltage in a wide range and effectively, and filter the influence of the superimposed noise signal on the original signal; the detection precision of the pulse width can be effectively improved on the basis of a hardware technology by a phase-shift pulse technology method adopted by the duty ratio detection unit; the scheme has wide popularization range in engineering application, low hardware cost, high efficiency and practicability.
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In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are required to be used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only embodiments of the present application, and that other drawings may be obtained according to the provided drawings without inventive effort to a person skilled in the art.
FIG. 1 is a schematic diagram of a PWM signal with wide folding noise according to the present solution;
fig. 2 is a schematic diagram of the working principle of the wide-voltage anti-interference shaping unit according to the scheme;
FIG. 3 is a schematic diagram of the transmission characteristics of the inverting hysteresis comparator according to the present embodiment;
FIG. 4 is a schematic diagram of the measurement principle of the phase-shifting pulse counting method according to the scheme;
FIG. 5 is a schematic diagram of a wide-voltage noise-superimposed PWM signal according to the present embodiment;
FIG. 6 is a schematic diagram of a wide voltage anti-interference shaping unit circuit in the present embodiment;
fig. 7 is a schematic diagram of the duty ratio detection unit for calculating the duty ratio by using the FPGA in the present embodiment.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The scheme is mainly a simple and efficient detection method for detecting the duty ratio of the wide-voltage-superposition-noise PWM signal. The duty ratio of the PWM signal with the wide folding noise is detected through the duty ratio detection system. The system consists of a wide-voltage anti-interference shaping unit and a duty ratio detection unit. The wide-voltage anti-interference shaping unit is used for shaping the PWM signal with wide-voltage superposition noise into the PWM signal which can be identified by the duty ratio detection unit, and simultaneously maintaining the period and the duty ratio of the signal unchanged; the duty ratio detection unit is based on FPGA hardware, and obtains the pulse width and the period of the PWM signal output by the wide-voltage anti-interference shaping unit by adopting a phase-shift pulse counting method, so as to obtain the duty ratio.
As shown in fig. 1, is a wide press stackSchematic of a noisy PWM signal. U (U) max Representing the high level voltage amplitude of the signal, U min Representing the low level voltage amplitude of the signal. U under different application scenes max Ranging from a few volts to hundreds of volts, U min May be zero level voltage or negative voltage, and may range from minus a few volts to minus a few hundred volts. The interfering signal may be superimposed on a high level or on a low level.
The wide-voltage anti-interference shaping unit comprises a division/voltage stabilizing selection circuit, an inverse hysteresis comparator circuit and an inverse logic isolation digital level conversion circuit, and the schematic diagram of the wide-voltage anti-interference shaping unit is shown in figure 2. U (U) i Is a wide-voltage noise-superimposed PWM signal as shown in fig. 1. Analog switch S a And S is b Forms a voltage dividing/stabilizing circuit with peripheral resistance, a voltage stabilizing tube and the like, wherein C_S a And C_S b Respectively analog switches S a And S is b Can simulate the switch S by an external control signal a And S is b Control of opening and closing, switching, etc.; u output by the dividing/stabilizing circuit x Enters an anti-phase hysteresis comparator, outputs symmetrical positive and negative amplitude values, and has an absolute value of U z PWM signal U of (2) y ；U y After passing through the inverse logic isolation digital level conversion circuit, the digital level PWM signal U which can be identified by the duty ratio detection unit with the high level of 2.5V/3.3V and the low level of (0-0.8V) is shaped z . The signal U z Logic characteristics of (a) and signal U y Conversely, the signal U y Logic characteristics of (a) and signal U x In contrast, the signal U z Logic characteristics of (c) and the signal U x The same applies.
As shown in fig. 2, a schematic diagram of the divide/steady voltage selection circuit is shown, for signals U of different levels and different frequencies i Different voltage division modes can be selected through the control terminal of the analog switch. The voltage-dividing and stabilizing topological structure of the resistor and the bidirectional voltage-stabilizing diode has strong anti-interference performance, and is suitable for signals U with positive and negative levels and smaller frequency i The method comprises the steps of carrying out a first treatment on the surface of the The voltage division and stabilization topological structure of the resistor and the unidirectional voltage-stabilizing diode also has strong anti-interference performance,adapted for signals U having only positive levels, less frequent i The method comprises the steps of carrying out a first treatment on the surface of the Although the pure resistive voltage division topology has no anti-interference capability, the divided signal U x The frequency characteristic of Ui can be closely tracked, and the signal interference problem can be perfectly solved in the design of the inverse hysteresis comparator. In the case of a single-limit comparator, the superimposed noise, if any small change around the threshold, will cause a transition in the input voltage, ultimately affecting the duty cycle detection result of the signal. The hysteresis comparator circuit has hysteresis characteristics, so that the hysteresis comparator circuit has certain anti-interference capability. The inverse hysteresis comparator is shown in FIG. 2 and corresponds to U x There are two modes of operation with different level voltages. When U is x When the level voltage of (1) is positive only, the threshold selection analog switch S is at the positive input end of the comparator N1 yz Selecting access reference voltage U ref The method comprises the steps of carrying out a first treatment on the surface of the When U is x When the level voltage of the comparator N1 has positive and negative voltages, the threshold selection analog switch S is arranged at the positive input end of the comparator N1 yz An access reference ground is selected.
If U, as shown in FIG. 2 x Is a positive and negative symmetrical signal, and the threshold selection analog switch S yz Selecting the potential at the non-inverting input to be connected to ground
Let U + ＝U - U is obtained X Thus giving rise to
U y And U X The transmission characteristics of (a) are shown in fig. 3 (a).
If U X Only a positive level signal, the threshold selection analog switch S yz Selecting access reference voltage U ref The potential of the non-inverting input
Let U + ＝U - U is obtained X Thus giving rise to
Due to the reference voltage U ref >0，U y And U x The transmission characteristics of (a) are shown in fig. 3 (b). Changing the reference voltage, the voltage transmission characteristic of the hysteresis comparator will generate the movement in the horizontal direction; changing the stabilizing voltage of the stabilizing tube can make the voltage transmission characteristic move in the vertical direction.
From the output voltage of the inverting hysteresis comparator at the input voltage U y When equal to the threshold voltage, assume U x Is a signal of positive and negative symmetry, when U x <-U T Then the input voltage U of the comparator N1 - Must be smaller than U + Thus U y ＝+U Z So U is + ＝+U T . Only when the voltage U is input x Increase to +U T Further increasing by an infinitesimal amount is the output voltage U y Will be from +U Z Transition to-U Z . Similarly, assume U x >+U T Then the input voltage U of the comparator N1 - Is necessarily greater than U + Thus U y ＝-U Z So U is + ＝-U T . Only when the voltage U is input x Reduced to-U T When the output voltage U is reduced by an infinite small amount y Will be from-U Z Transition to +U Z . It can be seen that U y From +U Z Transition to-U Z And Uy slave-U Z Transition to +U Z Is different at the threshold voltage of (c).
The signal U output by the hysteresis comparator y Already isOutput voltage amplitude value + -U Z The signals of the (2) are input into an inverse logic isolation digital level conversion circuit, and finally the signals are formed into PWM signals with high level of 2.5V or 3.3V and low level of (0-0.8V). As shown in fig. 2, the inverse logic isolation digital level conversion circuit is implemented by a high-speed optocoupler, and the high level of the conversion output is 2.5V or 3.3V, depending on the level voltage required by the I/O port of the duty cycle detection unit FPGA. R4 is a current limiting resistor for limiting forward current of the optocoupler; r5 is a pull-up resistor, and the pull-up voltage determines the magnitude of the output high level voltage.
The duty ratio detection unit is based on FPGA hardware, and obtains the pulse width and the period of the PWM signal output by the wide-voltage anti-interference shaping unit by adopting a phase-shift pulse counting method, so as to obtain the duty ratio. In a conventional pulse counting method, a clock pulse is counted within a pulse width to be measured (generally, a rising edge of the clock pulse is counted, and the rising edge is counted as an example), and a count value N is multiplied by a clock period T to obtain a value of the pulse width. The error of this method is derived from the time differences t1, t2 between the leading edge and the trailing edge of the pulse to be measured and the rising edge of the adjacent clock, and the maximum error is a value of one clock period, for example, the clock frequency is 100MHz, and the maximum error is 10ns. The conventional pulse counting method needs to increase the clock frequency if the timing precision is to be increased, and the increase of the clock frequency is limited by the performance of the device and brings certain difficulties to the design and processing of the printed board. If the measurement accuracy of nanosecond order is to be obtained, the clock frequency needs to reach 1GHz, which is difficult to apply in practical engineering. Based on the conventional pulse counting method, the invention provides a phase-shifting pulse counting method by combining a digital phase-shifting technology with an FPGA, and can improve the measurement accuracy to nanosecond level. The phase shift is that the clock signal generates a delay of a certain time by the delay function of a phase-locked loop module (PLL) in the FPGA, and the newly generated signal and the original signal form two paths of clock signals with the same frequency but a certain phase difference. As shown in fig. 4, for the schematic diagram of the measurement principle, the clock signal CLK0 is processed by a phase shifting technique, and sequentially phase shifted by 90 ° to form three other clock signals CLK90, CLK180 and CLK270. The four-way counter is driven by the four-way clock signals to measure the pulse to be measured. Assuming that the frequency of the clock signal CLK0 is f, the period thereof is t=1/f, the count values measured by the four-way clock to-be-measured pulse signals are N1, N2, N3, N4, respectively, and the measured value of the last to-be-measured pulse signal is
As can be seen from equation (6) and fig. 4, each rising edge of the clock signals CLK0, CLK90, CLK180, and CLK270 corresponds to one rising edge of the equivalent clock, respectively, and thus can be expressed as follows: the pulse signal to be measured is measured using four clocks and the measurement results are added, which is equivalent to measuring the pulse to be measured using a clock signal with a frequency of 4f, which is a frequency of 4 times. As can be seen from the conventional pulse counting method described above, the maximum error of the measurement result is 1/4 of the clock period of the equivalent clock, i.e. the clock period of the clock signal CLK 0. By the method, the purposes of reducing measurement errors and improving timing accuracy can be achieved on the premise of not improving the frequency of the counting clock.
The duty ratio detection unit obtains the pulse width of the PWM signal with higher precision, namely the width of high level by utilizing the phase-shifting pulse counting method; similarly, after the signal to be measured is subjected to phase inversion, the phase-shifting pulse counting method can be used for obtaining the low-level width of the PWM signal, the sum of the low-level width and the phase-shifting pulse counting method is the period of the signal to be measured, and the ratio of the high-level time to the period is the duty ratio of the signal to be measured.
The duty ratio detection system for the PWM signals is not limited by the voltage range of the signals, and has strong anti-interference capability. The wide-voltage anti-interference shaping unit can change voltage in a wide range and effectively, and filter the influence of the superimposed noise signal on the original signal; the phase-shift pulse technique method adopted by the duty ratio detection unit can effectively improve the detection precision of pulse width on the basis of hardware technology and has low hardware cost.
The present solution is further described below in connection with fig. 5 to 7.
A duty cycle detection system suitable for wide-voltage noise-superimposed PWM signals is further described in this embodiment by way of example. The system comprises: and the wide-voltage anti-interference shaping unit and the duty ratio detection unit. The wide-voltage anti-interference shaping unit is used for shaping the PWM signal with wide-voltage superposition noise into the PWM signal which can be identified by the duty ratio detection unit, and simultaneously maintaining the period and the duty ratio of the signal unchanged; the duty ratio detection unit is based on FPGA hardware, and obtains the pulse width and the period of the PWM signal output by the wide-voltage anti-interference shaping unit by adopting a phase-shift pulse counting method, so as to obtain the duty ratio.
In this embodiment, the wide-voltage noise-superimposed PWM signal U i Specifically, the frequency 10k (period 10 5 ns), high level voltage 28V, low level voltage-28V, PWM signal with continuously varying duty ratio D, and superimposed noise voltage peak-to-peak value 5V, as shown in fig. 5.
As shown in fig. 6, the wide-voltage anti-interference shaping unit in this embodiment includes a voltage dividing circuit, an inverse hysteresis comparator circuit and an inverse logic isolation digital level conversion circuit.
As can be seen by comparing fig. 2 and 6, the present embodiment is provided with an analog switch S a And S is b Control terminal c_s of (2) a And C_S b Respectively select resistors R sa1 And R is sb2 Constitute a voltage dividing circuit R sa1 Take the value 22k, R sb1 The value 10k is taken according to the following steps:
the high level voltage is 8.75V, the low level voltage is-8.75V, the frequency is equal to U i Identical U x A signal. It should be noted that although the voltage dividing circuit theoretically has a reducing effect on the superimposed noise value, the specific effect cannot be calculated by a simple voltage dividing calculation formula for the noise peak-to-peak reduction amount, here for the signal U x The noise peak-to-peak value on this is considered to be only less than 5V.
As shown in fig. 6, the inverting hysteresis comparator in this embodiment performs the following parameter design: the comparator adopts +/-15V to supply power, the voltage stabilizing reference value selected by the voltage stabilizing pair tube is +/-5V, the R1 value is 4k, and the R2 value is 1k. According to the above parameters, the threshold voltage of the inverting hysteresis comparator can be obtained:
when U is x When the interference signal with the peak value of +5V is superimposed on the low level of (3), U x ＝(-8.75+5)V，U y = +5v, so U + The disturbing signal does not cause the output signal U = +4v y Is only when the input voltage U x To +4V, an infinitely small amount is the output voltage U y Will jump from +5V to-5V. Similarly, when U x When the interference signal with the peak value of-5V is superimposed on the high level of (2), U x ＝(8.75-5)V，U y = -5V, so U + -4V, the interfering signal will not cause the output signal U either y Is only when the input voltage U x Reduced to-4V and then reduced by an infinitely small amount, the output voltage U y Will jump from-5V to +5V. Thus, the output signal U of the inverting hysteresis comparator y Is a non-interfering, polarity-identical input signal U to the circuit x An inverted signal. The signal has a high level of +5V, a low level of-5V, a frequency of 10k, and a duty cycle of (1-D).
As shown in FIG. 6, the inverting hysteresis comparator circuit of the present embodiment outputs a signal U y After entering an inverse logic isolation digital level conversion circuit, the digital level PWM signal U with the high level of 3.3V and the low level of (0-0.8V) is finally formed Z . When U is y When the current is at a high level, under the action of the current limiting resistor R4, the current of the diode at the front stage of the optocoupler B1 is about 5mA, the diode is conducted, the triode at the rear stage of the optocoupler B1 is saturated to output, and a signal U is output z About 0.3V; when U is y When the level is low, the front stage of the optocoupler B1 is cut off, U z A +3.3v voltage signal is output through the pull-up resistor. Thus, the output signal U of the inverse logic isolation digital level conversion circuit z With the input signal U y The polarity is opposite.
To sum up, the whole wide-voltage anti-interference shaping sheetOutput signal U of element z And input signal U i The polarities are the same, and the frequency and the duty ratio are uniform.
In the FPGA adopted by the duty cycle detection unit in this embodiment, the I/O level voltage is 3.3V. Since the PWM signal frequency in the embodiment is fixed to 10k, only the pulse width (i.e., high level time) of the PWM signal needs to be measured to obtain the duty ratio of the measured signal. The method of pulse width used in the embodiment is a phase-shifted pulse counting method. First, four clock signals which are sequentially different in phase by 90 degrees are generated by using a phase-locked loop (PLL) module in an FPGA. In order to reduce the influence of the high-frequency clock signal on the design of the printed board, the input clock signal frequency selected by the design is 50MHz, the PLL is used for 5 times to generate a clock with the frequency of 250MHz, and four counting clock signals CLK0, CLK90, CLK180 and CLK270 which are sequentially different in phase by 90 degrees are generated through the phase shifting function of the PLL. Then, four counting modules (COUNTER) are generated by the counting modules of the FPGA and are driven by CLK0, CLK90, CLK180 and CLK270 respectively to count within the pulse width. As shown in fig. 7, the duty ratio detection unit uses an FPGA to calculate the duty ratio. The input pin pulse is a pulse signal to be measured, the input pin clr is a counting module zero clearing signal, and the output pin width is a measured pulse width output end.
Since the frequency of the counting clock signal is 250MHz, the period T is 4ns, and according to the measurement principle and formula (6) described above, the pulse width is t=n1+n2+n3+n4, i.e. the value output by the adder is the measured pulse width, with the unit of ns.
Finally dividing the measured pulse width by the PWM signal period 10 5 ns is the duty cycle of the signal to be measured.
The detailed logic implementation of the logic circuit unit can refer to the corresponding description of the method part, and each part related in the description can be correspondingly referred to, and is not repeated here
Although the embodiments of the present invention are disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.
Claims (6)
1. A duty cycle detection system, the system comprising:
wide-voltage anti-interference shaping unit: the PWM signal shaping device is used for shaping the PWM signal with wide folding noise; the wide-voltage anti-interference shaping unit comprises a division/voltage stabilizing selection circuit, an inverse hysteresis comparator circuit and an inverse logic isolation digital level conversion circuit which are connected in sequence, and PWM signals with wide-voltage folding noise are processed through the division/voltage stabilizing selection circuit, the inverse hysteresis comparator circuit and the inverse logic isolation digital level conversion circuit in sequence to obtain digital level PWM signals;
duty ratio detection unit: a phase-shifting pulse counting method is adopted to obtain the pulse width and the period of a digital level PWM signal, and the duty ratio is determined based on the pulse width and the period; the duty ratio detection unit comprises a phase-locked loop module and a calculation module; the phase-locked loop module is used for generating two paths of clock signals which have the same frequency as the original signals and have phase differences; the calculation module determines the period of the digital level PWM signal according to the obtained width of the high level of the PWM signal and the width of the low level of the PWM signal; the duty cycle is obtained by using the ratio of the high level time of the digital level PWM signal to the period thereof.
2. The system of claim 1, wherein the divide/steady voltage selection circuit comprises:
a first signal input terminal;
a first signal output terminal;
a first analog switch group connected between the first signal input terminal and the second signal output terminal; each analog switch in the first analog switch group is connected with a first signal input end through a peripheral resistor;
the second analog switch group is connected with the first signal output end and the ground end; each analog switch in the second analog switch group can be selectively connected with the ground through two diodes, peripheral resistors or one diode which are oppositely arranged according to an external control signal.
3. The system of claim 1, wherein the inverting hysteresis comparator circuit comprises:
a second signal input terminal;
a second signal output terminal;
the comparator is connected with the second signal input end and the second signal output end; the negative input end of the comparator is directly connected with the second signal input end; the positive input end of the comparator is connected with the ground end and the reference voltage end sequentially through a first resistor and a selection switch; the positive input end of the comparator is respectively connected with a second signal output end and a ground end through a second resistor, wherein two diodes which are oppositely arranged are connected between the second resistor and the ground end; the output end of the comparator is connected with the second signal output end.
4. The system of claim 1, wherein the inverse logic isolated digital level shift circuit comprises:
a third signal input terminal;
a third signal output terminal;
the high-speed optical coupler is connected between the third signal input end and the third signal output end; a current limiting resistor is connected between the high-speed optocoupler and the third signal input end; and the output end of the high-speed optocoupler is connected with a power supply voltage end through a pull-up resistor.
5. The system of claim 1, wherein the phase-locked loop module specifically performs the steps of:
processing the clock signal CLK0 based on a phase-shifting pulse counting method, and sequentially shifting the phase by 90 0 to form other three clock signals CLK90, CLK180 and CLK270;
driving four-way counters to measure the pulse to be measured by using the four-way clock signals respectively;
if the frequency of the clock signal CLK0 is f and the period thereof is t=1/f, the count values measured by the four-way clock to-be-measured pulse signals are N1, N2, N3, N4 respectively, and the measured value of the last to-be-measured pulse signal is:
measuring pulse signals to be measured by using four paths of clocks and adding the measurement results, which is equivalent to measuring the pulse to be measured by using a clock signal with the frequency of 4f of 4 times;
the maximum error of the measurement result is the clock period of the equivalent clock, i.e. 1/4 of the clock period of the clock signal CLK 0.
6. The system of claim 1, wherein the duty cycle detection unit employs a programmable gate array FPGA.
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| CN101762751A (en) * | 2008-12-04 | 2010-06-30 | 北京中科信电子装备有限公司 | GLITCH detection circuit |
| JP2019007886A (en) * | 2017-06-27 | 2019-01-17 | ラピスセミコンダクタ株式会社 | Duty cycle detection circuit and duty cycle detection method |
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| JP3594538B2 (en) * | 2000-07-27 | 2004-12-02 | 三洋電機株式会社 | Digital signal duty ratio detection circuit |
| US6674387B1 (en) * | 2002-10-02 | 2004-01-06 | Honeywell International Inc. | Pulse width modulation analog to digital conversion |
| JP4277912B2 (en) * | 2007-03-02 | 2009-06-10 | 株式会社デンソー | Load driving device and load driving method |
| CN106771582A (en) * | 2016-11-21 | 2017-05-31 | 东南大学 | The method of testing and tester of high-frequency pulse signal |
| CN207586312U (en) * | 2018-03-20 | 2018-07-06 | 成都信息工程大学 | A kind of digital frequency meter based on FPGA |
| CN113676162B (en) * | 2018-03-26 | 2024-02-23 | 南京矽力微电子技术有限公司 | Pulse signal level calculating method and circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101762751A (en) * | 2008-12-04 | 2010-06-30 | 北京中科信电子装备有限公司 | GLITCH detection circuit |
| JP2019007886A (en) * | 2017-06-27 | 2019-01-17 | ラピスセミコンダクタ株式会社 | Duty cycle detection circuit and duty cycle detection method |
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