CN112769406A - Low noise amplifier circuit with multiple amplification gains - Google Patents

Low noise amplifier circuit with multiple amplification gains Download PDF

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Publication number
CN112769406A
CN112769406A CN201911074912.2A CN201911074912A CN112769406A CN 112769406 A CN112769406 A CN 112769406A CN 201911074912 A CN201911074912 A CN 201911074912A CN 112769406 A CN112769406 A CN 112769406A
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circuit
signal
current
output
current path
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张家润
李珈谊
蔡秉轩
陈家源
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Realtek Semiconductor Corp
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Realtek Semiconductor Corp
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/42—Amplifiers with two or more amplifying elements having their dc paths in series with the load, the control electrode of each element being excited by at least part of the input signal, e.g. so-called totem-pole amplifiers

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Abstract

The low noise amplifier circuit comprises an input stage circuit, a first output stage circuit and a second output stage circuit. The input stage circuit is used for receiving an input signal through the antenna and generating a bias signal. The first output stage circuit corresponds to the first wireless communication and is biased according to a bias signal and a first control signal to generate a first output signal, wherein the first control signal is used for setting a first amplification gain of the first output stage circuit. The second output stage circuit corresponds to the second wireless communication and is biased to generate a second output signal according to the bias signal and a second control signal, wherein the second control signal is used for setting a second amplification gain of the second output stage circuit.

Description

Low noise amplifier circuit with multiple amplification gains
Technical Field
The present disclosure relates to receiver devices, and more particularly, to receiver devices including low noise amplifiers with multiple amplification gains.
Background
In order to simultaneously receive a plurality of wireless signals with different input powers, a low noise amplifier in a transceiver device often has an adjustable gain. In the prior art, when a wireless signal with high power is received, the gain of the low noise amplifier is reduced to avoid saturation of the subsequent circuit. As a result, other wireless signals with low power cannot be effectively amplified, and are susceptible to noise.
Disclosure of Invention
In some embodiments, the low noise amplifier circuit includes an input stage circuit, a first output stage circuit, and a second output stage circuit. The input stage circuit is used for receiving an input signal through the antenna and generating a bias signal. The first output stage circuit corresponds to the first wireless communication and is biased according to a bias signal and a first control signal to generate a first output signal, wherein the first control signal is used for setting a first amplification gain of the first output stage circuit. The second output stage circuit corresponds to the second wireless communication and is biased to generate a second output signal according to the bias signal and a second control signal, wherein the second control signal is used for setting a second amplification gain of the second output stage circuit.
The features, implementations, and technical effects of the present disclosure will be described in detail below with reference to the accompanying drawings.
Drawings
Fig. 1 is a schematic diagram illustrating a signal receiver apparatus according to some embodiments of the present disclosure;
FIG. 2 is a circuit schematic diagram illustrating the low noise amplifier circuit of FIG. 1 according to some embodiments of the present disclosure; and
fig. 3 is a circuit schematic diagram illustrating the low noise amplifier circuit of fig. 1 according to some embodiments of the present disclosure.
Description of the symbols
100 receiver device
101 antenna
103 impedance matching circuit
110 Low Noise Amplifier (LNA) circuit
111 input stage circuit
112. 113 output stage circuit
120. 125 isolation circuit
130. 135 LNA circuit
140. 145 mixer circuit
150. 155 digital baseband circuit
L1, L2 inductance
S1+、S1-、S2+、S2-Signal
SBBias signal
SC1、SC2Control signal
SI1+、SI1-、SQ1+、SQ1-Signal
SI2+、SI2-、SQ2+、SQ2-Signal
SINInput signal
SO1、SO2Output signal
A0, A1, A2, A3, A4, A5 current paths
B0, B1, B2, B3, B4 and B5 current paths
N1, N2, N3, N4, N5 and N6 transistors
ND node
P1, P2, P3, P4, P5 transistors
SC1[i]、SC2[i]Bit cell
VDD Voltage
112A, 113A amplifying circuit
112B, 113B current regulation circuit
IC1、IC2Electric current
SC1[j]、SC2[j]Bit cell
Detailed Description
All words used herein have their ordinary meaning. The definitions of the above-mentioned words in commonly used dictionaries, any use of the words discussed herein in this disclosure is intended to be exemplary only and should not be construed as limiting the scope and meaning of the disclosure. Likewise, the present disclosure is not limited to the various embodiments shown in this specification.
As used herein, the term "couple" or "connect" refers to two or more elements being in direct physical or electrical contact with each other, or in indirect physical or electrical contact with each other, or to two or more elements operating or acting together.
As used herein, the term "circuit system" may be a single system formed by at least one circuit (circuit), and the term "circuit" may be a device connected by at least one transistor and/or at least one active and passive component in a certain manner to process signals. As used herein, the term "and/or" includes any combination of one or more of the associated listed items.
Fig. 1 is a schematic diagram illustrating a receiver apparatus 100 according to some embodiments of the present disclosure. In some embodiments, the receiver device 100 may be used for wireless communication applications.
The receiver device 100 includes an antenna 101, an impedance matching circuit 103, a Low Noise Amplifier (LNA) circuit 110, an isolation circuit 120, an isolation circuit 125, a mixer circuit 140, a mixer circuit 145, a digital baseband circuit 150, and a digital baseband circuit 155. The antenna 101 receives an input signal SINAnd transmits the input signal S via the impedance matching circuit 103INTo the LNA circuit 110.
The LNA circuit 110 is configured to output an input signal SINGenerating a bias signal SB. The LNA circuit 110 is based on the bias signal SBAnd a control signal SC1Generating an output signal SO1And according to the bias signal SBAnd a control signal SC2Generating an output signal SO2. In some embodiments, the LNA circuit 110 includes an input stage circuit 111, an output stage circuit 112, and an output stage circuit 113. Input stage circuit111 according to an input signal SINGenerating a bias signal SB. The output stage circuit 112 corresponds to the first wireless communication, and the output stage circuit 113 corresponds to the second wireless communication. For example, the first wireless communication may be, but is not limited to, a Wireless Local Area Network (WLAN), and the output stage circuit 112 is used to amplify data signals transmitted through the WLAN. The second wireless communication may be, but is not limited to, Bluetooth (Bluetooth), and the output stage circuit 113 is used to amplify the data signal transmitted via Bluetooth.
The output stage circuit 112 is used for generating a bias signal S according to the output voltageBAnd a control signal SC1Is biased to generate an output signal SO1-Wherein the control signal SC1For setting the amplification gain of the output stage circuit 112. If the amplification gain of the output stage circuit 112 is larger, the output signal S is outputO1-The higher the power of. Similarly, the output stage circuit 113 is used for generating the bias signal S according to the output voltageBAnd a control signal SC2Is biased to generate an output signal SO2. Control signal SC2For setting the amplification gain of the output stage circuit 113. If the amplification gain of the output stage circuit 113 is larger, the output signal S is outputO2-The higher the power of. The operation of this will be described later with reference to fig. 2 and 3.
In some embodiments, the inductances in each of the isolation circuit 120 and the isolation circuit 125, such as the inductance L1 and the inductance L2, may be implemented by coil (coil) circuits or windings (winding). The isolation circuit 120 is coupled to the LNA circuit 110 for receiving the output signal SO1And generates a differential signal S1+And signal S1-To the mixer circuit 140. The isolation circuit 125 is coupled to the LNA circuit 110 to receive the output signal SO2And generates a differential signal S2+And signal S2-To the mixer circuit 145. Mixing circuit 140 modulates signal S1+And signal S1-To generate a plurality of signals SI1+、SI1-、SQ1+And SQ1-. Mixing circuit 145 modulates signal S2+And signal S2-To generate a plurality of signals SI2+、SI2-、SQ2+And SQ2-. The digital baseband circuit 150 can be based on a plurality of signalsSI1+、SI1-、SQ1+And SQ1-Analyzing an input signal SINTo generate the control signal SC1. The digital baseband circuit 155 can be based on a plurality of signals SI2+、SI2-、SQ2+And SQ2-Analyzing an input signal SINTo generate the control signal SC2。
For example, if the input signal SINIncluding a data signal corresponding to the first wireless communication, the digital baseband circuit 150 may be configured to generate a plurality of signals SI1+、SI1-、SQ1+And SQ1-This data signal is acquired. Based on the bits of the data signal, the digital baseband circuit 150 can determine whether the power of the data signal needs to be adjusted. For example, if the time when the bits of the data signal are all logic 1 exceeds a predetermined time, the digital baseband circuit 150 can determine that the power of the data signal is too high and output the control signal SC1To reduce the amplification gain of the output stage circuit 112. Based on similar operation, the digital baseband circuit 155 can also output the control signal SC2To adjust the amplification gain of the output stage circuit 113. The above arrangement of the digital baseband circuits 150 and 155 is merely an example, and the disclosure is not limited thereto.
In some embodiments, the receiver device 100 may further include an LNA circuit 130 and an LNA circuit 135. The LNA circuit 130 is coupled between the isolation circuit 120 and the mixer circuit 140, and is used for providing an additional gain to amplify the signal S1+And signal S1-. The LNA circuit 135 is coupled between the isolation circuit 125 and the mixer circuit 145, and is used for providing an extra gain to amplify the signal S2+And signal S2-. The LNA circuit 130 and the LNA circuit 135 may be selectively configured according to different practical requirements.
In some related art, the LNA circuit is set to amplify a plurality of wireless signals at the same time. When the LNA circuit processes a wireless signal having a higher power, the amplification gain of the LNA circuit may be reduced to avoid over-saturating subsequent circuits. As a result, other wireless signals with lower power cannot be sufficiently amplified and are more affected by noise. In contrast to the above-mentioned techniques, in some embodiments of the present disclosure, when a plurality of wireless signals with different powers are received, the LNA circuit 110 may provide a plurality of different amplification gains to process the wireless signals, so as to improve the above-mentioned problem.
Fig. 2 is a circuit schematic diagram of the LNA circuit 110 of fig. 1, shown in accordance with some embodiments of the present disclosure. In this example, the input stage circuit 111, the output stage circuit 112, and the output stage circuit 113 operate as current mirror circuits.
The input stage circuit 111 includes a transistor N1 and a transistor P1. A first terminal (e.g., a source) of the transistor P1 is coupled to a voltage source for receiving the voltage VDD, and a second terminal (e.g., a drain) of the transistor P1 is coupled to a first terminal (e.g., a drain) of the transistor N1 and a control terminal (e.g., a gate) of the transistor P1 for generating the bias signal SB. A second terminal (e.g., a source) of the transistor N1 is coupled to ground, and a control terminal (e.g., a gate) of the transistor N1 receives the input signal SIN. The transistor N1 is used for receiving the input signal SINIs turned on. The transistor P1 is used to operate as a diode-connected transistor to generate the bias signal SB。
The output stage circuit 112 includes at least one current path (e.g., M current paths, where M is a positive integer greater than or equal to 1) according to the control signal SC1Is conducted to generate an output signal SO1. For example, as shown in fig. 2, the output stage circuit 112 includes a current path a0 and a current path a 1. The current path a0 and the current path a1 are coupled in parallel with each other and have the same circuit structure. Taking the current path a0 as an example, the current path a0 includes a transistor P2 and a transistor P3. A first terminal of the transistor P2 receives the voltage VDD, a second terminal of the transistor P2 is coupled to the first terminal of the transistor P3, and a control terminal of the transistor P2 is for receiving the bias signal SB. The second terminal of the transistor P3 is used for transmitting the output signal SO1To the isolation circuit 120 (e.g., the inductor L1 in FIG. 1), and the control terminal of the transistor P3 is used for receiving the control signal SC1One bit (denoted as S)C1[i]). The transistor P2 is biased by the bias signal SBIs biased to generate an outputOutput signal SO1. The transistor P3 is used for generating a voltage according to the bit SC1[i]Is conducted to output the signal SO1Output to the isolation circuit 120.
As mentioned above, the current path A0 and the current path A1 are connected in parallel, so the output signal SO1Is the sum of the current signals flowing through the two current paths a0 and a 1. The current path A0 is set according to the control signal SC1One bit of SC1[i]Is turned on, and the current path A1 is set according to the control signal SC1Another bit (e.g. can be S)C1[i+1]) And conducting. When the current path A0 and the current path A1 are both turned on, the output signal S is assertedO1Will have a higher current value. Conversely, if the current path A0 is conductive and the current path A1 is non-conductive, the signal S is outputO1Will have a lower current value. In other words, if the amplification gain of the output stage circuit 112 is higher, the controlled signal S in at least one current path isC1The greater the number of paths that are conducting.
The output stage circuit 113 includes at least one current path (e.g., N current paths, where N is a positive integer greater than or equal to 1, and N may be the same as or different from M) according to the control signal SC2Is conducted to generate an output signal SO2. For example, as shown in fig. 2, the output stage circuit 113 includes a current path B0 and a current path B1. The current path B0 and the current path B1 are coupled in parallel with each other and have the same circuit configuration. Taking the current path B0 as an example, the current path B0 includes a transistor P4 and a transistor P5. A first terminal of the transistor P4 receives the voltage VDD, a second terminal of the transistor P4 is coupled to the first terminal of the transistor P5, and a control terminal of the transistor P4 is for receiving the bias signal SB. The second terminal of the transistor P5 is used for transmitting the output signal SO2To the isolation circuit 125 (e.g., inductor L2 in FIG. 1), and the control terminal of the transistor P5 is for receiving the control signal SC2-One bit (denoted as S)C2[i]). The transistor P4 is biased by the bias signal SBIs biased to generate an output signal SO2. The transistor P5 is used for controlling the output according to the control signal SC2Is turned on to output the signal SO2Output to the isolation circuit 125.
Similarly, the signal S is outputO2Is the sum of the current signals flowing through the two current paths B0 and B1. The current path B0 is set according to the control signal SC2Is turned on and the current path B1 is set according to the control signal SC2Another bit (e.g. can be S)C2[i+1]) And conducting. When the current paths B0 and B1 are both turned on, the signal S is outputtedO2Will have a higher current value. Conversely, if the current path B0 is conductive and the current path B1 is non-conductive, the signal S is outputtedO2Will have a lower current value. In other words, the higher the amplification gain of the output stage circuit 113, the higher the controlled signal S in at least one current pathC2The greater the number of paths that are conducting.
The number of current paths shown in fig. 2 is for example only, and the present disclosure is not limited thereto. The number of current paths can be adjusted accordingly according to different requirements. Accordingly, various numbers of current paths are within the scope of the present disclosure.
Fig. 3 is a circuit schematic diagram of the LNA circuit 110 of fig. 1, shown in accordance with some embodiments of the present disclosure. In this example, the input stage circuit 111, the output stage circuit 112, and the output stage circuit 113 operate as current steering (current steering) circuits.
The input stage circuit 111 includes a transistor N2. A first terminal of the transistor N2 is coupled to the node ND, a second terminal of the transistor N2 is coupled to ground, and a control terminal of the transistor N2 receives the input signal SIN. The transistor N2 is used for receiving the input signal SINAnd generates (draws) a bias signal S from the node NDB。
The output stage circuit 112 is coupled to the node ND for receiving the bias signal SB. The output stage circuit 112 includes an amplifier circuit 112A and a current regulator circuit 112B. The amplifying circuit 112A is used for generating a bias signal S according to the bias signalBAnd a control signal SC1Generating an output signal SO1. In this example, the inductor L1 of fig. 1 is coupled between the voltage source providing the voltage VDD and the output stage circuit 112. The current adjusting circuit 112B is used for adjusting the current according to the control signal SC1Adjusts the current (corresponding to the output signal S) flowing through the amplifier circuit 112AO1) To set the amplification gain of the output stage circuit 112.
For example, the amplifying circuit 112A includes at least one current path (e.g., M current paths) for generating the control signal SC1At least one bit (denoted as S)C1[i]) Is conducted to generate an output signal SO1. The current adjusting circuit 112B includes at least one current path (for example, M current paths) for adjusting the current according to the control signal SC1Is turned on (marked as S)C1[j]) To output a current IC1. Output signal SO1Is the sum of the currents flowing through the current paths turned on in the amplifying circuit 112A, and the current IC1Is the sum of the currents flowing through the turned-on current paths in the current adjustment circuit 112B.
In some embodiments, different current paths in the same amplifying circuit 112A may be controlled by the control signal SC1The different bits are turned on. For example, current path A2 is based on bit SC1[i]On, the current path A3 is based on the bit SC1[i+1]And conducting. In some embodiments, different current paths in the same current regulation circuit 112B may be controlled by the control signal SC1The different bits are turned on. For example, current path A4 is based on bit SC1[j]On, the current path A5 is based on the bit SC1[j+1]And conducting.
Current IC1And output signal SO1Is kept as the bias signal SBA predetermined multiple of. In this example, the bias signal SBIs 2I, and current IC1And output signal SO1The sum of (c) is set to I (i.e., the predetermined multiple is 0.5). When the number of paths to be conducted in the at least one current path of the amplifying circuit 112A is larger, the number of paths to be conducted in the at least one current path of the current adjusting circuit 112B is smaller. Under this condition, the signal S is outputO1Large and current IC1Is smaller. Conversely, when the number of paths conducted in the at least one current path of the amplifying circuit 112A is smaller, the number of paths conducted in the at least one current path of the current adjusting circuit 112B is larger. Under this condition, the signal S is outputO1Small and current IC1Is relatively large. In some implementationsIn one embodiment, at least one bit SC1[i]Complementary to at least one bit SC1[j]. In this way, the amplification gain of the output stage circuit 112 can be controlled according to the control signal SC1And (4) setting.
For example, as shown in fig. 3, the amplifying circuit 112A includes a current path a2 and a current path A3 connected in parallel, and the current adjusting circuit 112B includes a current path a4 and a current path a5 connected in parallel. When both current path a2 and current path A3 are on, current path a4 and current path a5 are off. Under this condition, the signal S is outputO1With a larger current value. Equivalently, the output stage circuit 112 has a high amplification gain. When current path a2 is on and current path A3 is off, current path a4 is on and current path a5 is off. Under this condition, the signal S is outputO1With a lower current value. Equivalently, the output stage circuit 112 has a lower amplification gain.
The current path a2 and the current path A3 are coupled in parallel, coupled between the inductor L1 and the node ND, and have the same circuit structure. Taking the current path a2 as an example, the current path a2 includes a transistor N3. A first terminal of the transistor N3 is coupled to the inductor L1, a second terminal of the transistor N3 is coupled to the node ND, and a control terminal of the transistor N3 is configured to receive the control signal SC1At least one bit (i.e. S) ofC1[i]). When transistor N3 responds to bit SC1[i]When conducting, the current path A2 generates the output signal SO1。
Similarly, the current path a4 and the current path a5 are coupled in parallel to each other, coupled between a voltage source providing the voltage VDD and the node ND, and have the same circuit structure. Taking the current path a4 as an example, the current path a4 includes a transistor N4. A first terminal of the transistor N4 receives the voltage VDD, a second terminal of the transistor N4 is coupled to the node ND, and a control terminal of the transistor N4 receives the control signal SC1At least one bit (i.e. S) ofC1[j]). When transistor N4 responds to bit SC1[j]When conducting, current path A4 generates current IC1。
The output stage circuit 113 is coupled to the node ND for receiving the bias signal SB. The output stage circuit 113 includes an amplifying circuit113A and a current adjusting circuit 113B. The amplifying circuit 113A is used for generating a bias signal S according to the bias signal SBAnd a control signal SC2Generating an output signal SO2. In this example, the inductor L2 of fig. 1 is coupled between the voltage source providing the voltage VDD and the output stage circuit 113. The current adjusting circuit 113B is used for adjusting the current according to the control signal SC2Adjusts the current (corresponding to the output signal S) flowing through the amplifier circuit 113AO2) To set the amplification gain of the output stage circuit 113.
For example, the amplifying circuit 113A includes at least one current path (e.g., N current paths) for generating the control signal SC2At least one bit (denoted as S)C2[i]) Is conducted to generate an output signal SO2. The current adjusting circuit 113B includes at least one current path (e.g., N current paths) for adjusting the current according to the control signal SC2Is turned on (marked as S)C2[j]) To output a current IC2. Output signal SO2Is the sum of the currents flowing through the current paths turned on in the amplifying circuit 113A, and the current IC2Is the sum of the currents flowing through the current paths turned on in the current adjusting circuit 113B.
In some embodiments, different current paths in the same amplifying circuit 113A may be controlled by the control signal SC2The different bits are turned on. For example, the current path B2 is based on bit SC2[i]On, the current path B3 is based on the bit SC2[i+1]And conducting. In some embodiments, different current paths in the same current regulation circuit 113B may be controlled by the control signal SC2The different bits are turned on. For example, the current path B4 is based on bit SC2[j]On, the current path B5 is based on the bit SC2[j+1]And conducting.
Current IC2And output signal SO2Is kept as the bias signal SBA predetermined multiple of. In this example, the bias signal SBIs 2I, and current IC2And output signal SO2The sum of (c) is set to I (i.e., the predetermined multiple is 0.5). When the number of the paths conducted in the at least one current path of the amplifying circuit 113A is larger, the at least one current path of the current adjusting circuit 113B is largerThe fewer the number of paths in the path that are turned on. Under this condition, the signal S is outputO2Large and current IC2Is smaller. Conversely, when the number of paths conducted in the at least one current path of the amplifying circuit 113A is smaller, the number of paths conducted in the at least one current path of the current adjusting circuit 113B is larger. Under this condition, the signal S is outputO2Small and current IC2Is relatively large. In some embodiments, at least one bit SC2[i]Complementary to at least one bit SC2[j]. In this way, the amplification gain of the output stage 113 can be controlled according to the control signal SC2And (4) setting.
For example, as shown in fig. 3, the amplifying circuit 113A includes a current path B2 and a current path B3 connected in parallel, and the current adjusting circuit 113B includes a current path B4 and a current path B5 connected in parallel. When the current path B2 and the current path B3 are both turned on, the current path B4 and the current path B5 are turned off. Under this condition, the signal S is outputO2With a higher current value. Equivalently, the output stage circuit 113 has a high amplification gain. When current path B2 is on and current path B3 is off, current path B4 is on and current path B5 is off. Under this condition, the signal S is outputO2With a lower current value. Equivalently, the output stage circuit 113 has a low amplification gain.
The current path B2 and the current path B3 are coupled in parallel, coupled between the inductor L2 and the node ND, and have the same circuit structure. Taking the current path B2 as an example, the current path B2 includes a transistor N5. A first terminal of the transistor N5 is coupled to the inductor L2, a second terminal of the transistor N5 is coupled to the node ND, and a control terminal of the transistor N5 is configured to receive the control signal SC2At least one bit (i.e. S) ofC2[i]). When transistor N5 responds to bit SC2[i]When conducting, the current path B2 generates the output signal SO2。
Similarly, the current path B4 and the current path B5 are coupled in parallel to each other, coupled between a voltage source providing the voltage VDD and the node ND, and have the same circuit structure. Taking the current path B4 as an example, the current path B4 includes a transistor N6. A first terminal of the transistor N6 is coupled to the voltage sourceA second terminal of the transistor N6 is coupled to the node ND, and a control terminal of the transistor N6 is configured to receive the control signal SC2At least one bit (i.e. S) ofC2[j]). When transistor N6 responds to bit SC2[j]When conducting, current path B4 generates current IC2。
The number of current paths shown in fig. 3 is for example only, and the present disclosure is not limited thereto. The number of current paths can be adjusted accordingly according to different requirements. Accordingly, various numbers of current paths are within the scope of the present disclosure.
The above circuit arrangement is used for example, and the disclosure is not limited thereto. In some embodiments, the input stage circuit 111 may include a plurality of transistors according to the input signal SINTurned on to provide a plurality of bias signals to the output stage circuit 112 and the output stage circuit 113, respectively.
The transistor type (P-type or N-type) and the transistor element (e.g., MOSFET) shown in fig. 2 and 3 are only examples, and the disclosure is not limited to these examples. Various transistor forms or elements of the LNA circuit 110 that can perform the same function are all within the scope of the present disclosure.
In summary, some embodiments of the present disclosure provide a receiver apparatus using a low noise amplifier that can provide multiple gains to process multiple wireless signals with different powers. In this way, when a plurality of wireless signals are received simultaneously, it can be ensured that the wireless signals can be efficiently amplified to reduce the influence of noise.
Although the embodiments of the present disclosure have been described above, the embodiments are not intended to limit the present disclosure, and those skilled in the art can make variations on the technical features of the present disclosure according to the explicit or implicit contents of the present disclosure, and all such variations may fall within the scope of patent protection sought by the present disclosure, in other words, the scope of patent protection of the present disclosure should be subject to the claims of the present specification.

Claims (10)

1. A low noise amplifier circuit, comprising:
an input stage circuit for receiving an input signal via an antenna and generating a bias signal;
a first output stage circuit corresponding to a first wireless communication and biased according to the bias signal and a first control signal to generate a first output signal, wherein the first control signal is used for setting a first amplification gain of the first output stage circuit; and
a second output stage circuit corresponding to a second wireless communication and biased according to the bias signal and a second control signal for generating a second output signal, wherein the second control signal is used for setting a second amplification gain of the second output stage circuit.
2. The lna circuit of claim 1, wherein the input stage circuit, the first output stage circuit and the second output stage circuit operate as a current mirror circuit.
3. The low noise amplifier circuit of claim 1, wherein the input stage circuit comprises:
a first transistor, for conducting according to the input signal; and
a second transistor coupled between a voltage source and the first transistor and configured to operate as a diode-type transistor to generate the bias signal.
4. The low noise amplifier circuit of claim 1, wherein the first output stage circuit comprises at least one current path configured to be turned on according to the first control signal to generate the first output signal, and each of the at least one current path comprises:
a third transistor, biased by the bias signal, for generating the first output signal; and
a fourth transistor coupled to the third transistor and turned on according to the first control signal to output the first output signal.
5. The LNA circuit of claim 4, where the higher the first amplification gain, the greater the number of paths in the at least one current path that are turned on.
6. The lna circuit of claim 1, wherein the input stage circuit, the first output stage circuit and the second output stage circuit operate as a current-steering circuit.
7. The low noise amplifier circuit of claim 1, wherein the first output stage circuit comprises:
an amplifying circuit for generating the first output signal according to the bias signal and the first control signal; and
a current adjusting circuit for adjusting a current flowing through the amplifying circuit according to the first control signal to set the first amplification gain.
8. The low noise amplifier circuit of claim 7, wherein the amplifying circuit comprises at least one current path configured to be turned on according to the first control signal to generate the first output signal, and each of the at least one current path comprises:
a transistor, which is turned on according to the first control signal to generate the first output signal.
9. The lna circuit of claim 7, wherein the current regulation circuit comprises at least one current path that is turned on according to the first control signal to generate a first current, and each of the at least one current path comprises:
a transistor, configured to be turned on according to the first control signal to generate the first current, wherein the first current is smaller if the first amplification gain is higher.
10. The lna circuit of claim 9, wherein the sum of the first current and the first output signal is a predetermined multiple of the bias signal.
CN201911074912.2A 2019-11-06 2019-11-06 Low noise amplifier circuit with multiple amplification gains Pending CN112769406A (en)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7135894B1 (en) * 2002-09-13 2006-11-14 National Semiconductor Corporation Dual-output current driver
US7190299B2 (en) * 2002-11-28 2007-03-13 Sanyo Electric Co., Ltd. Current control method and application thereof
GB2436651B (en) * 2006-03-30 2008-02-20 Matsushita Electric Ind Co Ltd Variable gain low noise amplifier
US20130043955A1 (en) * 2010-09-06 2013-02-21 Mediatek Inc. Signal amplification circuits for receiving/transmitting signals according to input signal
US9774303B1 (en) * 2015-08-25 2017-09-26 Marvell International Ltd. Low-noise amplifier for intra-band non contiguous carrier agregation

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7135894B1 (en) * 2002-09-13 2006-11-14 National Semiconductor Corporation Dual-output current driver
US7190299B2 (en) * 2002-11-28 2007-03-13 Sanyo Electric Co., Ltd. Current control method and application thereof
GB2436651B (en) * 2006-03-30 2008-02-20 Matsushita Electric Ind Co Ltd Variable gain low noise amplifier
US20130043955A1 (en) * 2010-09-06 2013-02-21 Mediatek Inc. Signal amplification circuits for receiving/transmitting signals according to input signal
US9774303B1 (en) * 2015-08-25 2017-09-26 Marvell International Ltd. Low-noise amplifier for intra-band non contiguous carrier agregation

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