CN112768445A - Silicon controlled rectifier structure for electrostatic protection - Google Patents

Silicon controlled rectifier structure for electrostatic protection Download PDF

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Publication number
CN112768445A
CN112768445A CN202110111482.8A CN202110111482A CN112768445A CN 112768445 A CN112768445 A CN 112768445A CN 202110111482 A CN202110111482 A CN 202110111482A CN 112768445 A CN112768445 A CN 112768445A
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type
doped region
heavily doped
region
type heavily
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凌盛
张泽飞
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Shanghai Analog Semiconductor Technology Co ltd
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Shanghai Analog Semiconductor Technology Co ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203Particular design considerations for integrated circuits
    • H01L27/0248Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0259Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements
    • H01L27/0262Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements including a PNP transistor and a NPN transistor, wherein each of said transistors has its base coupled to the collector of the other transistor, e.g. silicon controlled rectifier [SCR] devices

Abstract

The application discloses silicon controlled rectifier structure for electrostatic protection includes: a semiconductor substrate; the first N-type well region and the first P-type well region are positioned in the semiconductor substrate and are adjacent; the N-type lightly doped region is positioned in the first N-type well region, a first N-type heavily doped region close to the surface of the semiconductor substrate is formed in the N-type lightly doped region, and a first P-type heavily doped region and a second N-type heavily doped region are sequentially formed around the first N-type lightly doped region; the P-type lightly doped region is positioned in the first P-type well region, and a third N-type heavily doped region, a second P-type heavily doped region and a fourth N-type heavily doped region which are close to the surface of the semiconductor substrate are respectively formed in the P-type lightly doped region; covering a part of the polysilicon layer of the first N-type well region and the first P-type well region, wherein each heavily doped region is exposed by the polysilicon layer; the first N-type heavily doped region and the first P-type heavily doped region are connected with the anode, and the third N-type heavily doped region, the second P-type heavily doped region and the fourth N-type heavily doped region are connected with the cathode, so that the ESD release capacity is improved.

Description

Silicon controlled rectifier structure for electrostatic protection
Technical Field
The invention belongs to the technical field of integrated circuits, and particularly relates to a silicon controlled rectifier structure for electrostatic protection.
Background
Electrostatic discharge (ESD) is an objective natural phenomenon that accompanies the entire cycle of chip production. From the manufacturing, packaging, testing to application stages of the chip, certain charges are accumulated in the external environment and the internal structure of the chip, so that the product is threatened by static electricity at any time. Therefore, in chip design, ESD protection devices are required to be placed at each pin for protecting the chip from power-off and power-on states.
A Silicon Controlled Rectifier (SCR) circuit applied to electrostatic protection in the prior art includes a PNP transistor and an NPN transistor. In the operation process of a traditional SCR structure, when the operating voltage is lower than a trigger voltage Vt1, the SCR cannot be started, when the voltage exceeds Vt1, the voltage of the SCR drops along with the rise of current, when the voltage reaches Vh, the current rapidly increases, the voltage of the SCR slowly rises until the voltage rises to a secondary breakdown voltage Vt2, the process is a stage of releasing the current, namely an ESD discharge process, and the size of the secondary breakdown current It2 is a mark of the ESD protection capability of a device. The trigger voltage Vt1 of the conventional SCR structure is too high, the second breakdown current It2 is too low, and the ESD protection capability is insufficient.
Disclosure of Invention
An object of the embodiments of the present disclosure is to provide a thyristor structure for electrostatic protection, which improves ESD discharge capability.
The application discloses silicon controlled rectifier structure for electrostatic protection contains:
a semiconductor substrate;
the first P-type well region and the first N-type well region are positioned in the semiconductor substrate and are adjacent;
the P-type lightly doped region is positioned in the first P-type well region, and a first N-type heavily doped region, a first P-type heavily doped region and a second N-type heavily doped region which are close to the surface of the semiconductor substrate and are sequentially arranged are respectively formed in the P-type lightly doped region;
the N-type lightly doped region is positioned in the first N-type well region, a third N-type heavily doped region close to the surface of the semiconductor substrate is formed in the N-type lightly doped region, and a second P-type heavily doped region and a fourth N-type heavily doped region are sequentially formed around the N-type lightly doped region;
covering a portion of the polysilicon layer of the first N-type well region and the first P-type well region, the polysilicon layer exposing each of the heavily doped regions;
the first N-type heavily doped region, the first P-type heavily doped region and the second N-type heavily doped region are connected with a cathode, and the third N-type heavily doped region and the second P-type heavily doped region are connected with an anode.
In a preferred embodiment, the third N-type heavily doped region includes multiple P-type heavily doped regions at intervals.
The application discloses silicon controlled rectifier structure for electrostatic protection contains:
a semiconductor substrate;
the first P-type well region and the first N-type well region are positioned in the semiconductor substrate and are adjacent;
the P-type lightly doped region is positioned in the first P-type well region, and a first N-type heavily doped region, a first P-type heavily doped region and a second N-type heavily doped region which are close to the surface of the semiconductor substrate and are sequentially arranged are respectively formed in the P-type lightly doped region;
the N-type lightly doped region is positioned in the first N-type well region, and a third N-type heavily doped region, a second P-type heavily doped region and a fourth N-type heavily doped region which are close to the surface of the semiconductor substrate and are sequentially arranged are formed in the N-type lightly doped region;
covering a portion of the polysilicon layer of the first N-type well region and the first P-type well region, the polysilicon layer exposing each of the heavily doped regions;
the first N-type heavily doped region, the first P-type heavily doped region and the second N-type heavily doped region are connected with a cathode, and the third N-type heavily doped region, the second P-type heavily doped region and the fourth N-type heavily doped region are connected with an anode.
In a preferred embodiment, the second P-type heavily doped region includes multiple segments of N-type heavily doped regions at intervals.
In a preferred embodiment, the semiconductor substrate includes an N-type buried layer, and the first N-type well region and the first P-type well region are located above the N-type buried layer.
In a preferred embodiment, a P-type well region located above the N-type buried layer is formed in the first N-type well region.
In a preferred embodiment, the method further comprises the following steps: the second P type well region and the second N type well region are sequentially located on one side, away from the first P type well region, of the first N type well region, a third P type heavily doped region close to the surface of the semiconductor is formed in the second P type well region, the third P type heavily doped region is connected with the cathode, a fifth N type heavily doped region close to the surface of the semiconductor is formed in the second N type well region, and the fifth N type heavily doped region is connected with the anode.
In a preferred embodiment, a P-type heavily doped region located in the semiconductor substrate and close to the semiconductor surface is formed on one side of the second N-type well region, and the P-type heavily doped region is connected to a ground terminal.
In a preferred embodiment, the P-type lightly doped region includes a first P-type lightly doped region and a second P-type lightly doped region, the first P-type lightly doped region is located in the first P-type well region, the second P-type lightly doped region is located in the first P-type lightly doped region and has a doping concentration higher than that of the first P-type lightly doped region, and the first N-type heavily doped region, the first P-type heavily doped region, and the second N-type heavily doped region are formed in the second P-type lightly doped region.
In a preferred embodiment, the P-type lightly doped region includes a first P-type lightly doped region and a second P-type lightly doped region, the first P-type lightly doped region is located in the first P-type well region, and the second P-type lightly doped region is located in the first P-type lightly doped region and has a higher doping concentration than the first P-type lightly doped region.
In a preferred embodiment, the semiconductor substrate is a P-type semiconductor substrate.
Compared with the prior art, the silicon controlled structure for electrostatic protection has the following beneficial effects:
the silicon controlled structure can improve the trigger voltage Vh and/or the secondary breakdown current It2, improve the ESD discharge capacity and enhance the device performance.
A large number of technical features are described in the specification, and are distributed in various technical solutions, so that the specification is too long if all possible combinations of the technical features (namely, the technical solutions) in the application are listed. In order to avoid this problem, the respective technical features disclosed in the above summary of the invention of the present specification, the respective technical features disclosed in the following embodiments and examples, and the respective technical features disclosed in the drawings may be freely combined with each other to constitute various new technical solutions (which should be regarded as having been described in the present specification) unless such a combination of the technical features is technically impossible. For example, in one example, the feature a + B + C is disclosed, in another example, the feature a + B + D + E is disclosed, and the features C and D are equivalent technical means for the same purpose, and technically only one feature is used, but not simultaneously employed, and the feature E can be technically combined with the feature C, then the solution of a + B + C + D should not be considered as being described because the technology is not feasible, and the solution of a + B + C + E should be considered as being described.
Drawings
The appended drawings illustrate only exemplary embodiments of this invention and therefore do not limit its scope because the inventive concepts lend themselves to other equally effective embodiments.
Fig. 1 is a cross-sectional view of a thyristor structure for electrostatic protection according to an embodiment of the invention.
Fig. 2 is a partial top view of a thyristor structure for electrostatic protection according to a third embodiment of the present invention.
Fig. 3 is a cross-sectional view of a thyristor structure for electrostatic protection according to a second embodiment of the invention.
Fig. 4 is a partial top view of a thyristor structure for electrostatic protection according to a fourth embodiment of the invention.
Fig. 5 is a partial top view of a thyristor structure for electrostatic protection according to a fifth embodiment of the invention.
Fig. 6 is a cross-sectional view of a thyristor structure for electrostatic protection according to a sixth embodiment of the invention.
Fig. 7 is a cross-sectional view of a thyristor structure for electrostatic protection in a seventh embodiment of the invention.
Description of reference numerals:
101. 301, 601, 701: semiconductor substrate
102. 302, 602, 703: n-type buried layer
103. 116, 303, 316, 603, 616, 703, 716: p-type well region
104. 304, 604, 704: p-type shallow doped region
105. 305, 605, 705: p-type shallow doped region
106. 306, 606, 706: deep doped P-well
107. 118, 307, 318, 607, 618, 707, 718: n-type well region
108. 208, 308, 408, 608, 708: n-type shallow doped region
110. 113, 117, 120, 214, 221, 310, 313, 317, 320, 413, 610, 613, 617, 620, 622, 710, 713, 717, 720, 721: p-type heavily doped region
109. 111, 112, 114, 119, 212, 309, 310, 312, 314, 319, 412, 414, 421, 609, 611, 612, 614, 619, 621, 623, 709, 711, 712, 714, 719, 722: n-type heavily doped region
501-504: line of
Detailed Description
In the following description, numerous technical details are set forth in order to provide a better understanding of the present application. However, it will be understood by those skilled in the art that the technical solutions claimed in the present application may be implemented without these technical details and with various changes and modifications based on the following embodiments.
Several different embodiments are presented below in accordance with different features of the invention. The particular elements and arrangements of parts in the present invention are provided for simplicity and clarity and should not be construed as limitations on the invention described herein. For example, the description of forming a first element over a second element can include embodiments in which the first and second elements are in direct contact, as well as embodiments in which additional elements are formed between the first and second elements such that the first and second elements are not in direct contact. Moreover, the present invention may be represented in different examples by repeated symbols and/or letters without necessarily implying any particular relationship between such embodiments and/or structures.
Furthermore, spatially relative terms, such as "above," "below," "upper," "lower," and the like, may be used in the embodiments to facilitate describing a relationship between one element(s) or feature(s) and another element(s) or feature(s) in the drawings. These spatial relationships include the various orientations of the device in use or operation and the orientation depicted in the figures. The device may be oriented in different directions (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
It will be understood that when a layer is "on" another layer or substrate, it can be directly on the other layer or substrate or intervening layers may also be present.
Example one
The first embodiment of the application discloses a silicon controlled rectifier structure for electrostatic protection, which comprises a semiconductor substrate, a first P-type well region and a first N-type well region which are adjacent to each other and are positioned in the semiconductor substrate, a P-type lightly doped region positioned in the first P-type well region and an N-type lightly doped region positioned in the first N-type well region. The first N-type heavily doped region, the first P-type heavily doped region and the second N-type heavily doped region are formed in the P-type lightly doped region, are close to the surface of the semiconductor substrate and are sequentially arranged, and the first N-type heavily doped region, the first P-type heavily doped region and the second N-type heavily doped region are connected with the cathode. And a third N-type heavily doped region close to the surface of the semiconductor substrate is formed in the N-type lightly doped region, a second P-type heavily doped region and a fourth N-type heavily doped region are sequentially formed around the N-type lightly doped region, and the third N-type heavily doped region and the second P-type heavily doped region are connected with the anode. The silicon controlled structure also comprises a polysilicon layer covering part of the first N-type well region and the first P-type well region, and the polysilicon layer exposes each heavily doped region.
Fig. 1 is a cross-sectional view of a thyristor structure for electrostatic protection according to an embodiment of the invention. The thyristor structure in this embodiment includes a semiconductor substrate (e.g., a P-type semiconductor substrate) 101, an N-type buried layer (NBL)102 on the semiconductor substrate 101, a deeply doped P-well (DPW)106, an N-well (HVNW)107, and a P-well (HVPW)103 on the N-type buried layer 102, a P-type lightly doped region (SH _ P)104 in the P-well 103, a P-type lightly doped region (HVPB)105 with a higher doping concentration in the P-type lightly doped region 104, and an N-type lightly doped region (SH _ N)108 in the N-well 107. In this embodiment, the scr structure includes a plurality of P-type well regions and N-type well regions, which are spaced apart from each other. The doping depth of the P-well 103, the P-type lightly doped region (SH _ P)104 and the P-type lightly doped region (HVPB)105 is gradually reduced, and the doping concentration is gradually increased, so that the voltage resistance characteristic of the device can be enhanced.
An N-type heavily doped region (N +)109, a P-type heavily doped region (P +)110 and an N-type heavily doped region (N +)111 are formed in the P-type lightly doped region HVPB, the N-type heavily doped region 109, the P-type heavily doped region 110 and the N-type heavily doped region 111 are connected with a cathode NG, an N-type heavily doped region (N +)112 is formed in the N-type lightly doped region 108, a P-type heavily doped region (P +)113 and an N-type heavily doped region (N +)114 are formed around the N-type lightly doped region 108, the N-type heavily doped region 112 in the N-type lightly doped region 108 and the external P-type heavily doped region 113 are connected with an anode POS, a polysilicon gate 115 is formed on the P-type well region 103 and the N-type well region 107, and each heavily doped region 109 to.
In the first embodiment of the invention shown in fig. 1, the SCR structure can reduce the width of the N well region of the PNP, and the amplification factor of the PNP is increased, so that the second breakdown current It2 is increased, and the ESD discharging capability is improved.
Example two
The thyristor structure for electrostatic protection in the second embodiment is basically the same as the thyristor structure in the first embodiment, and the main difference is that: the third heavily doped N-type region in this embodiment includes multiple P-type heavily doped regions at intervals.
Fig. 2 is a top view of a thyristor structure for electrostatic protection according to a second embodiment of the present invention, where the top view only shows a partial structure. In this embodiment, the N-type heavily doped regions (N +)212 in the N-type lightly doped region (SH _ N)208 form a plurality of P-type heavily doped regions 221 at intervals. In this embodiment, the area of the P-type heavily doped region 211 can be further increased by replacing part of the N-type heavily doped region 212 with the P-type heavily doped region 221, and more small SCRs can be added, so as to improve the second breakdown current It2 and improve the ESD discharging capability.
EXAMPLE III
The third embodiment of the present application discloses a thyristor structure for electrostatic protection, which includes: the semiconductor substrate, the first P-type well region and the first N-type well region which are adjacent in the semiconductor substrate, the P-type lightly doped region which is positioned in the first P-type well region, and the N-type lightly doped region which is positioned in the first N-type well region. The P-type lightly doped region is respectively provided with a first N-type heavily doped region, a first P-type heavily doped region and a second N-type heavily doped region which are close to the surface of the semiconductor substrate and are sequentially arranged, and the first N-type heavily doped region, the first P-type heavily doped region and the second N-type heavily doped region are connected with a cathode. And a third N-type heavily doped region, a second P-type heavily doped region and a fourth N-type heavily doped region which are close to the surface of the semiconductor substrate and are sequentially arranged are formed in the N-type lightly doped region, and the third N-type heavily doped region, the second P-type heavily doped region and the fourth N-type heavily doped region are connected with an anode. The silicon controlled structure also comprises a polysilicon layer covering part of the first N-type well region and the first P-type well region, and the polysilicon layer exposes each heavily doped region.
Fig. 3 is a cross-sectional view of a thyristor structure for electrostatic protection according to a third embodiment of the invention. The silicon controlled structure comprises a semiconductor substrate 301, an N-type buried layer (NBL)302 positioned on the semiconductor substrate 301, a deep doped P-well (DPW)306 positioned on the N-type buried layer 302, an N-well (HVNW)307 and a P-well (HVPW)303, a P-type lightly doped region (SH _ P)304 positioned in the P-well 303, a P-type lightly doped region (HVPB)305 with higher doping concentration positioned in the P-type lightly doped region 304, and an N-type lightly doped region (SH _ N)308 positioned in the N-well 307, wherein the P-type lightly doped region HVPB is provided with an N-type heavily doped region (N +)309, a P-type heavily doped region (P +)310 and an N-type heavily doped region (N +)311, the N-type heavily doped region 309, the P-type heavily doped region 310 and the N-type heavily doped region 311 are connected with a cathode NG, the N-type lightly doped region (SH _ N)308 is provided with an N-type heavily doped region (N +), a P-type heavily doped region (P) 312, a, the N-type heavily doped region (N +)312, the P-type heavily doped region (P +)313 and the N-type heavily doped region (N +)314 are connected with the anode POS, a polysilicon gate is formed on the P-type well region HVPW and the N-type well region HVNW, and the polysilicon gate exposes the heavily doped regions 309 to 314.
In the third embodiment of the invention shown in fig. 3, the SCR structure can relatively increase the area of the N-well region, and the resistance of the N-well region is reduced, so that the holding voltage Vh is increased, and the ESD discharging capability is improved.
In this embodiment, the ESD current is drained from the ground terminal VSS.
Example four
The thyristor structure for electrostatic protection in the fourth embodiment is basically the same as the thyristor structure in the third embodiment, and the main difference is that: in this embodiment, the second P-type heavily doped region includes a plurality of segments of N-type heavily doped regions at intervals.
Fig. 4 is a top view of a thyristor structure for electrostatic protection according to an embodiment of the invention, which shows only a partial structure. In this embodiment, the P-type heavily doped regions (P +)413 in the N-type lightly doped region (SH _ N)408 form a plurality of segments of N-type heavily doped regions 421 at intervals. In this embodiment, the part of the P-type heavily doped region 413 is replaced with the N-type heavily doped region 421, so that the relative area of the N-well region can be further increased, and the resistance of the N-well region can be reduced, thereby increasing Vh and further improving ESD discharging capability.
EXAMPLE five
Fig. 5 is a top view of a thyristor structure for electrostatic protection according to an embodiment of the present invention, which is a combination of the embodiments shown in fig. 1 and 3, and the top view shows only a partial structure. It should be noted that only each heavily doped region in the N-type lightly doped region SH _ N is shown in the figure, N +, P +, N + sequentially arranged in the first row 501 and the third row 503 may be used to represent the N-type heavily doped region 112, the P-type heavily doped region 113, and the N-type heavily doped region 114 in fig. 1, and P +, N +, P + sequentially arranged in the second row 502 and the fourth row 504 may be used to represent the N-type heavily doped region 312, the P-type heavily doped region 313, and the N-type heavily doped region 314 in fig. 3. The SCR structure in the first embodiment of fig. 1 can relatively reduce the width of the N-well region of the PNP, and the amplification factor of the PNP is increased, so that the second breakdown current It2 is increased, and the SCR structure in the third embodiment of fig. 3 can relatively increase the area of the N-well region, and the resistance of the N-well region is reduced, so that the sustain voltage Vh is increased. It should be understood that a plurality of thyristor structures may be included in the semiconductor substrate, and the structures of fig. 1 and fig. 3 may be simultaneously used between the plurality of thyristor structures, that is, the second breakdown current It2 and the holding voltage Vh may be simultaneously increased, further improving the overall ESD discharging capability.
EXAMPLE six
Fig. 6 is a cross-sectional view of a thyristor structure for electrostatic protection in accordance with an embodiment of the present invention. In fig. 6, a part of the N-type lightly doped region 608 is formed with an N-type heavily doped region 612, a part of the N-type lightly doped region 608 is formed with a P-type heavily doped region 613 and an N-type heavily doped region 614 around the N-type lightly doped region 608, the N-type heavily doped region 612 and an external P-type heavily doped region 613 in the N-type lightly doped region 608 are connected to the anode POS, a part of the N-type lightly doped region 608 is formed with an N-type heavily doped region 621, a P-type heavily doped region 622 and an N-type heavily doped region 623, and the N-type heavily doped region 621, the P-type heavily doped region 622 and the N-type heavily doped region 623 are connected to the anode POS, fig. 6 includes a plurality of SCR structures, adjacent SCR structures may respectively adopt the SCR structures shown in the first embodiment and the third embodiment, wherein the SCR structures in the first embodiment can relatively reduce the width of the N well region of the PNP, the amplification factor of the PNP is increased, so that the second breakdown, therefore, the holding voltage Vh is increased, so that the secondary breakdown current It2 and the holding voltage Vh can be increased simultaneously in the embodiment, the overall ESD discharging capability is further improved, and the device performance is enhanced.
EXAMPLE seven
Fig. 7 is a cross-sectional view of a thyristor structure for electrostatic protection in accordance with an embodiment of the present invention. In fig. 7, an N-type lightly doped region 708 is formed with an N-type heavily doped region 712, a P-type heavily doped region 721 and an N-type heavily doped region 722, a P-type heavily doped region 713 and an N-type heavily doped region 714 are formed around the N-type lightly doped region 708, the N-type heavily doped region 712, the P-type heavily doped region 721 and the N-type heavily doped region 722 in the N-type lightly doped region 708 and the external P-type heavily doped region 713 are connected to an anode POS, an SCR structure in fig. 7 can simultaneously include the SCR structures shown in the first and third embodiments, wherein the SCR structure in the first embodiment can relatively reduce the width of the N-well region of the PNP, the amplification factor of the PNP is increased, so that the secondary breakdown current It2 is increased, the SCR structure in the third embodiment can relatively increase the area of the N-well region, the resistance of the N-well region is reduced, so that the sustain voltage Vh is increased, so that the secondary breakdown current It2 and the sustain voltage Vh, further improving the whole ESD discharge capacity and enhancing the performance of the device.
It is noted that, in the present patent application, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, the use of the verb "comprise a" to define an element does not exclude the presence of another, same element in a process, method, article, or apparatus that comprises the element. In the present patent application, if it is mentioned that a certain action is executed according to a certain element, it means that the action is executed according to at least the element, and two cases are included: performing the action based only on the element, and performing the action based on the element and other elements. The expression of a plurality of, a plurality of and the like includes 2, 2 and more than 2, more than 2 and more than 2.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (10)

1. A thyristor structure for electrostatic protection, comprising:
a semiconductor substrate;
the first P-type well region and the first N-type well region are positioned in the semiconductor substrate and are adjacent;
the P-type lightly doped region is positioned in the first P-type well region, and a first N-type heavily doped region, a first P-type heavily doped region and a second N-type heavily doped region which are close to the surface of the semiconductor substrate and are sequentially arranged are respectively formed in the P-type lightly doped region;
the N-type lightly doped region is positioned in the first N-type well region, a third N-type heavily doped region close to the surface of the semiconductor substrate is formed in the N-type lightly doped region, and a second P-type heavily doped region and a fourth N-type heavily doped region are sequentially formed around the N-type lightly doped region;
covering a portion of the polysilicon layer of the first N-type well region and the first P-type well region, the polysilicon layer exposing each of the heavily doped regions;
the first N-type heavily doped region, the first P-type heavily doped region and the second N-type heavily doped region are connected with a cathode, and the third N-type heavily doped region and the second P-type heavily doped region are connected with an anode.
2. The silicon controlled rectifier structure for electrostatic protection as claimed in claim 1, wherein said third heavily N-doped region comprises a plurality of segments of P-doped regions spaced apart.
3. A thyristor structure for electrostatic protection, comprising:
a semiconductor substrate;
the first P-type well region and the first N-type well region are positioned in the semiconductor substrate and are adjacent;
the P-type lightly doped region is positioned in the first P-type well region, and a first N-type heavily doped region, a first P-type heavily doped region and a second N-type heavily doped region which are close to the surface of the semiconductor substrate and are sequentially arranged are respectively formed in the P-type lightly doped region;
the N-type lightly doped region is positioned in the first N-type well region, and a third N-type heavily doped region, a second P-type heavily doped region and a fourth N-type heavily doped region which are close to the surface of the semiconductor substrate and are sequentially arranged are formed in the N-type lightly doped region;
covering a portion of the polysilicon layer of the first N-type well region and the first P-type well region, the polysilicon layer exposing each of the heavily doped regions;
the first N-type heavily doped region, the first P-type heavily doped region and the second N-type heavily doped region are connected with a cathode, and the third N-type heavily doped region, the second P-type heavily doped region and the fourth N-type heavily doped region are connected with an anode.
4. The silicon controlled rectifier structure for electrostatic protection as claimed in claim 1, wherein said second heavily P-doped region comprises a plurality of segments of heavily N-doped regions spaced apart.
5. The silicon controlled structure for electrostatic protection according to any one of claims 1 to 4, wherein an N-type buried layer is included in the semiconductor substrate, and the first N-type well region and the first P-type well region are located above the N-type buried layer.
6. The SCR structure of any one of claims 1 to 4, wherein the first N-type well region has a P-type well region formed therein over the buried N-type layer.
7. The thyristor structure for electrostatic protection according to any one of claims 1 to 4, further comprising: the second P type well region and the second N type well region are sequentially located on one side, away from the first P type well region, of the first N type well region, a third P type heavily doped region close to the surface of the semiconductor is formed in the second P type well region, the third P type heavily doped region is connected with the cathode, a fifth N type heavily doped region close to the surface of the semiconductor is formed in the second N type well region, and the fifth N type heavily doped region is connected with the anode.
8. The SCR structure of claim 7, wherein the second N-type well region is formed with a heavily doped P-type region in the semiconductor substrate and close to the semiconductor surface, and the heavily doped P-type region is connected to ground.
9. The SCR structure of claim 1 or 4, wherein the P-type lightly doped region comprises a first P-type lightly doped region and a second P-type lightly doped region, the first P-type lightly doped region is located in the first P-type well region, the second P-type lightly doped region is located in the first P-type lightly doped region and has a doping concentration higher than that of the first P-type lightly doped region, and the first N-type heavily doped region, the first P-type heavily doped region and the second N-type heavily doped region are formed in the second P-type lightly doped region.
10. The silicon controlled rectifier structure for electrostatic protection according to claim 1 or 4, wherein the semiconductor substrate is a P-type semiconductor substrate.
CN202110111482.8A 2021-01-27 2021-01-27 Silicon controlled rectifier structure for electrostatic protection Pending CN112768445A (en)

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