CN112768366A - Semiconductor structure and preparation method thereof - Google Patents
Semiconductor structure and preparation method thereof Download PDFInfo
- Publication number
- CN112768366A CN112768366A CN202110087124.8A CN202110087124A CN112768366A CN 112768366 A CN112768366 A CN 112768366A CN 202110087124 A CN202110087124 A CN 202110087124A CN 112768366 A CN112768366 A CN 112768366A
- Authority
- CN
- China
- Prior art keywords
- test
- substrate
- circuit block
- insulating layer
- voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 43
- 238000002360 preparation method Methods 0.000 title abstract description 6
- 238000012360 testing method Methods 0.000 claims abstract description 249
- 239000000758 substrate Substances 0.000 claims abstract description 85
- 238000002955 isolation Methods 0.000 claims abstract description 82
- 230000000149 penetrating effect Effects 0.000 claims abstract description 15
- 239000000463 material Substances 0.000 claims description 14
- 238000000034 method Methods 0.000 claims description 12
- 229910052710 silicon Inorganic materials 0.000 claims description 12
- 239000010703 silicon Substances 0.000 claims description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 10
- 230000004888 barrier function Effects 0.000 claims description 10
- 239000004020 conductor Substances 0.000 claims description 10
- 239000011810 insulating material Substances 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 5
- 239000002184 metal Substances 0.000 abstract description 25
- 230000008021 deposition Effects 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 238000001514 detection method Methods 0.000 description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000003313 weakening effect Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000011156 evaluation Methods 0.000 description 1
- 238000011165 process development Methods 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Integrated Circuits (AREA)
- Element Separation (AREA)
Abstract
The invention provides a semiconductor structure and a preparation method thereof, comprising the following steps: a substrate having a plurality of circuit blocks, the substrate having a first surface and a second surface opposite to the first surface, at least one isolation structure penetrating the substrate to electrically isolate the circuit blocks, an insulating layer disposed on the first surface of the substrate, and multiple test components arranged on the insulating layer and above the longitudinal projection of a corresponding circuit block, wherein two of the plurality of test parts are used for being applied with test voltages to enable the substrate voltages in the corresponding two circuit blocks to have a difference value, by arranging the test component on the insulating layer above the longitudinal projection of each circuit block and applying the test voltage to two of the circuit blocks, the substrate voltage in the two corresponding circuit blocks has a difference value, therefore, whether metal residues exist on the isolation structure can be judged by detecting the magnitude of leakage current between the two circuit blocks.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a semiconductor structure and a preparation method thereof.
Background
During the fabrication of integrated circuits, the evaluation of the reliability of the components of the integrated circuit is an important part of the process development, and Isolation structures are important components of each integrated circuit, such as TSI (Through Silicon Isolation) structures that electrically isolate the well regions of the integrated circuit to prevent leakage from the well regions.
However, in the existing process flow, there is no effective detection method for detecting whether there is a metal residue on the isolation structure in the semiconductor structure, and thus it is impossible to avoid the problem that the semiconductor structure fails in device performance due to the presence of the metal residue on the isolation structure.
Disclosure of Invention
The invention provides a semiconductor structure and a preparation method thereof, which effectively solve the problem that no effective detection method is available in the prior art to detect whether metal residues exist on an isolation structure in the semiconductor structure.
In order to solve the above problems, the present invention provides a semiconductor structure comprising:
the circuit comprises a substrate, a first circuit block, a second circuit block and a third circuit block, wherein the substrate comprises a plurality of circuit blocks and is provided with a first surface and a second surface which are opposite;
at least one isolation structure penetrating the substrate to electrically isolate the plurality of circuit blocks;
an insulating layer disposed on the first surface of the substrate;
the plurality of test components are arranged on the insulating layer, and each test component is positioned above the longitudinal projection of one corresponding circuit block;
wherein two of the plurality of test parts are used for being applied with test voltages so that the substrate voltages in the two corresponding circuit blocks have a difference value.
Further preferably, the isolation structure has a first length in a first transverse direction, and the test component has a second length in the first transverse direction, wherein the first length is not greater than the second length.
Further preferably, the plurality of test parts includes a first test part and a second test part which are provided on the same insulating layer, wherein:
the first test component has a first vertical distance from the first surface of the corresponding first circuit block and is applied with a first test voltage;
the second test component has a second vertical distance from the first surface of the corresponding second circuit block and is applied with a second test voltage;
and wherein the first vertical distance is equal to the second vertical distance, and the first test voltage is not equal to the second test voltage.
Further preferably, the plurality of test parts includes a first test part and a second test part which are provided on the same insulating layer, wherein:
the first test component has a first vertical distance from the first surface of the corresponding first circuit block and is applied with a first test voltage;
the second test component has a second vertical distance from the first surface of the corresponding second circuit block and is applied with a second test voltage;
and wherein the first vertical distance is not equal to the second vertical distance, and the first test voltage is equal to the second test voltage.
Further preferably, the plurality of test components includes a first test component and a second test component, wherein:
the first test component is arranged on the first insulating layer, has a first vertical distance with the first surface of the corresponding first circuit block, is applied with a first test voltage, and has a first relative dielectric constant;
the second test component is arranged on the second insulating layer, has a second vertical distance with the first surface of the corresponding second circuit block, is applied with a second test voltage, and has a second relative dielectric constant;
and wherein the first vertical distance is equal to the second vertical distance, the first test voltage is equal to the second test voltage, and the first relative permittivity is not equal to the second relative permittivity.
Further preferably, a first connection structure and a second connection structure are further formed in the insulating layer, the plurality of test components include a first test component and a second test component, the first connection structure electrically connects the first test component and the corresponding first circuit block, and the second connection structure electrically connects the second test component and the corresponding second circuit block, wherein a first test voltage is applied to the first test component, a second test voltage is applied to the second test component, and the first test voltage and the second test voltage are not equal to each other.
Further preferably, the two test components to which the test voltage is applied are located above a longitudinal projection of two sides of the same isolation structure.
In another aspect, the present invention further provides a method for manufacturing a semiconductor structure, where the method includes:
providing a substrate, wherein the substrate comprises a plurality of circuit blocks and is provided with a first surface and a second surface which are opposite;
forming at least one isolation structure through the substrate, the isolation structure electrically isolating the plurality of circuit blocks;
forming an insulating layer on the first surface of the substrate;
forming a plurality of test components on the insulating layer, wherein each test component is positioned above the longitudinal projection of one corresponding circuit block;
wherein two of the plurality of test parts are used for being applied with test voltages so that the substrate voltages in the two corresponding circuit blocks have a difference value.
Further preferably, the step of forming at least one isolation structure penetrating through the substrate specifically includes:
forming at least one isolation trench penetrating through the substrate and forming a plurality of through-silicon trenches penetrating through the substrate;
filling an insulating material in the isolation trench to form the isolation structure, and filling the same insulating material in the through silicon trench to form an insulating inner wall;
continuously and sequentially filling a barrier material and a conductive material in the through silicon trench to form a through silicon structure;
and etching to remove the residual barrier material and the conductive material on the first surface of the substrate.
The invention has the beneficial effects that: the present invention provides a semiconductor structure comprising: a substrate having a plurality of circuit blocks, the substrate having a first surface and a second surface opposite to the first surface, at least one isolation structure penetrating the substrate to electrically isolate the circuit blocks, an insulating layer disposed on the first surface of the substrate, and multiple test components arranged on the insulating layer and above the longitudinal projection of a corresponding circuit block, wherein two of the plurality of test parts are used for being applied with test voltages to enable the substrate voltages in the corresponding two circuit blocks to have a difference value, by arranging the test component on the insulating layer above the longitudinal projection of each circuit block and applying the test voltage to two of the circuit blocks, the substrate voltage in the two corresponding circuit blocks has a difference value, therefore, whether the isolation structure has metal residues or not can be detected by detecting whether the leakage current between the two corresponding circuit blocks is larger than a preset value or not.
Drawings
In order to more clearly illustrate the technical solution of the present invention, the drawings needed to be used in the description of the embodiments according to the present invention will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained based on these drawings without inventive effort.
Fig. 1 is a schematic cross-sectional view of a semiconductor structure according to a first embodiment of the present invention.
Fig. 2 is a schematic flow chart of a method for fabricating a semiconductor structure according to a first embodiment of the present invention.
FIG. 3 is a schematic flow chart illustrating a method for fabricating a semiconductor structure according to a first embodiment of the present invention.
Fig. 4 is a schematic cross-sectional view of a semiconductor structure according to a second embodiment of the present invention.
Fig. 5 is a schematic cross-sectional view of a semiconductor structure according to a third embodiment of the present invention.
Fig. 6 is a schematic cross-sectional view of a semiconductor structure according to a fourth embodiment of the present invention.
Detailed Description
The technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, it is to be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", and the like, indicate orientations and positional relationships based on those shown in the drawings, and are used only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be considered as limiting the present invention. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first", "second", may explicitly or implicitly include one or more of the described features. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.
In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; may be mechanically connected, may be electrically connected or may be in communication with each other; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
In the present invention, unless otherwise expressly stated or limited, "above" or "below" a first feature means that the first and second features are in direct contact, or that the first and second features are not in direct contact but are in contact with each other via another feature therebetween. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly under and obliquely below the second feature, or simply meaning that the first feature is at a lesser elevation than the second feature.
The following disclosure provides many different embodiments or examples for implementing different features of the invention. To simplify the disclosure of the present invention, the components and arrangements of specific examples are described below. Of course, they are merely examples and are not intended to limit the present invention. Furthermore, the present invention may repeat reference numerals and/or letters in the various examples, such repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. In addition, the present invention provides examples of various specific processes and materials, but one of ordinary skill in the art may recognize applications of other processes and/or uses of other materials.
The invention aims at solving the problem that in the existing semiconductor preparation process, because an effective detection method is not available for detecting whether metal residues exist on an isolation structure in a semiconductor structure, the semiconductor structure cannot avoid the problem that the performance of the device of the semiconductor structure is invalid due to the metal residues existing on the isolation structure.
Referring to fig. 1, fig. 1 is a schematic cross-sectional view of a semiconductor structure 100 according to a first embodiment of the present invention, in which components and relative positions of the components can be seen visually.
As shown in fig. 1, the semiconductor structure 100 includes a substrate 110, a plurality of isolation structures 120, an insulating layer 130, and a plurality of test features 140, wherein:
the substrate 110 includes a plurality of circuit blocks 111, and the substrate 110 has a first surface S opposite to the first surface1And a second surface S2；
The isolation structure 120 electrically isolates the plurality of circuit blocks 111 through the substrate 110;
an insulating layer 130 is disposed on the first surface S of the substrate 1101The above step (1);
the plurality of test members 140 are disposed on the insulating layer 130, and each test member is located above a longitudinal projection of a corresponding one of the plurality of circuit blocks 111;
wherein two of the plurality of test members 140 (e.g., the first test member 140 shown in fig. 1)aAnd a second test part 140b) For applying test voltage to two corresponding circuit blocks, such as the first circuit block 111 shown in FIG. 1aAnd a second circuit block 111bHas a difference in substrate voltage.
It should be noted that, in the present embodiment, the Isolation structure 120 may be a Through Silicon Isolation (TSI) structure for electrically isolating two adjacent circuit blocks 111aAnd 111bWhen there is metal residue on the isolation structure 120, the isolation structure 120 is not effective for the two circuit blocks 111 located at two sides thereofaAnd 111bThe two circuit blocks 111 are electrically isolated as a resultaAnd 111bA leakage current occurs between the two circuit blocks 111aAnd 111bWhen the two circuit blocks 111 are not normally operatedaAnd 111bWhen the leakage current between the two is too large, the two can even be isolatedThe structure 120 breaks down.
It is easily understood that, in the present embodiment, the test members 140 are disposed on the insulating layer 130 located above the longitudinal projection of each circuit block 111, and two of the test members 140, namely the first test member 140aAnd a second test part 140bTwo test parts 140 to which test voltages are applied by applying the test voltagesaAnd 140bTwo corresponding circuit blocks (first circuit block 111)aAnd a second circuit block 111b) Has a difference value so that the corresponding two circuit blocks 111 can be detectedaAnd 111bThe magnitude of the leakage current therebetween is used to determine whether there is metal residue on the isolation structure 120. Specifically, when the first circuit block 111aAnd a second circuit block 111bWhen there is no leakage current therebetween or the leakage current is smaller than a predetermined value, it can be determined that the first circuit block 111 is not located in the first circuit blockaAnd a second circuit block 111bThere is no metal residue on the isolation structures 120 between the first circuit blocks 111aAnd a second circuit block 111bWhen the leakage current therebetween is greater than the predetermined value, the first circuit block 111 is determinedaAnd a second circuit block 111bWith metal residue on the isolation structures 120 in between.
Specifically, the first test part 140 is testedaAnd a second test part 140bWhen the test voltage is applied, the test can be performed by gradually increasing the voltage from zero to the test voltage, or by directly applying a proper test voltage. Further, an exemplary material of the test part 140 may be a metal of a three-layer structure of Ti + TiN/Al/Ti + TiN, and an exemplary material of the isolation structure 120 may be silicon dioxide.
It should be noted that, in the present embodiment, the isolation structures 120 have a first length along the first transverse direction X parallel to the substrate 110, and the test component 140 has a second length along the first transverse direction X, it should be understood that, in order to ensure the accuracy of the test result, the first length of the isolation structures 120 is not greater than the second length of the test component 140. In other possible modifications of the present invention, a plurality of test components 140 may be disposed on the insulating layer 130 above the vertical projection of each circuit block 111, and the test component 140 closest to the same isolation structure 120 in the vertical direction is used for being tested by applying a test voltage, in this case, it is only necessary to ensure that the second length of the two test components 140 closest to the same isolation structure 120 in the vertical direction is greater than the first length of the isolation structure 120.
Further, in the present embodiment, the first circuit block 111 is testedaAnd a second circuit block 111bThe first test part 140 is tested to determine whether there is metal residue on the isolation structure 120aAnd a second test part 140bA test voltage is applied.
It should be noted that, because the first testing part 140aAnd a second test part 140bAre disposed on the same insulating layer 130, so that the first test part 140aAnd a first circuit block 111aAnd a second test member 140bAnd a second circuit block 111bThe relative dielectric constant of the medium therebetween is equal (i.e., the medium is equal to the first test member 140)aAnd a first circuit block 111aAnd a second test member 140bAnd a second circuit block 111bThe same degree of electric field weakening); meanwhile, since the first test part 140aAnd a first circuit block 111aFirst surface S of1Is equal to the second test member 140bAnd a second circuit block 111bFirst surface S of1A second vertical distance therebetween, and therefore, is applied to the first test part 140aApplying a first test voltage to the second test part 140bWhen the second test voltage is applied for testing, the first test voltage should not be equal to the second test voltage, so that the first circuit block 111 will be testedaAnd a second circuit block 111bThe coupled potentials are not equal, thereby making the first circuit block 111aAnd a second circuit block 111bHas a difference value so that it is possible to detect the first circuit block 111aAnd a second circuit block 111bThe magnitude of the leakage current therebetween is used to determine whether there is a metal residue on the isolation structure 120 therebetween.
It should be understood that, in the present embodiment, two test members 140 to which test voltages are appliedaAnd 140bOver the longitudinal projection of both sides of the same isolation structure 120, but since there are also situations where there are metal residues on a plurality of adjacent isolation structures 120, two test members 140 to which test voltages are appliedaAnd 140bOr above the longitudinal projection of the side edges of the different isolation structures 120, indicating that the two test parts 140 are tested when the tested leakage current is greater than a predetermined valueaAnd 140bWith metal residue on each of the plurality of isolation structures 120 therebetween.
Further, referring to fig. 1, in the present embodiment, the semiconductor structure 100 further includes a through-silicon structure 150 disposed in each of the circuit blocks 111 and penetrating the substrate 110, wherein the isolation structure 120 has a first width L1 along a second lateral direction Y parallel to the substrate 110, the through-silicon structure 150 has a second width L2 along the second lateral direction Y, the first width L1 of the isolation structure 120 is smaller than the second width L2 of the through-silicon structure 150, and the second lateral direction Y forms an included angle with the first lateral direction X.
Referring to fig. 2, fig. 2 is a flow chart illustrating a method for fabricating a semiconductor structure 100 according to a first embodiment of the present invention.
Referring to fig. 1 for reference numbers of components that make up the semiconductor structure 100, as shown in fig. 2, the method of fabrication specifically includes:
substrate providing step S101: providing a substrate 110, wherein the substrate 110 includes a plurality of circuit blocks 111 having opposite first surfaces S1And a second surface S2；
Isolation structure formation step S102: forming a plurality of isolation structures 120 penetrating through the substrate 110, the isolation structures 120 electrically isolating the plurality of circuit blocks 111;
insulating layer forming step S103: on the first surface S of the substrate 1101Forming an insulating layer 130 thereon;
test member forming step S104: a plurality of test components 140 are formed on the insulating layer 130, and each of the plurality of test components 140 is located above the longitudinal projection of a corresponding circuit block 111, wherein two of the plurality of test components 140 are used for being applied with a test voltage to make the substrate voltages in the corresponding two circuit blocks 111 have a difference.
Please refer to fig. 3, wherein fig. 3 is a schematic flowchart of a method for manufacturing the semiconductor structure 100 according to a first embodiment of the present invention, and as shown in fig. 3, the isolation structure forming step S102 may specifically include:
trench forming step S1021: forming a plurality of isolation trenches (not shown) through the substrate 110 and forming a plurality of through silicon trenches (not shown) through the substrate 110;
first deposition step S1022: filling the isolation trench with an insulating material to form an isolation structure 120, and filling the through silicon trench with the same insulating material to form an insulating inner wall (not shown);
second deposition step S1023: continuing to sequentially fill the barrier material and the conductive material in the through-silicon trench to form a through-silicon structure 150;
an etching step S1024: etching to remove the first surface S of the substrate 1101With the remaining barrier material and conductive material.
It should be noted that, since the first width of the isolation structure 120 is smaller than the second width of the through-silicon structure 150, the insulating inner walls of the isolation structure 120 and the through-silicon structure 150 are usually prepared at the same time in the first deposition step S1022, it is easily understood that if the insulating material is not sufficiently filled in the isolation trench in the first deposition step S1022, a recess appears on the surfaces of the isolation structure 120 and the substrate 110, and then, when the barrier material and the conductive material are sequentially filled in the through-silicon trench in the second deposition step S1023, the barrier material and the conductive material are filled into the recess, and since the etching step S1024 can only etch and remove the barrier material and the conductive material remaining on the surface of the substrate 110, but cannot etch and remove the barrier material and the conductive material in the recess, the metal residue exists on the isolation structure 120.
Unlike the prior art, the present invention provides a semiconductor structure 100 comprising: a substrate 110 having a plurality of circuit blocks 111, and the substrate 110 having a first surface S opposite to the first surface S1And a second surface S2A plurality of isolation structures 120 penetrating the substrate 110 and electrically isolating the plurality of circuit blocks 111, disposed on the first surface S of the substrate 1101An upper insulating layer 130, and a plurality of test components 140 disposed on the insulating layer 130, and each of the plurality of test components 140 is located above a longitudinal projection of a corresponding circuit block 111, wherein a first test component 140 of the plurality of test components 140aAnd a second test part 140bDisposed on the same insulating layer 130, and a first test part 140aAnd a first circuit block 111aFirst surface S of1Is equal to the second test member 140bAnd a second circuit block 111bFirst surface S of1A second vertical distance therebetween, and wherein the first test member 140aAnd a second test part 140bFor applying a first test voltage and a second test voltage with different voltage values to the corresponding first circuit blocks 111aAnd a second circuit block 111bHas a difference value so that it is possible to detect the first circuit block 111aAnd a second circuit block 111bWhether the leakage current therebetween is greater than a predetermined value, and whether there is a metal residue on the isolation structure 120 therebetween is detected.
Referring to fig. 4, fig. 4 is a schematic cross-sectional view of a semiconductor structure 200 according to a second embodiment of the present invention, in which components and relative positions of the components can be clearly seen.
As shown in fig. 4, the second embodiment has substantially the same structure as the first embodiment, wherein the substrate 210 in the second embodiment has the same function and arrangement position as the substrate 110 in the first embodiment; isolation structures 220 of the second embodiment are fabricated with isolation structures 120 of the first embodimentThe use and arrangement positions are the same; the insulating layer 230 in the second embodiment has the same function and arrangement position as the insulating layer 130 in the first embodiment; the test part 240 in the second embodiment (including the first test part 240 disposed on the same insulating layer 230)aAnd a second test part 240b) As with the test member 140 of the first embodiment (including the first test member 140 disposed on the same insulating layer 130)aAnd a second test part 140b) The function and the arrangement position of the same.
The difference is that in the present embodiment, the first test part 240aAnd a first circuit block 211aFirst surface S of1Is smaller than the second test part 240bAnd a second circuit block 211bFirst surface S of1A second vertical distance therebetween, and a first test member 240aAnd a second test part 240bA first test voltage and a second test voltage with equal voltage values are applied to the first circuit block 211 respectivelyaIs coupled to a potential greater than that of the second circuit block 211bPotential coupled to thereby make the first circuit block 211aAnd a second circuit block 211bHas a difference value so that it is possible to detect the first circuit block 211aAnd a second circuit block 211bThe magnitude of the leakage current therebetween is used to determine whether there is a metal residue on the isolation structure 220 therebetween.
Unlike the prior art, the present invention provides a semiconductor structure 200 comprising: a substrate 210 having a plurality of circuit blocks 211, and the substrate 210 having a first surface S opposite to the first surface S1And a second surface S2A plurality of isolation structures 220 penetrating the substrate 210 and electrically isolating the plurality of circuit blocks 211, disposed on the first surface S of the substrate 2101An insulating layer 230 on the substrate, and a plurality of test components 240 disposed on the insulating layer 230, and each of the plurality of test components 240 is located above a longitudinal projection of a corresponding circuit block 211, wherein a first test component 240 of the plurality of test components 240aAnd a second test part 240bDisposed on the same insulating layer 230, and a first test part 240aAnd a first circuit block 211aFirst surface S of1Is smaller than the second test part 240bAnd a second circuit block 211bFirst surface S of1A second vertical distance therebetween, and wherein the first test member 240aAnd a second test part 240bFor applying a first test voltage and a second test voltage with the same voltage value to the corresponding first circuit block 211aAnd a second circuit block 211bHas a difference value so that it is possible to detect the first circuit block 211aAnd a second circuit block 211bWhether the leakage current therebetween is greater than a predetermined value, and whether there is a metal residue on the isolation structure 220 therebetween is detected.
Referring to fig. 5, fig. 5 is a schematic cross-sectional view of a semiconductor structure 300 according to a third embodiment of the present invention, in which components and relative positions of the components can be clearly seen.
As shown in fig. 5, the third embodiment has substantially the same structure as the first embodiment, wherein the third embodiment has substantially the same structure as the first embodiment, and wherein the substrate 310 in the third embodiment has the same function and arrangement position as the substrate 110 in the first embodiment; the isolation structure 320 in the third embodiment has the same function and arrangement position as the isolation structure 120 in the first embodiment; the insulating layer 330 in the third embodiment has the same function and arrangement position as the insulating layer 130 in the first embodiment; the test member 340 in the third embodiment (and wherein the first test member 340aAnd a first circuit block 311aFirst surface S of1Is equal to the second test member 340bAnd a second circuit block 311bFirst surface S of1A second vertical distance therebetween) is the same as the function and arrangement position of the test member 140 in the first embodiment (and wherein the first test member 140aAnd a first circuit block 111aFirst surface S of1Is equal to the second test member 140bAnd a second circuit block 111bFirst surface S of1A second vertical distance therebetween).
The difference is that in the present embodiment, the first test part 340aIs disposed on the first insulating layer 330aUpper, and a first insulating layer 330aHaving a first relative permittivity, second test member 340bIs disposed on the second insulating layer 330bUpper, and a second insulating layer 330bHas a second relative dielectric constant, wherein the first relative dielectric constant is not equal to the second relative dielectric constant, and the first test part 340aAnd a second test part 340bA first test voltage and a second test voltage having the same voltage value are applied, respectively, so that the first test part 340aAnd a second test part 340bAre respectively disposed on the first insulating layers 330 having different relative dielectric constantsaAnd a second insulating layer 330bAbove, therefore, when the first test part 340aAnd a second test part 340bWhen a first test voltage and a second test voltage having the same voltage value are applied, the first insulating layer 330aAnd a second insulating layer 330bFor the first test part 340 respectivelyaAnd a first circuit block 311aAnd a second test part 340bAnd a second circuit block 311bThe weakening degree of the electric field is different from each other, so that the first circuit block 311 is causedaAnd a second circuit block 311bCoupled to unequal potentials, thereby making the first circuit block 311aAnd a second circuit block 311bHas a difference value so that it is possible to detect the first circuit block 311aAnd a second circuit block 311bThe magnitude of the leakage current therebetween is used to determine whether there is a metal residue on the isolation structure 320 therebetween.
Unlike the prior art, the present invention provides a semiconductor structure 300 comprising: a substrate 310 having a plurality of circuit blocks 311, and the substrate 310 having a phaseFirst surface S of the pair1And a second surface S2A plurality of isolation structures 320 penetrating the substrate 310 and electrically isolating the plurality of circuit blocks 311, disposed on the first surface S of the substrate 3101An upper insulating layer 330 including a first insulating layer 330aAnd a second insulating layer 330bAnd a plurality of test members 340 disposed on the insulating layer 330, each of the plurality of test members 340 being located above a longitudinal projection of a corresponding circuit block 311, wherein a first test member 340 of the plurality of test members 340aIs disposed on the first insulating layer 330aUpper, second test part 340bIs disposed on the second insulating layer 330bUpper, and a first insulating layer 330aHaving a different second insulating layer 330bRelative permittivity of, the first test part 340aAnd a first circuit block 311aFirst surface S of1Is equal to the second test member 340bAnd a second circuit block 311bFirst surface S of1A second vertical distance therebetween, and wherein the first test member 340aAnd a second test part 340bFor applying a first test voltage and a second test voltage with the same voltage value to the corresponding first circuit blocks 311aAnd a second circuit block 311bHas a difference value so that it is possible to detect the first circuit block 311aAnd a second circuit block 311bWhether the leakage current therebetween is greater than a predetermined value, and whether there is a metal residue on the isolation structure 320 therebetween is detected.
Referring to fig. 6, fig. 6 is a schematic cross-sectional view of a semiconductor structure 400 according to a fourth embodiment of the present invention, in which components and relative positions of the components can be clearly seen.
As shown in fig. 6, the fourth embodiment has substantially the same structure as the first embodiment, wherein the fourth embodiment has substantially the same structure as the first embodiment, and wherein the substrate 410 in the fourth embodiment has the same function and arrangement position as the substrate 110 in the first embodiment; the isolation structure 420 in the fourth embodiment has the same function and arrangement position as the isolation structure 120 in the first embodiment; the insulating layer 430 in the fourth embodiment has the same function and the same arrangement position as the insulating layer 130 in the first embodiment; the test member 440 in the fourth embodiment has the same function and arrangement position as the test member 140 in the first embodiment.
The difference is that in the present embodiment, a first connection structure 450 is further formed in the insulating layer 430aAnd a second connecting structure 450b First test part 440 to which different test voltages are appliedaAnd a second test member 440bAre respectively connected with the first connecting structure 450aAnd a second connecting structure 450bIs electrically connected to the first circuit block 411aAnd a second circuit block 311bThus, the first circuit block 411 will be enabledaAnd a second circuit block 411bSo that it is possible to detect the first circuit block 411 by detectingaAnd a second circuit block 411bThe magnitude of the leakage current therebetween is used to determine whether there is a metal residue on the isolation structure 420 therebetween.
In distinction from the prior art, the present invention provides a semiconductor structure 400 comprising: a substrate 410 having a plurality of circuit blocks 411, and the substrate 410 having a first surface S opposite to the first surface S1And a second surface S2A plurality of isolation structures 420 penetrating the substrate 410 and electrically isolating the plurality of circuit blocks 411 are disposed on the first surface S of the substrate 4101An insulating layer 430 on the substrate, and a plurality of test components 440 disposed on the insulating layer 430, each of the plurality of test components 440 being located above a longitudinal projection of a corresponding circuit block 411, wherein a first test component 440 of the plurality of test components 440 isaAnd a second test member 440bAre respectively connected with the first connecting structure 450aAnd a second connecting structure 450bIs electrically connected to the first circuit block 411aAnd a second circuit block 411bAnd a first test member 440aAnd a second test member 440bFirst test voltages of different magnitudes are applied to the test terminals respectivelyThe second test voltage makes the corresponding first circuit block 411aAnd a second circuit block 411bHas a difference value so that it is possible to detect the first circuit block 411aAnd a second circuit block 411bWhether the leakage current therebetween is greater than a predetermined value, and whether there is a metal residue on the isolation structure 420 therebetween is detected.
It should be understood that in another variation of the present invention, the two test components for performing the test may have different applied test voltages, different vertical distances from the first surface of the corresponding circuit block, and different relative dielectric constants of the media between the two corresponding circuit blocks (i.e., different test voltages, different vertical distances, and different relative dielectric constants) or different relative dielectric constants (i.e., different test voltages, different vertical distances, and different relative dielectric constants), so long as the substrate voltages in the corresponding circuit blocks are different, and whether there is any metal residue on the isolation structure therebetween can be determined.
In addition to the above embodiments, the present invention may have other embodiments. All technical solutions formed by using equivalents or equivalent substitutions fall within the protection scope of the claims of the present invention.
In summary, although the preferred embodiments of the present invention have been described above, the above-described preferred embodiments are not intended to limit the present invention, and those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, therefore, the scope of the present invention shall be determined by the appended claims.
Claims (9)
1. A semiconductor structure, comprising:
the circuit comprises a substrate, a first circuit block, a second circuit block and a third circuit block, wherein the substrate comprises a plurality of circuit blocks and is provided with a first surface and a second surface which are opposite;
at least one isolation structure penetrating the substrate to electrically isolate the plurality of circuit blocks;
an insulating layer disposed on the first surface of the substrate;
the plurality of test components are arranged on the insulating layer, and each test component is positioned above the longitudinal projection of one corresponding circuit block;
wherein two of the plurality of test parts are used for being applied with test voltages so that the substrate voltages in the two corresponding circuit blocks have a difference value.
2. The semiconductor structure of claim 1, wherein the isolation structure has a first length along a first lateral direction and the test component has a second length along the first lateral direction, wherein the first length is not greater than the second length.
3. The semiconductor structure of claim 1, wherein the plurality of test features comprises a first test feature and a second test feature disposed on the same insulating layer, wherein:
the first test component has a first vertical distance from the first surface of the corresponding first circuit block and is applied with a first test voltage;
the second test component has a second vertical distance from the first surface of the corresponding second circuit block and is applied with a second test voltage;
and wherein the first vertical distance is equal to the second vertical distance, and the first test voltage is not equal to the second test voltage.
4. The semiconductor structure of claim 1, wherein the plurality of test features comprises a first test feature and a second test feature disposed on the same insulating layer, wherein:
the first test component has a first vertical distance from the first surface of the corresponding first circuit block and is applied with a first test voltage;
the second test component has a second vertical distance from the first surface of the corresponding second circuit block and is applied with a second test voltage;
and wherein the first vertical distance is not equal to the second vertical distance, and the first test voltage is equal to the second test voltage.
5. The semiconductor structure of claim 1, wherein the plurality of test components comprises a first test component and a second test component, wherein:
the first test component is arranged on the first insulating layer, has a first vertical distance with the first surface of the corresponding first circuit block, is applied with a first test voltage, and has a first relative dielectric constant;
the second test component is arranged on the second insulating layer, has a second vertical distance with the first surface of the corresponding second circuit block, is applied with a second test voltage, and has a second relative dielectric constant;
and wherein the first vertical distance is equal to the second vertical distance, the first test voltage is equal to the second test voltage, and the first relative permittivity is not equal to the second relative permittivity.
6. The semiconductor structure of claim 1, wherein a first connection structure and a second connection structure are further formed in the insulating layer, the plurality of test components include a first test component and a second test component, the first connection structure electrically connects the first test component with a corresponding first circuit block, and the second connection structure electrically connects the second test component with a corresponding second circuit block, wherein a first test voltage is applied to the first test component, a second test voltage is applied to the second test component, and the first test voltage and the second test voltage are not equal.
7. The semiconductor structure of claim 1, wherein two of the test components to which the test voltage is applied are located above a longitudinal projection of two sides of the same isolation structure.
8. A method for fabricating a semiconductor structure, the method comprising:
providing a substrate, wherein the substrate comprises a plurality of circuit blocks and is provided with a first surface and a second surface which are opposite;
forming at least one isolation structure through the substrate, the isolation structure electrically isolating the plurality of circuit blocks;
forming an insulating layer on the first surface of the substrate;
forming a plurality of test components on the insulating layer, wherein each test component is positioned above the longitudinal projection of one corresponding circuit block;
wherein two of the plurality of test parts are used for being applied with test voltages so that the substrate voltages in the two corresponding circuit blocks have a difference value.
9. The method according to claim 8, wherein the step of forming at least one isolation structure through the substrate comprises:
forming at least one isolation trench penetrating through the substrate and forming a plurality of through-silicon trenches penetrating through the substrate;
filling an insulating material in the isolation trench to form the isolation structure, and filling the same insulating material in the through silicon trench to form an insulating inner wall;
continuously and sequentially filling a barrier material and a conductive material in the through silicon trench to form a through silicon structure;
and etching to remove the residual barrier material and the conductive material on the first surface of the substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110087124.8A CN112768366B (en) | 2021-01-22 | 2021-01-22 | Semiconductor structure and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110087124.8A CN112768366B (en) | 2021-01-22 | 2021-01-22 | Semiconductor structure and preparation method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN112768366A true CN112768366A (en) | 2021-05-07 |
| CN112768366B CN112768366B (en) | 2024-02-23 |
Family
ID=75702823
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110087124.8A Active CN112768366B (en) | 2021-01-22 | 2021-01-22 | Semiconductor structure and preparation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112768366B (en) |
Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100763704B1 (en) * | 2006-08-28 | 2007-10-04 | 동부일렉트로닉스 주식회사 | Test pattern group for leakage current monitoring and fabrication method thereof |
| US20090309097A1 (en) * | 2008-06-13 | 2009-12-17 | Force Mos Technology Co. Ltd. | Testing device on water for monitoring vertical mosfet on-resistance |
| US20110073858A1 (en) * | 2009-09-25 | 2011-03-31 | International Business Machines Corporation | Test Structure for Determination of TSV Depth |
| CN103137511A (en) * | 2011-11-25 | 2013-06-05 | 中芯国际集成电路制造(上海)有限公司 | Silicon through-hole test structure and corresponding test method |
| KR20140030608A (en) * | 2012-09-03 | 2014-03-12 | 에스케이하이닉스 주식회사 | Tsv structure of semiconductor memory device and testing method thereof |
| CN203800036U (en) * | 2014-03-28 | 2014-08-27 | 中芯国际集成电路制造(北京)有限公司 | Source and drain leakage current testing structure |
| US8933345B1 (en) * | 2010-05-13 | 2015-01-13 | Xilinx, Inc. | Method and apparatus for monitoring through-silicon vias |
| CN104752406A (en) * | 2013-12-27 | 2015-07-01 | 中芯国际集成电路制造(上海)有限公司 | Test structure for through silicon via |
| US9966318B1 (en) * | 2017-01-31 | 2018-05-08 | Stmicroelectronics S.R.L. | System for electrical testing of through silicon vias (TSVs) |
| CN208045490U (en) * | 2017-02-28 | 2018-11-02 | 意法半导体(鲁塞)公司 | Integrated circuit |
| CN109952643A (en) * | 2016-10-10 | 2019-06-28 | 三维单晶公司 | 3D semiconductor devices and structure |
-
2021
- 2021-01-22 CN CN202110087124.8A patent/CN112768366B/en active Active
Patent Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100763704B1 (en) * | 2006-08-28 | 2007-10-04 | 동부일렉트로닉스 주식회사 | Test pattern group for leakage current monitoring and fabrication method thereof |
| US20090309097A1 (en) * | 2008-06-13 | 2009-12-17 | Force Mos Technology Co. Ltd. | Testing device on water for monitoring vertical mosfet on-resistance |
| US20110073858A1 (en) * | 2009-09-25 | 2011-03-31 | International Business Machines Corporation | Test Structure for Determination of TSV Depth |
| US8933345B1 (en) * | 2010-05-13 | 2015-01-13 | Xilinx, Inc. | Method and apparatus for monitoring through-silicon vias |
| CN103137511A (en) * | 2011-11-25 | 2013-06-05 | 中芯国际集成电路制造(上海)有限公司 | Silicon through-hole test structure and corresponding test method |
| KR20140030608A (en) * | 2012-09-03 | 2014-03-12 | 에스케이하이닉스 주식회사 | Tsv structure of semiconductor memory device and testing method thereof |
| CN104752406A (en) * | 2013-12-27 | 2015-07-01 | 中芯国际集成电路制造(上海)有限公司 | Test structure for through silicon via |
| CN203800036U (en) * | 2014-03-28 | 2014-08-27 | 中芯国际集成电路制造(北京)有限公司 | Source and drain leakage current testing structure |
| CN109952643A (en) * | 2016-10-10 | 2019-06-28 | 三维单晶公司 | 3D semiconductor devices and structure |
| US9966318B1 (en) * | 2017-01-31 | 2018-05-08 | Stmicroelectronics S.R.L. | System for electrical testing of through silicon vias (TSVs) |
| CN208045490U (en) * | 2017-02-28 | 2018-11-02 | 意法半导体(鲁塞)公司 | Integrated circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| CN112768366B (en) | 2024-02-23 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US20110074459A1 (en) | Structure and method for semiconductor testing | |
| WO1999016107A2 (en) | Methods for determining on-chip interconnect process parameters | |
| CN103187403B (en) | Semiconductor failure analysis structure and formation method, the method for detection out-of-service time | |
| CN107978537B (en) | Test structure and test unit | |
| JP2718380B2 (en) | Semiconductor device electrical characteristics inspection pattern and inspection method | |
| US8344510B2 (en) | Semiconductor device with void detection monitor | |
| CN112768366B (en) | Semiconductor structure and preparation method thereof | |
| US8102053B2 (en) | Displacement detection pattern for detecting displacement between wiring and via plug, displacement detection method, and semiconductor device | |
| CN104752405A (en) | Semiconductor device test structure and forming method thereof | |
| JP2007123755A (en) | Void detector, manufacturing method therefor, and evaluation method | |
| US12031931B2 (en) | Inspection structure and inspection method | |
| US7510944B1 (en) | Method of forming a MIM capacitor | |
| US10103068B2 (en) | Detecting a void between a via and a wiring line | |
| CN113990845B (en) | Detection structure, preparation method thereof and detection method of cavity in membrane layer | |
| US20210109051A1 (en) | Inspection Structure and Inspection Method | |
| US8278765B2 (en) | Test-key for checking interconnect | |
| JP2012109402A (en) | Semiconductor device, method of manufacturing semiconductor device, and method of inspecting semiconductor device | |
| KR20090069714A (en) | Time dependent dielectric breakdown test pattern and method thereof | |
| CN115954343B (en) | Gate oxide layer test structure | |
| CN113363241B (en) | Test structure and test method | |
| US9524916B2 (en) | Structures and methods for determining TDDB reliability at reduced spacings using the structures | |
| US8916393B2 (en) | Method for estimating the diffusion length of metallic species within a three-dimensional integrated structure, and corresponding three-dimensional integrated structure | |
| CN109642840B (en) | Pressure sensor module | |
| CN117524909A (en) | Semiconductor test structure and forming method thereof | |
| CN117727738A (en) | Semiconductor test structure and semiconductor test method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |