CN112768351A - Pattern forming method - Google Patents
Pattern forming method Download PDFInfo
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- CN112768351A CN112768351A CN201911075391.2A CN201911075391A CN112768351A CN 112768351 A CN112768351 A CN 112768351A CN 201911075391 A CN201911075391 A CN 201911075391A CN 112768351 A CN112768351 A CN 112768351A
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- material layer
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- 238000000034 method Methods 0.000 title claims abstract description 47
- 239000000463 material Substances 0.000 claims abstract description 166
- 239000000758 substrate Substances 0.000 claims abstract description 51
- 238000005530 etching Methods 0.000 claims abstract description 31
- 238000000059 patterning Methods 0.000 claims abstract description 12
- 239000010410 layer Substances 0.000 claims description 213
- 239000011241 protective layer Substances 0.000 claims description 20
- 229920002120 photoresistant polymer Polymers 0.000 claims description 13
- 238000000151 deposition Methods 0.000 claims description 9
- 238000005498 polishing Methods 0.000 claims description 4
- 239000000126 substance Substances 0.000 claims description 4
- 238000004519 manufacturing process Methods 0.000 abstract description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 14
- 229910052581 Si3N4 Inorganic materials 0.000 description 10
- 229910052681 coesite Inorganic materials 0.000 description 10
- 229910052906 cristobalite Inorganic materials 0.000 description 10
- 239000000377 silicon dioxide Substances 0.000 description 10
- 229910052682 stishovite Inorganic materials 0.000 description 10
- 229910052905 tridymite Inorganic materials 0.000 description 10
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 7
- 229910052799 carbon Inorganic materials 0.000 description 7
- 239000007789 gas Substances 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 3
- JJWKPURADFRFRB-UHFFFAOYSA-N carbonyl sulfide Chemical compound O=C=S JJWKPURADFRFRB-UHFFFAOYSA-N 0.000 description 2
- 238000005034 decoration Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 description 1
- 238000004380 ashing Methods 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3081—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their composition, e.g. multilayer masks, materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Drying Of Semiconductors (AREA)
Abstract
The invention provides a pattern forming method, which comprises the following steps: providing a substrate; forming a pattern transfer layer on the substrate, wherein the pattern transfer layer comprises a first material layer and a second material layer, and the first material layer and the second material layer are alternately arranged and extend along the direction parallel to the substrate; forming a first pattern window on the pattern transfer layer, wherein the first pattern window at least exposes a part of the first material layer or at least exposes a part of the second material layer; etching the first material layer or the second material layer along the first pattern window to form a second pattern window in the pattern transfer layer; and etching the substrate along the second pattern window, and patterning the substrate. The invention has the advantages of realizing the purpose of reducing the key size, simplifying the process for preparing the key size and obtaining smaller key size.
Description
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a pattern forming method.
Background
With the continuous development of integrated circuit technology, the feature size of semiconductor integrated circuit devices is continuously shrinking. For example, as a semiconductor integrated circuit device widely used in a computer system, a Dynamic Random Access Memory (DRAM) has smaller critical dimensions, greater manufacturing difficulty, more complex manufacturing process, and higher cost.
Therefore, how to simplify the process of fabricating the critical dimension and obtain the small critical dimension becomes a technical problem to be solved urgently.
Disclosure of Invention
The invention provides a pattern forming method, which can simplify the process of preparing a critical dimension and obtain a small critical dimension.
In order to solve the above problems, the present invention provides a pattern forming method, comprising the steps of: providing a substrate; forming a pattern transfer layer on the substrate, wherein the pattern transfer layer comprises a first material layer and a second material layer, and the first material layer and the second material layer are alternately arranged and extend along the direction parallel to the substrate; forming a first pattern window on the pattern transfer layer, wherein the first pattern window at least exposes a part of the first material layer or at least exposes a part of the second material layer; etching the first material layer or the second material layer along the first pattern window to form a second pattern window in the pattern transfer layer; and etching the substrate along the second pattern window, patterning the substrate, and transferring the pattern of the pattern transfer layer to the substrate.
Further, forming the pattern transfer layer on the substrate includes: forming the first material layer on the substrate; patterning the first material layer, and forming first gaps arranged at intervals in the first material layer, wherein the first gaps expose the substrate; and depositing the second material layer in the first gap to form the pattern transfer layer.
Further, depositing the second material layer in the first void, forming the pattern transfer layer, includes: depositing a second material on the first material layer, wherein the second material covers the upper surface of the first material layer and fills the first gap to form the second material layer in the first gap; removing the second material on the upper surface of the first material layer to form the pattern transfer layer with the first material layer being flush with the top surface of the second material layer.
Further, the method for removing the second material layer on the upper surface of the first material layer includes chemical mechanical polishing or etching.
Further, forming a first pattern window on the pattern transfer layer includes: forming a photoresist layer on the pattern transfer layer; and patterning the light resistance layer, and forming the first pattern windows which are arranged at intervals in the light resistance layer.
Further, the first graphic window simultaneously exposes a portion of the first material layer and a portion of the second material layer.
Further, the first material layer and the second material layer exposed by the first graphic window are symmetrically distributed along the center line of the first graphic window.
Further, the etching selection ratio of the first material layer to the second material layer is larger than 6.
The invention has the advantages that the appearance of the formed pattern is controlled by the etching selection ratio of the first material layer and the second material layer, thereby achieving the purpose of reducing the critical dimension. In addition, in the conventional multi-pattern technology process, for example, SADP (self-aligned multi-pattern technology), it is usually required to deposit a sidewall deposition layer on the sidewall of the pattern window, and the pattern size is shrunk through the sidewall deposition layer, which is not required to be implemented in the present invention.
Drawings
FIG. 1 is a schematic step diagram of one embodiment of a pattern forming method of the present invention;
FIGS. 2A to 2G are process flow diagrams of an embodiment of a pattern forming method according to the present invention;
FIGS. 3A to 3D are process flow charts for forming a pattern transfer layer in the pattern forming method of the present invention;
fig. 4A and 4B are process flow diagrams of forming a first pattern window on the pattern transfer layer in the pattern forming method of the present invention.
Detailed Description
The following describes in detail a specific embodiment of a pattern forming method according to the present invention with reference to the drawings.
Fig. 1 is a schematic step diagram of one embodiment of the pattern forming method of the present invention, and fig. 2A to 2G are process flow diagrams of one embodiment of the pattern forming method of the present invention.
Referring to fig. 1, the method for forming a pattern includes the following steps: step S10, providing a substrate; step S11, forming a pattern transfer layer on the substrate, wherein the pattern transfer layer comprises a first material layer and a second material layer, and the first material layer and the second material layer are alternately arranged and extend along the direction parallel to the substrate; step S12, forming a first pattern window on the pattern transfer layer, wherein the first pattern window exposes at least a portion of the first material layer or exposes at least a portion of the second material layer; step S13, etching the first material layer or the second material layer along the first pattern window, and forming a second pattern window in the pattern transfer layer; step S14, etching the substrate along the second pattern window, patterning the substrate, and transferring the pattern of the pattern transfer layer to the substrate; in step S15, the first material layer and the second material layer are removed.
Referring to step S10 and fig. 2A, a substrate 20 is provided. The substrate 20 may be a conventional semiconductor substrate or a substrate having a device structure that needs to be patterned. In this embodiment, a protective layer 21 is provided on the substrate 20. The material of the protective layer 21 may be SiO2、Si3N4A Carbon, or a combination thereof.
Referring to step S11 and fig. 2B, a pattern transfer layer 22 is formed on the substrate 20. In the present embodiment, the pattern transfer layer 22 is formed on the protective layer 21. The pattern transfer layer 22 includes a first material layer 22A and a second material layer 22B, and the first material layer 22A and the second material layer 22B are alternately arranged and extend in a direction parallel to the substrate 20. Specifically, as shown in fig. 2B, the first material layers 22A and the second material layers 22B are alternately arranged and extend in the X direction.
The first material layer 22A and the second material layer 22B have a large etching selection ratio, so that both can not be etched at the same time in a subsequent process. That is, in the subsequent process, when the first material layer 22A and the second material layer 22B are etched by using the same etching gas, only the first material layer 22A or the second material layer 22B can be etched, but not both of them can be etched at the same time.
For example, if the first material layer 22A is Carbon, the second material layer 22B may be SiO2Or Si3N4(ii) a Alternatively, if the first material layer 22A is SiO2Or Si3N4Then the second material layer 22B can be Carbon, the Carbon and the SiO2Or Si3N4Has an etch selectivity greater than 10. As another example, if the first material layer 22A is SiO2Then the second material layer 22B can be Si3N4(ii) a Alternatively, if the first material layer 22A is Si3N4Then the second material layer 22B can be SiO2. Wherein, SiO2With Si3N4Has an etch selectivity of greater than 6.
The pattern transfer layer 22 may be formed on the protective layer 21 by the following method. Specifically, the method comprises the following steps:
referring to fig. 3A, the first material layer 22A is formed on the substrate 20. In the present embodiment, the first material layer 22A is formed on the protective layer 21. The material of the first material layer 22A may be SiO2、Si3N4A Carbon, or a combination thereof. In the present embodiment, the first material layer 22A covers the entire surface of the protective layer 21.
Referring to fig. 3B, the first material layer 22A is patterned to form first voids 220 arranged at intervals in the first material layer 22A, and the first voids 220 expose the substrate 20. In the present embodiment, the first gap 220 exposes the upper surface of the protection layer 21.
In this step, the first material layer 22A may be patterned by photolithography and etching to form the first voids 220. Specifically, a patterned photoresist layer may be formed on the first material layer 22A by photolithography, and the first material layer 22A is etched by using the patterned photoresist layer as a mask to form the first voids 220.
Depositing the second material layer 22B in the first voids 220 forms the pattern transfer layer 22. Specifically, referring to fig. 3C, a second material 221 is deposited on the first material layer 22A, and the second material 221 covers the upper surface of the first material layer 22A and fills the first gap 220 to form the second material layer 22B in the first gap 220; referring to fig. 3D, the second material 221 on the upper surface of the first material layer 22A is removed to form the pattern transfer layer 22 with the first material layer 22A flush with the top surface of the second material layer 22B. The material of the second material layer 22B can be SiO2、Si3N4A Carbon, or a combination thereof.
The method for removing the second material 221 from the upper surface of the first material layer 20A includes chemical mechanical polishing or etching. The advantage of using the chemical mechanical polishing method is that the upper surface of the second material layer 22B and the upper surface of the first material layer 22A can be planarized while removing the second material 221, so that the first material layer 22A is flush with the top surface of the second material layer 22B; the etching method has the advantage of high removal speed.
While the above description is directed to one method of forming the pattern transfer layer 22, it is understood that other methods of forming the pattern transfer layer 22 may be used without departing from the principles of the present invention.
Referring to step S12 and fig. 2C, a first pattern window 230 is formed on the pattern transfer layer 22, wherein the first pattern window 230 exposes at least a portion of the first material layer 22A or at least a portion of the second material layer 22B.
Wherein the first pattern window 230 may be formed on the pattern transfer layer 22 using the following method. The method comprises the following steps: referring to fig. 4A, a photoresist layer 23 is formed on the pattern transfer layer 22. Referring to fig. 4B, the photoresist layer 23 is patterned, and the first pattern windows 230 are formed in the photoresist layer 23 at intervals. Wherein the first pattern window 230 may be formed on the photoresist layer 23 by using an exposure and photolithography process.
In this embodiment, the first pattern window 230 exposes a portion of the first material layer 22A and a portion of the second material layer 22B at the same time, that is, both the upper surface of the first material layer 22A and the upper surface of the second material layer 22B are exposed in the same first pattern window 230. In other embodiments of the present invention, the first pattern window 230 may expose only a portion of the first material layer 22A, or only a portion of the second material layer 22B.
Preferably, in the present embodiment, the first material layer 22A and the second material layer 22B exposed by the first pattern window 230 are symmetrically distributed along the center line O of the first pattern window 230, and in step S13, the second pattern window 240 with the same size can be formed in the pattern transfer layer 22 by etching the first material layer 22A or etching the second material layer 22B.
Referring to step S13 and fig. 2D, the first material layer 22A or the second material layer 22B is etched along the first pattern window 230 to form a second pattern window 240 in the pattern transfer layer 22.
In this step, the first material layer 22A or the second material layer 22B is removed by etching using the photoresist layer 23 as a mask. Since the etching selectivity of the first material layer 22A or the second material layer 22B is relatively different, only one of the layers can be removed when etching is performed using the same etching gas. For example, when the first material layer 22A is SiO2Or Si3N4When the second material layer 22B is Carbon, in the present embodiment, O is used2COS (carbonyl sulfide), or SO2CO, etc. as an etching gas, the second material layer 22B is removed, the etching gas cannot etch the first material layer 22A, or the etching proportion of the first material layer 22A is very small and can be ignored, then after the step S13 is completedRemoving the second material layer 22B not blocked by the photoresist layer 23 to form the second pattern window 240; in other embodiments of the invention, CF is used4/CHF3/O2and/Ar and the like are used as etching gases to remove the first material layer 22A, the etching gases cannot etch the second material layer 22B, or the etching proportion of the second material layer 22B is very small and can be ignored, after the step S13 is completed, the first material layer 22A which is not blocked by the photoresist layer 23 is removed to form the second pattern window 240.
Since the first pattern window 230 exposes a portion of the first material layer 22A or the second material layer 22B, a second pattern window 240 formed by etching the first material layer 22A or the second material layer 22B along the first pattern window 230 has a size smaller than that of the first pattern window 230.
Referring to step S14, fig. 2E and fig. 2F, the substrate 20 is etched along the second pattern window 240, the substrate 20 is patterned, and the pattern of the pattern transfer layer 22 is transferred to the substrate 20.
In this embodiment, since the protective layer 21 is disposed on the substrate 20, in this step, referring to fig. 2E, the pattern of the pattern transfer layer 22 is first transferred to the protective layer 21, that is, the protective layer 21 is etched along the second pattern window 240, and the protective layer 21 is patterned; referring to fig. 2F, the patterned protective layer 21 is used as a mask to pattern the substrate 20, so as to transfer the pattern of the pattern transfer layer 22 to the substrate 20.
The size of the second pattern window 240 is smaller than that of the first pattern window 230, so that the critical dimension formed in the subsequent process is relatively reduced.
In step S15 and fig. 2G, the first material layer 22A, the second material layer 22B and the photoresist layer 23 are removed. In this step, the first material layer 22A and the second material layer 22B may be removed by mechanical stripping or laser stripping, and the photoresist layer 23 may be removed by stripping or ashing. This step may be performed after the step of patterning the substrate 20, and may also be performed after the step of patterning the protective layer 21. After this step is performed, the pattern of the pattern transfer layer 22 is transferred onto the substrate 20 or the protective layer 21.
In the subsequent process, the protective layer 21 may be removed to form a patterned substrate, and the protective layer 21 may also be remained to protect the upper surface of the substrate 20.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.
Claims (10)
1. A pattern forming method is characterized by comprising the following steps:
providing a substrate;
forming a pattern transfer layer on the substrate, wherein the pattern transfer layer comprises a first material layer and a second material layer, and the first material layer and the second material layer are alternately arranged and extend along the direction parallel to the substrate;
forming a first pattern window on the pattern transfer layer, wherein the first pattern window at least exposes a part of the first material layer or at least exposes a part of the second material layer;
etching the first material layer or the second material layer along the first pattern window to form a second pattern window in the pattern transfer layer;
and etching the substrate along the second pattern window, and patterning the substrate.
2. The pattern forming method according to claim 1, wherein forming the pattern transfer layer on the substrate comprises:
forming the first material layer on the substrate;
patterning the first material layer, and forming first gaps arranged at intervals in the first material layer, wherein the first gaps expose the substrate;
and depositing the second material layer in the first gap to form the pattern transfer layer.
3. The pattern forming method according to claim 2, wherein depositing the second material layer in the first voids to form the pattern transfer layer comprises:
depositing a second material on the first material layer, wherein the second material covers the upper surface of the first material layer and fills the first gap to form the second material layer in the first gap;
removing the second material on the upper surface of the first material layer to form the pattern transfer layer with the first material layer being flush with the top surface of the second material layer.
4. The pattern forming method according to claim 3, wherein a method for removing the second material layer from the upper surface of the first material layer comprises chemical mechanical polishing or etching.
5. The pattern forming method according to claim 1, wherein forming a first pattern window on the pattern transfer layer comprises:
forming a photoresist layer on the pattern transfer layer;
and patterning the light resistance layer, and forming the first pattern windows which are arranged at intervals in the light resistance layer.
6. The pattern forming method according to claim 1, wherein the first pattern window simultaneously exposes a part of the first material layer and a part of the second material layer.
7. The pattern forming method according to claim 6, wherein the first material layer and the second material layer exposed by the first pattern window are symmetrically distributed along a center line of the first pattern window.
8. The pattern forming method according to claim 1, further comprising forming a protective layer on the substrate, the protective layer being located between the substrate and the pattern transfer layer.
9. The pattern forming method according to claim 8, wherein transferring the pattern of the pattern transfer layer to the substrate comprises:
transferring the pattern of the pattern transfer layer to the protective layer;
patterning the protective layer;
and patterning the substrate by taking the patterned protective layer as a mask.
10. The pattern forming method according to any one of claims 1 to 9, wherein an etching selection ratio of the first material layer to the second material layer is greater than 6.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911075391.2A CN112768351B (en) | 2019-11-06 | 2019-11-06 | Pattern forming method |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911075391.2A CN112768351B (en) | 2019-11-06 | 2019-11-06 | Pattern forming method |
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| CN112768351A true CN112768351A (en) | 2021-05-07 |
| CN112768351B CN112768351B (en) | 2022-06-10 |
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| KR20010058352A (en) * | 1999-12-27 | 2001-07-05 | 박종섭 | Resist pattern forming method with precise width than mask size |
| US20030230234A1 (en) * | 2002-06-14 | 2003-12-18 | Dong-Seok Nam | Method of forming fine patterns of semiconductor device |
| US20090155733A1 (en) * | 2007-12-12 | 2009-06-18 | Nanya Technology Corporation | Method of forming iso space pattern |
| US20120132616A1 (en) * | 2010-11-30 | 2012-05-31 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | Method for making a pattern from sidewall image transfer |
| US20120329268A1 (en) * | 2011-03-28 | 2012-12-27 | Ibm Corporation | Method of making a semiconductor device |
| CN103594337A (en) * | 2012-08-14 | 2014-02-19 | 中芯国际集成电路制造(上海)有限公司 | A dual patterning method |
| CN106252229A (en) * | 2015-06-12 | 2016-12-21 | 中国科学院微电子研究所 | A kind of manufacture method of semiconductor device |
| CN106373880A (en) * | 2015-07-22 | 2017-02-01 | 联华电子股份有限公司 | Semiconductor element and formation method thereof |
| CN108546912A (en) * | 2018-05-03 | 2018-09-18 | 中芯集成电路（宁波）有限公司 | Mask plate and preparation method thereof |
| CN108624841A (en) * | 2018-05-03 | 2018-10-09 | 中芯集成电路（宁波）有限公司 | Mask plate and preparation method thereof |
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2019
- 2019-11-06 CN CN201911075391.2A patent/CN112768351B/en active Active
Patent Citations (10)
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|---|---|---|---|---|
| KR20010058352A (en) * | 1999-12-27 | 2001-07-05 | 박종섭 | Resist pattern forming method with precise width than mask size |
| US20030230234A1 (en) * | 2002-06-14 | 2003-12-18 | Dong-Seok Nam | Method of forming fine patterns of semiconductor device |
| US20090155733A1 (en) * | 2007-12-12 | 2009-06-18 | Nanya Technology Corporation | Method of forming iso space pattern |
| US20120132616A1 (en) * | 2010-11-30 | 2012-05-31 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | Method for making a pattern from sidewall image transfer |
| US20120329268A1 (en) * | 2011-03-28 | 2012-12-27 | Ibm Corporation | Method of making a semiconductor device |
| CN103594337A (en) * | 2012-08-14 | 2014-02-19 | 中芯国际集成电路制造(上海)有限公司 | A dual patterning method |
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| CN106373880A (en) * | 2015-07-22 | 2017-02-01 | 联华电子股份有限公司 | Semiconductor element and formation method thereof |
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| CN108624841A (en) * | 2018-05-03 | 2018-10-09 | 中芯集成电路（宁波）有限公司 | Mask plate and preparation method thereof |
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| CN112768351B (en) | 2022-06-10 |
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