CN112764669A

CN112764669A - Accelerator for a storage controller

Info

Publication number: CN112764669A
Application number: CN201911060807.3A
Authority: CN
Inventors: 陈博
Original assignee: Beijing Starblaze Technology Co ltd
Current assignee: Beijing Starblaze Technology Co ltd
Priority date: 2019-11-01
Filing date: 2019-11-01
Publication date: 2021-05-07
Anticipated expiration: 2039-11-01
Also published as: CN112764669B

Abstract

The application provides a hardware accelerator, which comprises a command manager, a read-write processor and a buffer memory, wherein the read-write processor acquires a data index according to first information, and instructs a data transfer unit to acquire read/write data corresponding to a first command, wherein the first information is acquired by a CPU group from the first command, the first information comprises the data index or information used for acquiring the data index, and if the first command is a read command, the read/write data comprises first data acquired by the data transfer unit from a Dynamic Random Access Memory (DRAM), and the buffer memory buffers the data index. Partial functions of the CPU are realized through the command manager, the read-write processor and the buffer memory respectively, CPU resources occupied in the read-write operation process are reduced, and therefore the read-write operation is accelerated.

Description

Accelerator for a storage controller

Technical Field

The present application relates to storage technology, and in particular, to a hardware accelerator for a control component of a storage device.

Background

FIG. 1A illustrates a block diagram of a solid-state storage device. The solid-state storage device 100 is coupled to a host for providing storage capability to the host. The host and the solid-state storage device 100 may be coupled by various methods, including, but not limited to, connecting the host and the solid-state storage device 100 by, for example, SATA (Serial Advanced Technology Attachment), SCSI (Small Computer System Interface), SAS (Serial Attached SCSI), IDE (Integrated Drive Electronics), USB (Universal Serial Bus), PCIE (Peripheral Component Interconnect Express, PCIE, high-speed Peripheral Component Interconnect), NVMe (NVM Express, high-speed nonvolatile storage), ethernet, fiber channel, wireless communication network, etc. The host may be an information processing device, such as a personal computer, tablet, server, portable computer, network switch, router, cellular telephone, personal digital assistant, etc., capable of communicating with the storage device in the manner described above. The Memory device 100 includes an interface 120, a control unit 140, one or more NVM chips 130, and a DRAM (Dynamic Random Access Memory) 110.

NAND flash Memory, phase change Memory, FeRAM (Ferroelectric RAM), MRAM (magnetoresistive Memory), RRAM (Resistive Random Access Memory), XPoint Memory, and the like are common NVM.

The interface 120 may be adapted to exchange data with a host by means such as SATA, IDE, USB, PCIE, NVMe, SAS, ethernet, fibre channel, etc.

The control component 140 is used to control data transfer between the interface 120, the NVM chip 130, and the DRAM 110, as well as for memory management, host logical address to flash physical address mapping, erase leveling, bad block management, and the like. The control part 140 may be implemented in various ways of software, hardware, firmware or a combination thereof, for example, the control part 140 may be in the form of an FPGA (Field-programmable gate array), an ASIC (Application-Specific Integrated Circuit), or a combination thereof. The control component 140 may also include a processor or controller in which software is executed to manipulate the hardware of the control component 140 to process IO (Input/Output) commands. The control component 140 may also be coupled to the DRAM 110 and may access data of the DRAM 110. FTL tables and/or cached IO command data may be stored in the DRAM.

Control component 140 includes a flash interface controller (or referred to as a media interface controller, flash channel controller) that is coupled to NVM chip 130 and issues commands to NVM chip 130 in a manner that conforms to the interface protocol of NVM chip 130 to operate NVM chip 130 and receive command execution results output from NVM chip 130. Known NVM chip interface protocols include "Toggle", "ONFI", etc.

Chinese patent applications CN201610009789.6 and CN201510053428.1 provide a method and apparatus for executing micro instructions for a flash memory interface controller, chinese patent application CN 201610861793.5 provides a method and apparatus for scheduling micro instruction sequences, chinese patent application CN 201611213754.0 provides an IO command processing method and a solid-state storage device, and chinese patent application CN 201611213755.5 provides a large-capacity NVM interface controller, the entire contents of which are incorporated herein.

In the chinese patent application with publication number CN107783917A, a command for operating an NVM chip is generated by executing a micro instruction to generate a control signal on a control pin of the NVM chip, so that a single flash memory controller is compatible with NVM chips of different manufacturers and different scales. Which is incorporated herein in its entirety.

In the storage device, mapping information from logical addresses to physical addresses is maintained by using a Flash Translation Layer (FTL). The logical addresses constitute the storage space of the solid-state storage device as perceived by upper-level software, such as an operating system. The physical address is an address for accessing a physical memory location of the solid-state memory device. Address mapping may also be implemented using an intermediate address modality in the related art. E.g. mapping the logical address to an intermediate address, which in turn is further mapped to a physical address. In these cases, the read/write commands received by the storage device indicate logical addresses.

A table structure storing mapping information from logical addresses to physical addresses is called an FTL table. FTL tables are important metadata in solid state storage devices. Typically, entries of the FTL table record address mapping relationships in units of data pages in the storage device.

The FTL of some memory devices is provided by a host to which the memory device is coupled, the FTL table is stored by a memory of the host, and the FTL is provided by a CPU of the host executing software. Still other storage management devices disposed between hosts and storage devices provide FTLs. In these cases, the read/write commands received by the storage device indicate physical addresses.

Commands provided by the host to the storage device may access a logical address space corresponding to one or more entries of the FTL table. And the control component may morph commands received from the interface 120 (e.g., split the commands according to the logical address space size corresponding to the FTL entry) and process the morphed commands. For clarity, herein, a read/write command received by a storage device accessing a single FTL entry is described as an example.

NVM chips such as NAND flash memory are unreliable storage media where there are erroneous bits of stored data. To identify and correct the error bits, ECC (error correction code) encoding is performed on the data written to the NVM chip, and the encoded check data is written to the NVM chip along with the data. When data is read out from the NVM chip, ECC decoding is performed on the read data (along with the check data) to get the correct data. When there are many error bits in the data, the ECC decoding cannot obtain correct data. Optionally, the control unit of the storage device may also take some other data correction measures (e.g., Read-Retry, RAID data reconstruction, etc.) to attempt to recover the correct data. There are still some cases where correct data cannot be obtained even after various or all data verification measures are taken, which is called UECC (uncorrectable error correction code) occurrence.

Disclosure of Invention

According to a first aspect of the present application, there is provided a first hardware accelerator according to the first aspect of the present application, comprising: the device comprises a command manager, a read-write processor and a buffer memory, wherein the command manager judges whether a read command or a write command acquired from a host conforms to a protocol between the host and a storage device, and sends a first command conforming to the protocol to a CPU group, the first command is the read command or the write command, and the CPU group comprises at least one CPU; the read-write processor acquires a data index according to first information, and instructs a data moving unit to acquire read/write data corresponding to the first command, wherein the first information is acquired by the CPU group from the first command, the first information comprises the data index or information used for acquiring the data index, and if the first command is a read command, the read/write data comprises first data acquired by the data moving unit from a Dynamic Random Access Memory (DRAM); the buffer memory buffers the data index.

The first hardware accelerator according to the first aspect of the present application provides the second hardware accelerator according to the first aspect of the present application, and if the first command is a write command, the read/write data includes second data acquired by the data moving unit from the host according to the data index.

According to the first or second hardware accelerator of the first aspect of the present application, there is provided the third hardware accelerator of the first aspect of the present application, where the read-write processor receives tag information sent by a media interface controller, where the tag information is used to characterize that the media interface controller has completed reading the first data from the NVM to the DRAM, and the tag information includes identification information corresponding to the first command; and the read-write processor instructs the data moving unit to acquire the first data from the DRAM according to the identification information and send the first data to a host according to the data index.

The third hardware accelerator according to the first aspect of the present application provides the fourth hardware accelerator according to the first aspect of the present application, and the tag information is fed back to the read/write processor by the media interface controller after the first data is stored in the DRAM.

According to a third hardware accelerator of the first aspect of the present application, there is provided a fifth hardware accelerator of the first aspect of the present application, where if the first command is a read command, the read/write processor records a data length of the first data, where the data length of the first data is obtained by the read/write processor according to the first information; responding to the label information, and recording the length of data which is sent to the host by the first command according to the label information by the read-write processor; and the read-write processor responds to the length of the data to be read by the first command and equals to the length of the data which is sent to the host for the first command, and sends state information for representing the completion of the processing of the read command to the host.

According to the third hardware accelerator of the first aspect of the present application, there is provided the sixth hardware accelerator of the first aspect of the present application, wherein if the first command is a read command, the read-write processor records a data length to be read by the first command; the read-write processor responds to the received label information and records the length of the data read to the DRAM by the first command according to the label information; and the read-write processor responds that the length of the data to be read by the first command is equal to the length of the data read to the DRAM for the first command, instructs the data moving unit to acquire the data read for the first command from the DRAM according to the identification information, and sends state information for representing the completion of the processing of the read command to the host.

The second hardware accelerator according to the first aspect of the present application provides the seventh hardware accelerator according to the first aspect of the present application, and if the first command is a write command, the read/write processor instructs the data moving unit to obtain the second data from the host address corresponding to the data index after the buffer memory obtains the data index, and sends the second data to a media interface controller.

According to a fifth hardware accelerator of the first aspect of the present application, there is provided the eighth hardware accelerator of the first aspect of the present application, wherein the read/write processor allocates a memory space of the DRAM for the second data, and indicates the allocated memory space to the media interface controller to control the NVM to store the second data.

According to one of the second to eighth hardware accelerators of the first aspect of the present application, there is provided the ninth hardware accelerator of the first aspect of the present application, wherein the hardware accelerator further includes at least two cache units, and the at least two cache units cache the first data or the second data in a ping-pong manner in a process when the data moving unit acquires the second data from the host or sends the first data to the host.

According to one of the second to ninth hardware accelerators of the first aspect of the present application, there is provided the tenth hardware accelerator of the first aspect of the present application, wherein the read/write processor sends status information for indicating completion of processing of a write command to the host in response to the second data transmission to the media interface controller.

According to one of the first to tenth hardware accelerators of the first aspect of the present application, there is provided the eleventh hardware accelerator of the first aspect of the present application, further comprising a security unit that decrypts the first data in the cache unit or encrypts the second data in the cache unit.

According to one of the first to eleventh hardware accelerators of the first aspect of the present application, there is provided the twelfth hardware accelerator of the first aspect of the present application, before determining whether a read command or a write command acquired from a host complies with the protocol, the command manager acquires a second command sent by the host, the second command being a read command, a write command, or a command other than a read command and a write command; and judging whether the second command is a read command or a write command.

According to one of the first to twelfth hardware accelerators of the first aspect of the present application, there is provided the thirteenth hardware accelerator of the first aspect of the present application, wherein if it is determined that the second command is not a read command or a write command, the command manager sends, to the host, response information indicating a command error.

According to a second aspect of the present application, there is provided a first control component according to the second aspect of the present application, comprising: an NVMe controller, a CPU bank, a media interface controller, and a hardware accelerator, the hardware accelerator coupled with the NVMe controller, the CPU bank, and the media interface controller, the CPU bank coupled with the media interface controller; the hardware accelerator acquires a read command or a write command from the NVMe controller, and sends a first command which accords with a protocol between a host and a storage device to the CPU group, wherein the first command is a read command or a write command; the CPU group acquires first information from the first command and indicates the first information to the hardware accelerator, wherein the first information comprises a data index or information for acquiring the data index, and the data index is used for acquiring first data or second data; and the media interface controller reads the first data from an NVM chip or writes the second data into the NVM chip according to the indication of the hardware accelerator, wherein the indication of the hardware accelerator is made by the hardware accelerator according to the first information.

According to a second aspect of the present application, there is provided a method for controlling a hardware accelerator, comprising receiving a read command or a write command from a host, and sending a command received from the host or sending indication information to the hardware accelerator, wherein the indication information is used for indicating the hardware accelerator to grab the read command or the write command from the NVMe controller.

According to the second aspect of the present application, there is provided the third control means according to the second aspect of the present application, wherein when the first command is a read command, the media interface controller reads the first data from the NVM chip according to an instruction of the hardware accelerator, and stores the first data in a DRAM coupled to the control means.

According to the second aspect of the present application, there is provided the fourth control unit according to the second aspect of the present application, wherein when the first command is a write command, the media interface controller reads the second data from the DRAM coupled to the control unit according to an instruction of the hardware accelerator, and writes the second data to the NVM chip.

According to a third control component of the second aspect of the present application, there is provided a fifth control component of the second aspect of the present application, wherein the hardware accelerator instructs the NVMe controller to move the first data from the DRAM to the host according to the tag information fed back by the media interface controller.

According to a fourth control component of the second aspect of the present application, there is provided a sixth control component of the second aspect of the present application, the hardware accelerator further instructing the NVMe controller to carry the second data from the host to the DRAM according to the first information.

According to a sixth control component of the second aspect of the present application, there is provided the seventh control component of the second aspect of the present application, wherein the hardware accelerator allocates a memory space in the DRAM for the second data and indicates the memory space to the NVMe controller and the media interface controller.

According to one of the first to seventh control components of the second aspect of the present application, there is provided the eighth control component of the second aspect of the present application, wherein the CPU group obtains a logical address where the first data is located after receiving the read command, and accesses the flash translation layer according to the logical address to obtain a physical address corresponding to the logical address; and the CPU group indicates the physical address to the medium interface controller, so that the medium interface controller reads the first data from the NVM chip according to the physical address.

According to one of the first to eighth controlling means of the second aspect of the present application, there is provided the ninth controlling means of the second aspect of the present application, the medium interface controller receiving second information supplied from the CPU group, the second information indicating that the first data is read out from a physical address of the NVM chip; and

the media interface controller provides the tag information to the hardware accelerator in response to the first data read from the NVM chip having been stored to the DRAM.

According to a ninth controlling means of the second aspect of the present application, there is provided the tenth controlling means of the second aspect of the present application, wherein the second information further carries an indication of a storage space in the DRAM for storing the first data.

According to one of the first to eighth control means of the second aspect of the present application, there is provided the eleventh control means of the second aspect of the present application, wherein the media interface controller transmits, to the CPU group, second tag information for indicating that reception of the second data by the media interface controller is completed, the second tag information including identification information corresponding to a write command; the media interface controller receives third information provided by the CPU group, wherein the third information indicates that the second data is written into a physical address of the NVM chip; and the media interface controller providing fourth information to the CPU group, the fourth information indicating that the second data has been written to the NVM chip.

According to an eleventh control section of the second aspect of the present application, there is provided the twelfth control section of the second aspect of the present application, wherein if the first command is a write command, the CPU group records a data length to be written by the first command; the CPU group responds to the received fourth information provided by the media interface controller, and records the length of the data written into the NVM chip by the first command according to the fourth information; the CPU learns that the first command has been processed in response to the first command having a length of data to be written equal to a length of data written to the NVM chip for the first command.

According to one of the first to twelfth control means of the second aspect of the present application, there is provided the thirteenth control means of the second aspect of the present application, the hardware accelerator decrypts the first data or encrypts the second data when transmitting the first data or the second data.

According to one of the first to thirteenth control means of the second aspect of the present application, there is provided the fourteenth control means of the second aspect of the present application, wherein the hardware accelerator records a data length of the first data, the data length of the first data being acquired by the hardware accelerator according to the first information; responding to the label information, the hardware accelerator records the length of data sent to the host by the first command according to the label information; the hardware accelerator sends status information to the host characterizing completion of processing of a read command in response to a length of data to be read by the first command being equal to a length of data that has been sent to the host for the first command.

According to one of the first to fourteenth control means of the second aspect of the present application, there is provided the fifteenth control means of the second aspect of the present application, wherein if the first command is a read command, the hardware accelerator records a data length to be read by the first command; the hardware accelerator records, in response to receiving the tag information, a length of data that the first command has stored to the DRAM according to the tag information.

According to a fifteenth control section of the second aspect of the present application, there is provided the sixteenth control section of the second aspect of the present application, wherein the hardware accelerator instructs the NVMe controller to acquire the data read for the first command from the DRAM according to the identification information, in response to a length of the data to be read for the first command being equal to a length of the data already stored to the DRAM for the first command.

According to a fifteenth control means of the second aspect of the present application, there is provided the seventeenth control means of the second aspect of the present application, wherein the hardware accelerator instructs the NVMe controller to acquire the data read for the first command from the DRAM in accordance with the identification information in response to part or all of the data to be read for the first command having been stored to the DRAM.

According to a sixteenth or seventeenth control unit of the second aspect of the present application, there is provided the eighteenth control unit of the second aspect of the present application, wherein the NVMe controller is instructed to send to the host status information characterizing completion of processing of the read command, in response to the first command that the data to be read has been sent to the host in its entirety.

According to one of the first to eighteenth control means of the second aspect of the present application, there is provided nineteenth control means according to the second aspect of the present application, wherein the hardware accelerator is one of the first to thirteenth hardware accelerators according to the first aspect of the present application.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments described in the present application, and other drawings can be obtained by those skilled in the art according to the drawings.

FIG. 1A is a block diagram of a prior art memory device;

FIG. 1B is a schematic diagram of a control unit in the prior art;

FIG. 2 is a schematic structural diagram of a control component provided in an embodiment of the present application;

FIG. 3 is a schematic diagram of a hardware accelerator according to an embodiment of the present disclosure;

fig. 4 is a schematic structural diagram of a control component provided in an embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application are clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some, but not all, embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

The phrases "in various embodiments," "in some embodiments," and the like are used repeatedly. Such phrases are not generally referring to the same embodiment; however, such phrases may refer to the same embodiment. The terms "comprising," "having," and "including" are synonymous, unless the context dictates otherwise. The phrase "A and/or B" means (A), (B) or (A and B). The phrases "A/B" and "A or B" mean (A) or (B). The phrase "at least one of A and B" means (A), (B) or (A and B).

Fig. 1B illustrates one possible structure of the control unit 140 in the prior art. As shown in fig. 1B, the control part 140 includes an NVMe controller 141, a CPU group 142, and a media interface controller 143. The NVMe controller 141 is coupled to the CPU group 142 and the interface 120 in fig. 1A, respectively. For example, the NVMe controller 141 receives a host send first read command from the interface 120. The NVMe controller 141 is coupled with the CPU group 142. For example, the NVMe controller 141 will receive the first write command, convert to a second write command in a data format suitable for CPU processing, and send the second write command to the CPU group 142. CPU bank 142 is coupled to media interface controller 143. For example, the CPU group 142 receives the second write command, and operates the media interface controller 143 to write data to the flash memory chip according to the second write command.

With continued reference to fig. 1A and 1B, after the host sends a read command or a write command to the storage device 100, the CPU group 142 accesses the FTL to obtain an appropriate physical address for the flash memory chip, and operates the media interface controller 144 to perform a read operation or a write operation, but the CPU group 142 needs more operations to operate the media interface controller 143, and increases the load of the CPU group 142, which affects the processing speed.

A control component 200 in an embodiment of the present application is shown in fig. 2. Referring to fig. 2, the control component 200 in the first embodiment of the present application includes an NVMe controller 210, a hardware accelerator 220, a CPU group 230, and a media interface controller 240. As shown in fig. 2, the NVMe controller 210 is coupled to the hardware accelerator 220, the hardware accelerator 220 is coupled to the CPU group 230 and the media interface controller 240, respectively, and the CPU group 230 is coupled to the media interface controller 240. The CPU group 230 includes one or more CPU cores.

The following takes as an example that the control section 200 processes a read command.

After the NVMe controller 210 receives the read command, the NVMe controller 210 sends the read command to the hardware accelerator 220 or sends a hint message to the hardware accelerator 220 for prompting the command to be processed in the NVMe controller 210. The hardware accelerator 220 receives the hint information and actively retrieves the read command from the NVMe controller 210.

Optionally, after retrieving the read command, the hardware accelerator 220 determines whether the read command complies with the protocol between the host and the storage device. For example, after the hardware accelerator 220 acquires the read command, it determines whether the data format of the read command conforms to the NVMe protocol. For another example, whether the data format of the read command conforms to the specification of the AHCI protocol is determined.

When the read command does not conform to the protocol specifications, the hardware accelerator 220 generates an error response and feeds back the error response to the host through the NVMe controller 210 to notify the host that the read command is in error.

When the read command complies with the protocol specifications, the hardware accelerator 220 sends the read command to the CPU group 230. After receiving the read command, the CPU group 230 accesses the FTL according to the valid information carried in the read command to obtain the physical address corresponding to the logical address of the read command, and the CPU group 230 further instructs the hardware accelerator 220 to record the host address according to the valid information or obtains the host address from the host according to the second index information pointing to the host address. In this embodiment, the valid information includes at least two of a logical address of data to be read, a host address for storing the read data, first index information pointing to the logical address, and second index information pointing to the host address.

In yet another embodiment, when the read command complies with the protocol specifications, hardware accelerator 220 will extract valid information from the read command, which carries the data needed by CPU group 230 to process the read command. Optionally, the length of the valid information is smaller than the read command. For example, the length of the read command acquired by the hardware accelerator 220 is 80 bits, and the length of the valid information is 64 bits. The effective information includes: at least two of a logical address of data to be read, a host address for storing the read data, first index information pointing to the logical address, and second index information pointing to the host address. For example, when the length of data to be read is short or logical addresses are consecutive, the valid information includes the logical address of the data to be read and a host address for storing the read data. For another example, when the data length to be read is long or is stored discretely, the valid information includes first index information pointing to the logical address and second index information pointing to the host address.

After the CPU group 230 receives the valid information, the FTL is accessed according to the valid information to obtain the physical address corresponding to the logical address of the read command, and the CPU group 230 further instructs the hardware accelerator 220 to record the host address according to the valid information or obtains the host address from the host according to the second index information pointing to the host address.

Upon receiving the host address, hardware accelerator 220 stores the host address to DRAM (not shown in fig. 2) via the bus. Alternatively, after receiving the second index information, the hardware accelerator 220 obtains the host address from the host through an interface coupled to the hardware accelerator 220, and sends the host address to the DRAM through the bus.

After the conversion of the logical address into the physical address is completed, the CPU group 230 transmits the physical address corresponding to the logical address of the read command to the media interface controller 240. The media interface controller 240 reads data stored in the physical address from the flash memory chip according to the physical address, and stores the data in the DRAM. After storing all the data to be read in the DRAM, the media interface controller 240 feeds back read data completion information to the hardware accelerator 220 for notifying the hardware accelerator 220 that the data can be transmitted to the host. The read data completion information includes command identifiers, and the command identifiers are used for distinguishing data corresponding to different commands.

Alternatively, after the conversion of the logical address into the physical address is completed, the CPU group 230 sends to the media interface controller 240 second information instructing the media interface controller 240 to read the first data from the physical address of the NVM, so that the media interface controller 240 starts reading the first data from the NVM and stores the read first data in the DRAM. For example, the size of the first data is 20KB, and the media interface controller 240 needs to perform 5 reads each time it reads 4KB, and stores the first data into the DRAM in 5 divisions.

Optionally, the CPU cluster 230 also allocates a buffer location from the DRAM before sending the second message to the media interface controller 240 and indicates the allocated buffer location in the second message. The media interface controller thus stores the data read from the NVM chip in response to the second message to the buffer location indicated by the second message. The media interface controller will also provide read data completion information to the hardware accelerator.

Still alternatively, the CPU group 230 is not responsible for the allocation of the buffer units, but the media interface controller allocates the buffer units from the DRAM and stores the data read out from the NVM chip in response to the second message to the allocated buffer units.

Still optionally, the hardware accelerator further comprises a cache unit manager. The media interface controller transmits the data read from the NVM chip in response to the second message to the buffer unit manager without a process of allocating buffer units in advance. The buffer manager manages the buffer and carries data read from the NVM chip in response to the second message received from the media interface controller with the available buffer, and the buffer manager also provides the read data completion information to the hardware accelerator. The read data completion information indicates an index of a buffer unit carrying read data.

In response to receiving the read data completion information and the host address of the read command has been stored in the DRAM, the hardware accelerator 220 sends a command identification to the NVMe controller 210 to instruct the NVMe controller 210 to carry data in the DRAM corresponding to the command identification into the storage space corresponding to the host address. For example, after the first data is completely stored in the DRAM, the media interface controller 240 sends tag information to the hardware accelerator 220, where the tag information includes identification information corresponding to the read command, so that the hardware accelerator 220 instructs the NVMe controller 210 to acquire the first data from the DRAM according to the identification information and move the first data to the host.

In some embodiments, the second information carries information indicative of a storage space in the DRAM where the first data is stored, so that the media interface controller 240 can directly store the first data read from the NVM in the storage space.

Optionally, the hardware accelerator 220 also buffers data generated by AES (Advanced encryption standard) processing between the media interface controller 240 to the host. For example, if the storage device is configured to perform AES processing when reading data, hardware accelerator 220 provides storage space to buffer data generated during AES processing.

The manner in which the control section 200 processes the write command is described below.

After the NVMe controller 210 receives the write command, the NVMe controller 210 sends the write command to the hardware accelerator 220 or sends a hint message to the hardware accelerator 220 for prompting a command to be processed in the NVMe controller 210. The hardware accelerator 220, upon receiving the hint information, actively grabs the write command from the NVMe controller 210.

Optionally, after retrieving the write command, the hardware accelerator 220 determines whether the write command complies with the specification of the protocol between the host and the storage device. For example, after the hardware accelerator 220 acquires the write command, it determines whether the data format of the write command conforms to the NVMe protocol. Protocols between the host and the storage device include NVMe protocol, AHCI protocol, and the like.

When the write command does not conform to the protocol specifications, the hardware accelerator 220 generates an error response and feeds back the error response to the host through the NVMe controller 210 to notify the host that the write command is in error.

When the write command complies with the specifications of the protocol, hardware accelerator 220 sends the write command to the CPU group.

After receiving the write command, the CPU group 230 indicates, according to valid information carried in the write command, a host address of data to be written by the hardware accelerator 220 or third index information pointing to the host address, and a command identifier. The effective information in this embodiment includes: the host address of the data to be written or the third index information pointing to the host address, and the command identification.

In another embodiment, when the write command complies with the protocol specifications, hardware accelerator 220 will extract valid information from the write command, which carries the data needed by CPU group 230 to process the write command. Optionally, the length of the valid information is smaller than the write command. For example, the length of the write command acquired by the hardware retarder 220 is 64 bits, and the length of the valid information is 32 bits. The effective information includes: the host address of the data to be written or the third index information pointing to the host address, and the command identification. For example, if the length of data to be written is long or the number of host addresses is too large, the valid command includes the third index information and the command identification. The command identifier in this embodiment corresponds to the data to be written corresponding to the write command, for example, 3 write commands are simultaneously processed in the NVMe controller 210, and each write command corresponds to one command identifier, so that the data to be written corresponding to the 3 write commands can be distinguished.

After the CPU group 230 receives the valid information, it indicates the host address storing the data to be written or the third index information pointing to the host address, and the command identification to the hardware accelerator 220.

After receiving the host address and the command identifier, the hardware accelerator 220 obtains corresponding data from the host address through the NVMe controller 210, and carries the data to the DRAM. Or after receiving the third index information, the hardware accelerator 220 acquires the host address from the host through an interface coupled to the hardware accelerator 220, acquires corresponding data according to the host address through the NVMe controller 210, and transports the data to the DRAM. After all the data corresponding to the command identifier is transferred to the DRAM, the hardware accelerator 220 feeds back completion information indicating completion of the write command to the host. After the host receives the completion information, the processing of the write command to the host is complete. The hardware accelerator 220 also feeds back completion information characterizing the completion of the write command to the CPU group 230.

Optionally, before the CPU bank 230 sends the host address to the hardware accelerator 220, it also allocates a cache location from the DRAM and provides the allocated cache location to the hardware accelerator 220 along with the host address. So that the hardware accelerator 220 stores the data retrieved from the host address to the allocated cache location.

Still alternatively, the CPU group 230 is not responsible for allocation of cache locations, but the hardware accelerator 220 allocates cache locations from the DRAM and stores data retrieved from the host address to the allocated cache locations.

Still optionally, the hardware accelerator further comprises a cache unit manager. The hardware accelerator 220 transmits the data retrieved from the host address to the cache unit manager without a process of allocating cache units in advance. The cache unit manager manages the cache units and carries the data retrieved from the host addresses received from the hardware accelerator 220 with the available cache units. The cache management unit stores the data acquired from the host address into the cache unit and then provides the data transmission completion information to the hardware accelerator. The data transfer completion information indicates an index of a cache unit carrying data acquired from the host address.

After receiving the valid information, the CPU group 230 further allocates a physical address to the data to be written in the write command, and accesses the FTL to record a correspondence relationship between the logical address indicated by the valid information and the allocated physical address. After receiving the information indicating that the data transmission is completed, which is sent by the hardware accelerator 220, the CPU group 230 sends the location in the DRAM and the allocated physical address of the data to be written by the write command to the media interface controller 240.

After receiving the physical address and the location of the data in the DRAM, the media interface controller 240 reads the data to be written from the DRAM and writes the data to be written into the memory space corresponding to the physical address in the flash memory chip.

Optionally, after receiving the host address and the command identifier, the hardware accelerator 220 reads data corresponding to the command identifier from the host address through the NVMe controller 210, and sends the data to the media interface controller 240, and the media interface controller 240 carries the data to the DRAM. Alternatively, after receiving the third index information, the hardware accelerator 220 obtains the host address from the host through an interface coupled to the hardware accelerator 220, reads data corresponding to the command identifier from the host address through the NVMe controller 210, sends the data to the media interface controller 240, and the media interface controller 240 transfers the data to the DRAM. After sending all the data corresponding to the command identifier to the media interface controller 240, the hardware accelerator 220 feeds back completion information representing the completion of the write command to the host. After the hardware accelerator 220 carries the data to the media interface controller 240, it sends an indication to the media interface controller 240 to start a write operation and notifies the CPU group 230 that the data transfer is complete.

The media interface controller 240, after receiving the data to be written, allocates a physical address to the data to be written and transmits the allocated physical address to the CPU group. After receiving the physical address, the CPU group accesses the FTL to record the correspondence between the logical address and the physical address of the write command.

After acquiring the physical address and the position of the data in the DRAM, the media interface controller 240 reads the data to be written from the DRAM and writes the data to be written into the storage space corresponding to the physical address in the flash memory chip.

Optionally, the hardware accelerator 220 caches data generated by the cryptographic processes between the media interface controller 240 to the host. The encryption process includes AES, TCGOPAL, and the like. For example, if the storage device is configured to perform AES processing when writing data, hardware accelerator 220 provides storage space to buffer data generated during AES processing.

Fig. 3 shows a possible structure of a hardware accelerator according to the second embodiment of the present application. The control unit in the present application may also adopt the hardware accelerator in the second embodiment of the present application, in addition to the hardware accelerator described in the above embodiments. As shown in fig. 3, a second embodiment of the present application provides a hardware accelerator 300, including: a command processor 310, a read-write processor 320, and a buffer memory 330. The command processor 310 is coupled to the read/write processor 320, and the read/write processor 320 is coupled to the buffer memory 330.

The command manager 310 determines whether the read command or the write command acquired from the host conforms to a protocol between the host and the storage device, and sends a first command conforming to the protocol to the CPU group 430, where the first command is a read command or a write command. One possible configuration of the control unit 400 is given in fig. 4. The hardware accelerator 300 will be described below by taking the structure of the control unit 400 in fig. 4 as an example. The CPU group 430 includes at least one CPU, for example, the CPU group 430 in fig. 4 includes 2 CPUs, i.e., a CPU core 1 and a CPU core 2. The CPU group 430 may further include more than two CPUs, and the number of the CPUs may be selected according to actual requirements, which is not limited herein.

When the first command is a read command, the CPU group 430 acquires first information including a data index or information for acquiring the data index from the read command. For example, the data index is a Physical Region Page (PRP) list, a Scatter Gather List (SGL), a host address of the data in the host, an address of the data in the DRAM, and the like. The information for acquiring the data index includes a pointer pointing to the data index, for example, the first information includes a pointer pointing to the data index, and the read/write processor 320 accesses the storage space where the data index is located through the pointer, thereby acquiring the data index. The read/write processor 320 also stores the data index into the buffer memory 330.

The CPU group 430 further acquires a logical address to be accessed by the read command from the first message, and accesses the FTL according to the logical address to acquire a physical address corresponding to the logical address to be accessed by the read command. Optionally, the CPU group 430 is further divided into a plurality of logical addresses according to the logical address range to be accessed by the read command, and obtains a plurality of corresponding physical addresses from the FTL.

The CPU group 430 also assigns a command identification to the read command to distinguish between multiple commands being processed simultaneously by the storage device. Multiple physical addresses obtained from the same read command are associated with the same command identification.

The CPU complex 430 sends one or more physical addresses associated with the same read command to the media interface controller 440 to instruct the media interface controller 440 to read data from the NVM chip according to the received physical addresses. The physical address is sent to the media interface controller 440 and the process of the media interface controller 440 reading data from the NVM chip is processed concurrently with the operation of the read/write processor 320 obtaining the data index.

Alternatively, CPU complex 430 may also allocate a cache location from DRAM50 and indicate the allocated cache location to media interface controller 440 before sending the physical address to media interface controller 440. So that the media interface controller 440 stores data read from the NVM chip in response to the physical address to the allocated buffer location. The media interface controller 440 will also provide read data completion information to the read write manager 320 instead of to the CPU group 430. The read data completion information indicates an index of a buffer unit carrying read data.

Still alternatively, the CPU group 430 is not responsible for allocation of the buffer units, but the media interface controller 440 allocates the buffer units from the DRAM50 and stores the data read out from the NVM chip to the allocated buffer units.

Still optionally, hardware accelerator 300 further comprises a cache unit manager (not shown). The media interface controller 440 sends data read from the NVM chip in response to one or more physical addresses to the buffer unit manager without a process of allocating buffer units in advance. The buffer unit manager manages the buffer units and carries the data read from the NVM chip received from the media interface controller 440 with the available buffer units, and also provides the read data completion information to the read-write manager 320 instead of to the CPU group 430.

The read/write manager 320 identifies whether the data to be read by the read command is all read from the NVM chip and stored to the DRAM50 according to the received read data complete message. By way of example, the read-write manager 320 records the length of data to be read by the read command and identifies the length of data that the read command has been read from the NVM chip and moved to the DRAM50 based on the received one or more read data completion messages, thereby determining that the data to be read by the read command has been completely read from the NVM chip and stored to the DRAM50 by identifying the length of data that the read command has been read from the NVM chip and moved to the DRAM 50.

In one embodiment, in response to a read command that the data to be read has all been read from the NVM chip and stored to the DRAM50, and the data index of the read command has been deposited into the buffer memory 330, the read/write processor 320 moves the data to be read by the read command (also referred to as "read data") to the host address indicated by the data index.

The read-write processor 320 instructs the data transfer unit to acquire read data corresponding to the read command. In this embodiment, the data moving unit is in the NVMe controller 410, so that the read-write processor 320 instructs the NVMe controller 410 to acquire the read data, for example, the data moving unit is a DMA engine (direct memory access) in the NVMe controller 410. The data transfer unit may be embedded in the NVMe controller 410, or may be a data transfer unit independent of the NVMe controller 410, which is not limited herein. Since the first command is a read command, the read data is data acquired from the DRAM by the data transfer unit according to the index of the cache unit carrying the read data indicated by the read data completion information, and the acquired data is transferred to the host index indicated by the data index.

Read-write manager 320 also identifies whether the read data has been completely migrated to the host. By way of example, the read/write manager 320 records the length of data to be read by the read command, and also counts the length of data sent to the host by the data transfer unit. It is thus determined that the data to be read by the read command has been completely transferred to the host by recognizing the data length to be read by the read command and the data length that has been read from the DRAM50 and transferred to the host. In turn, the read-write manager 320 indicates to the host through the NVMe controller 410 that the read command processing is complete.

Alternatively, the media interface controller 440 sends a read data complete message to the CPU group 430 so that the CPU group 430 recognizes whether the data to be read by the read command is all read from the NVM chip and stored to the DRAM 50. In turn, the CPU group 430 instructs the read-write manager 320 to move the read data to the host.

In another embodiment, the read/write processor 320 receives tag information sent by the media interface controller 440, where the tag information is used to represent that the reading of data from the NVM by the media interface controller to the DRAM is completed, and the tag information includes identification information corresponding to the first command; the read/write processor 320 instructs the data transfer unit to obtain the first data from the DRAM according to the identification information and to send the first data to the host according to the data index.

By way of example, the amount of first data may be greater than the amount of data read by the media interface controller 440 in one read from the flash memory chip to the DRAM. To characterize that a portion of the first data has been transferred into the DRAM, the media interface controller 440 feeds back tag information to the read/write processor 320. For example, the first data length is 10K, and the media interface controller 440 needs 3 times to complete the operation of transferring the first data into the DRAM every time 4K is transferred. After each 4K transfer to DRAM, the media interface controller 440 sends a tag message to the read/write processor 320 to inform the read/write processor 320 of the length of the data that has been currently transferred. Thus, the read/write processor 320 knows that the first data has been read from the flash memory chip into the DRAM after receiving the tag information, and the read/write processor 320 continues to move the first data from the DRAM to the host. For example, the read/write processor 320 indicates the identification information and the host address to the data transfer unit and indicates the data transfer unit to start data transfer, so that the data transfer unit obtains the first data from all data stored in the DRAM according to the identification information, accesses the host through the host address, and stores the first data in the storage space corresponding to the host address.

Optionally, the read-write processor 320 records a data length of the first data, where the data length of the first data is obtained by the read-write processor 320 according to the first information; the read-write processor 320 also records the length of the data that has been sent to the host according to the first command; the read-write processor 320 transmits status information for indicating completion of processing of the read command to the host in response to the length of data to be read by the first command being equal to the length of data that has been transmitted to the host for the first command.

In this embodiment, in the process of sending the first data to the host, the read/write processor 320 records the length of the data already sent to the host in the first data in real time, and compares the length with the data length of the first data (i.e., the total length of the first data) to determine whether the first data is sent completely, so as to determine the sending state of the first data simply and quickly. For example, if the data length of the first data is 4KB and the recorded transmitted data length is 3KB at time T1, the data transmission is not completed at time T1, and if the recorded transmitted data length is changed to 4KB at time T2, it is determined that the data transmission is completed at time T2, and status information indicating that the read command processing is completed is transmitted to the host.

When the first command is a write command, the CPU group 430 acquires first information including a data index or information for acquiring the data index from the write command. For example, the data indexes a host address in the host. The CPU group 430 sends the first information to the read/write processor 320, and the read/write processor 320 stores the data index into the buffer memory 330.

The read-write processor 320 further instructs the data transfer unit to obtain write data corresponding to the first command according to the data index, where the write data is second data obtained by the data transfer unit from the host according to the data index. The second data in this embodiment is data to be written into the flash memory chip.

Alternatively, the CPU group 430 also allocates a buffer unit from the DRAM50 before transmitting the host address to the read/write processor 320, and provides the allocated buffer unit to the read/write processor 320 along with the data index. So that the read-write processor 320 stores the data obtained from the host address to the allocated cache unit.

Still alternatively, the CPU group 430 is not responsible for allocation of cache units, but the read-write processor 320 allocates cache units from the DRAM50 and stores data acquired from the host address to the allocated cache units. The read-write processor 320 replaces the CPU group 430 to allocate the cache units, so that the occupied CPU resources are reduced, and the processing speed is increased.

Still optionally, hardware accelerator 300 further comprises a cache unit manager. The read/write processor 320 transmits the data acquired from the host address to the buffer unit manager without a process of allocating a buffer unit in advance. The buffer manager manages the buffer units and uses the available buffer units to carry the data received from the read/write processor 320 and obtained from the host address. After the cache management unit stores the data obtained from the host address in the cache unit, the cache management unit also provides the data transmission completion information to the read/write processor 320. The data transfer completion information indicates an index of a cache unit carrying data acquired from the host address.

Still alternatively, neither the CPU group 430 nor the read/write processor 320 is responsible for allocation of cache locations, but rather the media interface controller 440 allocates cache locations from the DRAM 50. The read/write processor 320 transmits the data acquired from the host address to the media interface controller 440 without a process of allocating a buffer unit in advance. The media interface controller 440 stores the data obtained from the host address in the buffer unit, and then provides the data transfer completion information to the read/write processor 320.

The read-write manager 320 also identifies whether complete write data has been obtained from the host. By way of example, the read-write manager 320 records the length of data to be written to the storage device by the write command, and also counts the length of data moved from the host by the data move unit. Thus, the data to be written by the write command is determined to be completely moved from the host to the storage device by identifying the length of the data to be written by the write command and the length of the data already moved from the host. In turn, the read-write manager 320 indicates to the host through the NVMe controller 410 that the write command processing is complete. Read-write manager 320 also provides information to CPU group 430 characterizing the completion of the data transfer of the write command.

For the host, the data to be written by the write command is transferred to the storage device, and the write command is completed. The host is freed up the host resources allocated for the write command.

The CPU group 430 also assigns a command identification to the write command to distinguish between multiple commands being processed simultaneously by the storage device. One or more physical addresses assigned to the same write command are associated with the same command identification. The command identification is also associated with the data index obtained from the write command and also with information characterizing the completion of the data transfer of the write command.

After receiving the write command, the CPU group 430 further allocates a physical address to the data to be written in the write command, and accesses the FTL to record a correspondence between the logical address indicated by the valid information and the allocated physical address. After receiving the information indicating that the data transmission is completed, which is sent by the read/write manager 320, the CPU group 230 sends the location of the data to be written in the DRAM50 and the allocated physical address of the write command to the media interface controller 440.

Optionally, the CPU group 430 allocates a physical address process to the write command, and processes the write command concurrently with the operation of the read/write processor 320 to obtain the data index.

The media interface controller 440 retrieves data from the DRAM50 according to the location of the received data in the DRAM50 and writes the retrieved data to the NVM chip according to the physical address. The media interface controller 440 sends a tag message to the read write processor 320 in response to data being written to the NVM chip, the tag message being information characterizing completion of data transfer of the write command.

The read/write manager 320 identifies whether the data to be written by the write command is completely written to the NVM chip according to the received tag message. By way of example, the read-write manager 320 records the length of data to be written by the write command and identifies the length of data that has been written by the write command to the NVM chip according to the received one or more tag messages, so as to determine that the data to be written by the write command has been completely written to the NVM chip by identifying the length of data to be read by the write command and the length of data that has been written to the NVM chip 0.

In response to a write command that the data to be read has all been written to the NVM chip, the read/write processor 320 releases the resources (e.g., command identification) allocated for the write command.

Optionally, media interface controller 440 sends a tag message to CPU group 430 so that CPU group 430 identifies whether the data to be written by the write command is all written to the NVM chip. Then, the CPU group 430 releases the resource allocated for the write command.

In some embodiments, the hardware accelerator 320 also includes at least two cache units. And in the process of acquiring the write data from the host or transmitting the read data to the host by the data moving unit, at least two buffer units buffer the write data or the read data in a ping-pong mode. In the application, the hardware accelerator can be provided with one or more than one cache units, and when at least two cache units are arranged, the data writing or reading can be cached in a ping-pong manner, so that the data transmission speed can be effectively increased.

Optionally, during the process of transmitting data between the host and the storage device, there is a need for data encryption, so that the hardware accelerator in this embodiment further includes a security unit, where the security unit decrypts the first data in the cache unit or encrypts the second data. For example, the security unit performs AES decryption processing on the first data.

Optionally, before determining whether the read command or the write command acquired from the host conforms to the protocol, the command manager acquires a second command sent by the host, where the second command is a read command, a write command, an erase command, or another command; and judging whether the second command is a read command or a write command.

In some embodiments, if it is determined that the second command is not a read command, a write command, or an erase command, the command manager 310 sends a response message to the host indicating a command error.

Although the present application has been described with reference to examples, which are intended to be illustrative only and not to be limiting of the application, changes, additions and/or deletions may be made to the embodiments without departing from the scope of the application.

The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A hardware accelerator, comprising: a command manager, a read-write processor, a buffer memory, wherein,

the command manager judges whether a read command or a write command acquired from a host conforms to a protocol between the host and the storage device, and sends a first command conforming to the protocol to a CPU group, wherein the first command is the read command or the write command, and the CPU group comprises at least one CPU;

the read-write processor acquires a data index according to first information, and instructs a data moving unit to acquire read/write data corresponding to the first command, wherein the first information is acquired by the CPU group from the first command, the first information comprises the data index or information used for acquiring the data index, and if the first command is a read command, the read/write data comprises first data acquired by the data moving unit from a Dynamic Random Access Memory (DRAM);

the buffer memory buffers the data index.

2. The hardware accelerator of claim 1 wherein if the first command is a write command, the read/write data comprises second data retrieved by the data mover from a host according to the data index.

3. The hardware accelerator of claim 1 or 2, wherein the read-write processor receives tag information sent by a media interface controller, the tag information being used to characterize that the reading of the first data from the NVM by the media interface controller to the DRAM is completed, the tag information including identification information corresponding to the first command;

and the read-write processor instructs the data moving unit to acquire the first data from the DRAM according to the identification information and sends the first data to a host according to the data index.

4. The hardware accelerator of claim 3 wherein the tag information is fed back to the read write processor by the media interface controller after the first data is stored to the DRAM.

5. The hardware accelerator of claim 3, wherein if the first command is a read command, the read/write processor records a data length of the first data, wherein the data length of the first data is obtained by the read/write processor according to the first information;

responding to the label information, and recording the length of data which is sent to the host by the first command according to the label information by the read-write processor;

and the read-write processor responds to the length of the data to be read by the first command and equals to the length of the data which is sent to the host for the first command, and sends state information for representing the completion of the processing of the read command to the host.

6. The hardware accelerator of claim 3,

if the first command is a read command, the read-write processor records the length of data to be read by the first command;

the read-write processor responds to the received label information and records the length of the data read to the DRAM by the first command according to the label information;

and the read-write processor responds that the length of the data to be read by the first command is equal to the length of the data read to the DRAM for the first command, instructs the data moving unit to acquire the data read for the first command from the DRAM according to the identification information, and sends state information for representing the completion of the processing of the read command to the host.

7. The hardware accelerator of claim 2, wherein if the first command is a write command, the read/write processor instructs the data moving unit to obtain the second data from a host address corresponding to the data index after the buffer memory obtains the data index, and sends the second data to the media interface controller.

8. The hardware accelerator of claim 5 wherein the read and write processor allocates memory space of the DRAM for the second data and indicates the allocated memory space to the media interface controller to control the NVM to store the second data.

9. The hardware accelerator of any one of claims 2 to 8 further comprising at least two cache units, wherein the at least two cache units cache the first data or the second data in a ping-pong manner during the process of the data mover acquiring the second data from the host or sending the first data to the host.

10. The hardware accelerator of any one of claims 2-9 wherein the read and write processor is to send status information to the host characterizing completion of write command processing in response to the second data transfer to the media interface controller.