CN112751757A - Stacking system, switching device, chip and link failure recovery method - Google Patents
Stacking system, switching device, chip and link failure recovery method Download PDFInfo
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- CN112751757A CN112751757A CN202011587470.4A CN202011587470A CN112751757A CN 112751757 A CN112751757 A CN 112751757A CN 202011587470 A CN202011587470 A CN 202011587470A CN 112751757 A CN112751757 A CN 112751757A
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- aggregation group
- link aggregation
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L45/00—Routing or path finding of packets in data switching networks
- H04L45/24—Multipath
- H04L45/245—Link aggregation, e.g. trunking
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L45/00—Routing or path finding of packets in data switching networks
- H04L45/28—Routing or path finding of packets in data switching networks using route fault recovery
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/10—Packet switching elements characterised by the switching fabric construction
- H04L49/109—Integrated on microchip, e.g. switch-on-chip
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/30—Peripheral units, e.g. input or output ports
Abstract
The application provides a stacking system, a switching device, a chip and a link failure recovery method, wherein, the stacking system comprises a first switching device and a second switching device of link aggregation, a first port of the first switching device and a second port of the second switching device are both member ports of a link aggregation group, the first port and the second port are both provided with a receiving module for receiving data and a sending module for sending data, if data is transmitted from the first switching device to the second switching device, in response to the first link failure recovery between the first port and the second port, the sending module of the first port is controlled to add the delay time T into the link aggregation group compared with the receiving module of the second port, and thus, the probability of packet loss in the message transmission process can be reduced.
Description
Technical Field
The present invention relates to the field of network technologies, and in particular, to a stacking system, a switching device, a chip, and a link failure recovery method.
Background
In the prior art, in order to improve the link bandwidth, link aggregation is often selected to expand the link capacity under the condition that the single link bandwidth cannot be improved; in addition, link aggregation may be used to back up the links for backup purposes. When a link in the link aggregation group fails, a message is usually sent by switching, that is, by switching the message to be sent by other links in the link aggregation group, the requirement of link aggregation on the switching time is higher, but in many cases, the packet loss problem of link aggregation recovery is ignored.
In the prior art, as shown in fig. 1, a first port and a third port of a first switching device, and a second port and a fourth port of a second switching device form a link aggregation group, the first port and the third port are transmission ports, the second port and the fourth port are reception ports, when a first link between the first port and the second port is broken due to a failure, switching occurs on the first switching device and the second switching device, at this time, ports of a link aggregation group member on the two devices only include the third port and the fourth port, when the first link is recovered due to the failure, the first port and the second port need to be rejoined into the link aggregation group, because the first port and the second port cannot be joined at exactly the same time, if the second port is joined into the link aggregation group after the first port is joined for 100ms, a traffic flow between the first switching device and the second switching device will be discarded for 100ms, i.e. packet loss occurs.
Disclosure of Invention
In view of the above technical problems in the prior art, the present invention provides a stacking system, including a first switch device and a second switch device for link aggregation, where a first port of the first switch device and a second port of the second switch device are both member ports of a link aggregation group, and both the first port and the second port have a receiving module for receiving data and a sending module for sending data, and if data is transmitted from the first switch device to the second switch device, in response to a first link failure recovery between the first port and the second port, the sending module of the first port is controlled to join the link aggregation group with a delay time T compared with the receiving module of the second port.
Optionally, the range of the delay time T is: t is more than or equal to 1ms within 1000ms or more than or equal to 1s within 10 s.
Optionally, the first switch device includes a switch chip, where the switch chip is connected to the first port and is capable of controlling a time when the sending module of the first port joins the link aggregation group.
Optionally, the second switch device includes the switch chip.
Optionally, in response to the first link failing, switching to other links in the link aggregation group to transmit the packet.
In order to achieve the above object, the present invention provides a switch chip, which is applied to a switch device, wherein the switch device performs link aggregation with other switch devices to form a link aggregation group including a first port, the first port includes a sending module and a receiving module, and the switch chip recovers in response to a link failure where the first port is located:
if the first port is used for receiving data, the exchange chip can control the receiving module of the first port to be added into the link aggregation group in advance of time T compared with the sending module of the data sending port on the link; and/or
If the first port is used for sending data, the switch chip can control the sending module of the first port to add to the link aggregation group by the delay time T compared with the receiving module of the data receiving port on the link.
In order to achieve the above object, the present invention provides a switch device, which employs the switch chip described above.
In order to achieve the above object, the present invention provides a link failure recovery method for processing a link failure of the above-mentioned stacking system, the method including: a fault detection step, responding to the first link fault, and detecting whether the first link fault is recovered; and a link recovery step of adding the transmission module of the first port to the link aggregation group by a delay time T compared with the reception module of the second port in response to failure recovery of the first link.
Optionally, in the link recovery step, in response to failure recovery of the first link, the receiving module of the second port is added to the link aggregation group, and after a delay time T, the sending module of the first port is added to the link aggregation group.
According to the invention, the sending module and the receiving module of the two ports on the control link are distinguished, and the time for the sending module of the data sending port to join the link aggregation group when the link failure is recovered is set to be compared with the delay time T of the receiving module of the data receiving port, so that the data loss caused by the fact that the sending module of the data sending port joins the link aggregation group before the receiving module of the data receiving port is avoided.
Drawings
FIG. 1 is a schematic diagram of a stacking system according to the prior art;
FIG. 2 is a schematic structural diagram of a stacking system according to an embodiment of the present invention;
fig. 3 is a flowchart illustrating a link failure recovery method according to an embodiment of the present invention.
Detailed Description
The present invention will be described in detail below with reference to specific embodiments shown in the drawings. These embodiments are not intended to limit the present invention, and structural, methodological, or functional changes made by those skilled in the art according to these embodiments are included in the scope of the present invention.
Examples
The embodiment provides a stacking system, as shown in fig. 2, including a first switching device 1 and a second switching device 2 for link aggregation, where a first port 01 and a third port 03 of the first switching device 1 and a second port 02 and a fourth port 04 of the second switching device 2 are both member ports of a link aggregation group, the first to fourth ports each have a sending module for sending a message and a receiving module for receiving a message, taking as an example that a message transmits data to the second port 02 and the fourth port 04 from the first port 01 and the third port 03 respectively, a link between the first port 01 and the second port 02 is a first link, a link between the third port 03 and the fourth port 04 is a second link, the first port 01 has a sending module 011 and a receiving module 012, the second port 02 has a sending module 021 and a receiving module 022, and when the first link fails, the first switching device 1 and the second switching device 2 are switched to transmit data through the second link, the first switching device 1 is configured with a switching chip 11, and the switching chip 11 is connected to the first port 01 and the third port 03 and can control the first port 01 and the third port 03 to join or remove from the link aggregation group.
The adding/removing of the link aggregation group by each port may be implemented by modifying the table entry distribution of the link aggregation, and is not described herein again.
Further, the switch chip 11 can control the timing of joining/removing the link aggregation group by the transmitting module 011 and the receiving module 012 of the first port 01.
The first switching device 1 can perform real-time detection on the first link, and when the failure of the first link is recovered, the switching chip 11 can control the sending module 011 of the first port 01 to add to the link aggregation group by a delay time T compared with the receiving module 022 of the second port 02.
Optionally, the delay time T ranges from: t is more than or equal to 1ms within 1000ms or more than or equal to 1s within 10 s.
Optionally, the switch chip 11 can control the timing of joining the transmitting module 011 and the receiving module 012 of the first port 01 into the link aggregation group to meet the data transmission requirement in different application scenarios, for example, in some application scenarios with a high requirement on the information interaction response time, the delay time T may be set to be shorter.
In this embodiment, an example of configuring a switch chip with the first switch device 1 is given, and actually, the second switch device 2 may also have a port (not shown) for sending a message, and therefore, a switch chip that achieves the same function as the switch chip 11 may also be configured for the second switch device 2.
It should be noted that this embodiment is only an exemplary illustration of the spirit of the present invention, and a person skilled in the art can easily think based on this embodiment that the stacking system may further include a third switch device (not shown), and the first switch device 1 and the second switch device 2 in the stacking system may further include a plurality of member ports of other link aggregation groups, and the above embodiments are all within the protection scope of the present invention.
It should be noted that there may also be a common port that is not included in the link aggregation group in the first switching device 1 and the second switching device 2, and if the port for processing the packet obtained according to the feature field of the packet is a common port, it is not in the scope of research in this embodiment, since packet processing and port selection of the common port are well known to those skilled in the art, and details are not described here again.
The present embodiment further provides a switch chip, which is applied to the above-mentioned switch device and stacking system, and is capable of controlling, when a link failure between each switch device of link aggregation is recovered, a timing at which a sending module and/or a receiving module of a data transmission port of the switch device joins in a link aggregation group, for example, link aggregation between the switch device and another switch device forms a link aggregation group including a first port 01, where the first port 01 includes a sending module 011 and a receiving module 012, and the link failure recovery is performed in response to the link failure where the first port 01 is located:
if the first port 01 is used to receive data, the switch chip 11 can control the receiving module 012 of the first port 01 to advance time T to join the link aggregation group compared with the sending module (not shown) of the data sending port on the link; and/or
If the first port 01 is used to transmit data, the switch chip 11 can control the sending module 011 of the first port 01 to delay time T from joining the link aggregation group compared with the receiving module (not shown) of the data receiving port on the link.
The present embodiment further provides a link failure recovery method, as shown in fig. 3, which is applied to process the above-mentioned link failure of the stacking system, and if the data transmission direction is from the first port 01 to the second port 02, the method includes:
a fault detection step of detecting whether the fault of the first link is recovered or not in response to the first link being in fault; and
a link recovery step of, in response to failure recovery of the first link, adding the transmitting module 011 of the first port 01 to the link aggregation group with a delay time T compared with the receiving module 022 of the second port 02.
With such a configuration, it can be avoided that the transmitting module 011 of the first port 01 joins the link aggregation group before the receiving module 022 of the second port 02 joins the link aggregation group, which results in data loss.
It should be noted that, based on the link failure recovery method provided in this embodiment, a person skilled in the art can easily know that when the data transmission direction changes, the link failure recovery scheme is adjusted accordingly, and details are not described here.
Optionally, in the link recovery step described above, in response to the failure recovery of the first link, the receiving module 022 of the second port 02 is added to the link aggregation group, and after a delay time T, the transmitting module 011 of the first port 01 is added to the link aggregation group, that is, if the link failure recovers, the receiving module 022 of the second port 02 is immediately added to the link aggregation group to ensure the normal operation of the subsequent data link, at this time, both the second port 02 and the fourth port 04 can participate in the reception of the packet, and after the delay time T, the transmitting module 011 of the first port 01 is added to the link aggregation group, at this time, the data transmitted by the first port 01 is received by the second port 02 without transmitting a packet loss, thereby ensuring the stability of the network.
Since the technical contents and features of the present invention have been disclosed above, those skilled in the art can make various substitutions and modifications without departing from the spirit of the present invention based on the teaching and disclosure of the present invention, and therefore, the scope of the present invention is not limited to the disclosure of the embodiments, but includes various substitutions and modifications without departing from the present invention, and is covered by the claims of the present patent application.
Claims (9)
1. A stacking system comprises a first switching device and a second switching device of link aggregation, wherein a first port of the first switching device and a second port of the second switching device are both member ports of a link aggregation group, and the first port and the second port both have a receiving module for receiving data and a sending module for sending data.
2. The stacking system of claim 1, wherein the delay time T ranges from: t is more than or equal to 1ms within 1000ms or more than or equal to 1s within 10 s.
3. The stacking system of claim 1 or 2, wherein the first switching device comprises:
and the switching chip is connected with the first port and can control the time when the sending module of the first port joins the link aggregation group.
4. The stacking system of claim 3, wherein the second switch device comprises the switch chip.
5. The stacking system of any of claims 1-2 and 4, wherein in response to a failure of the first link, switching to other links in the link aggregation group to transmit messages.
6. A switching chip is applied to a switching device, the switching device is subjected to link aggregation with other switching devices to form a link aggregation group including a first port, the first port includes a sending module for sending data and a receiving module for receiving data, and the switching chip is characterized in that, in response to the failure recovery of a link where the first port is located:
if the first port is used for receiving data, the exchange chip can control the receiving module of the first port to be added into the link aggregation group in advance of time T compared with the sending module of the data sending port on the link; and/or
If the first port is used for sending data, the switch chip can control the sending module of the first port to add to the link aggregation group by the delay time T compared with the receiving module of the data receiving port on the link.
7. A switching device, characterized in that the switching chip of claim 6 is applied.
8. A link failure recovery method for processing a link failure of the stack system according to any one of claims 1 to 5, the method comprising:
a fault detection step, responding to the first link fault, and detecting whether the first link fault is recovered; and
a link recovery step of adding the delay time T of the sending module of the first port to the link aggregation group compared with the delay time T of the receiving module of the second port in response to failure recovery of the first link.
9. The link failure recovery method according to claim 8, wherein in the link recovery step, the receiving module of the second port is added to the link aggregation group in response to failure recovery of the first link, and the transmitting module of the first port is added to the link aggregation group after a delay time T.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202011587470.4A CN112751757A (en) | 2020-12-29 | 2020-12-29 | Stacking system, switching device, chip and link failure recovery method |
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| CN202011587470.4A CN112751757A (en) | 2020-12-29 | 2020-12-29 | Stacking system, switching device, chip and link failure recovery method |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101552725A (en) * | 2009-05-13 | 2009-10-07 | 杭州华三通信技术有限公司 | Recovery processing method, system and apparatus of aggregation sublink |
| US20150271104A1 (en) * | 2014-03-20 | 2015-09-24 | Brocade Communications Systems, Inc. | Redundent virtual link aggregation group |
| CN108933744A (en) * | 2018-06-26 | 2018-12-04 | 新华三技术有限公司 | A kind of message forwarding method and device |
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2020
- 2020-12-29 CN CN202011587470.4A patent/CN112751757A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101552725A (en) * | 2009-05-13 | 2009-10-07 | 杭州华三通信技术有限公司 | Recovery processing method, system and apparatus of aggregation sublink |
| US20150271104A1 (en) * | 2014-03-20 | 2015-09-24 | Brocade Communications Systems, Inc. | Redundent virtual link aggregation group |
| CN108933744A (en) * | 2018-06-26 | 2018-12-04 | 新华三技术有限公司 | A kind of message forwarding method and device |
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