CN112750476A - Configuration memory bit line control circuit and FPGA bit line control system - Google Patents
Configuration memory bit line control circuit and FPGA bit line control system Download PDFInfo
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
- G11C7/1057—Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
- G11C7/1084—Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
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Abstract
According to the configuration memory bit line control circuit and the FPGA bit line control system, the data control read-write module writes received data into the storage module or reads the data in the storage module according to the state and the signal of the bit line control circuit, and drives the data control read-write module in the transmission process of writing the received data into the storage module; therefore, the invention can avoid the influence of the parasitic capacitance resistance by adding the driving buffer, improve the expandability of the system, shorten the time for new products to appear and reduce the research and development cost of the products.
Description
Technical Field
The invention relates to the Field of FPGA (Field-Programmable Gate Array) design, in particular to a configuration memory bit line control circuit and an FPGA bit line control system.
Background
FPGAs are developed based on Programmable devices such as PAL (Programmable Array Logic), GAL (general Array Logic), CPLD (Complex Programmable Logic Device), and the like. The Circuit is used as a semi-custom Circuit in the field of Application Specific Integrated Circuits (ASICs), not only overcomes the defects of the custom Circuit, but also overcomes the defect that the number of gate circuits of the original programmable device is limited.
Referring to fig. 1, the basic FPGA is mainly composed of the following parts: programmable input output IO block 101, programmable interconnect block 102, and programmable logic block 103. A user can implement various designs through the configurable logic module 103, communicate with the outside through the configurable input/output IO module 101, and ensure input/output voltage and current standards, and connect the configurable input/output IO module 101 and the configurable logic module 103 through the configurable interconnection module 102.
Generally, an FPGA corresponds to a very large set of digital circuits, which do not have specific circuit functions, and needs to be specifically designed and converted into configuration bitstreams supported by the FPGA to select some circuits of the set of digital circuits to be combined so as to realize the specific circuits desired by the FPGA. However, when the super-large-scale FPGA is designed in an expanded manner, bit line control has some problems, such as influence of parasitic capacitance and resistance, which may limit expansion of the super-large-scale FPGA.
Disclosure of Invention
The invention provides a bit line control circuit for a configuration memory and an FPGA (field programmable gate array) bit line control system, and aims to solve the problem of limitation in bit line control in the expansion design of the existing ultra-large-scale FPGA.
To solve the above technical problem, the present invention provides a bit line control circuit for a configuration memory, comprising: the device comprises a data read-write control module, a storage module, a transmission module and a buffer;
the data read-write control module is used for writing the received data into the storage module or reading the data in the storage module according to the state and the signal of the bit line control circuit;
the storage module is used for storing the data written or read by the data read-write control module;
the transmission module is used for transmitting the data received by the data read-write control module or the data read from the storage module;
and the buffer is used for increasing drive in the transmission process of writing the received data into the storage module by the data read-write control module.
Optionally, the transmission module includes a bit line transmission channel, and the buffer is disposed on the bit line transmission channel according to a preset distance.
Optionally, the data read-write control module includes a write word line control circuit, a write driving circuit, and a read matching circuit;
the write driving circuit is used for generating BL signals according to the received data, and the BL signals are respectively transmitted from left to right;
the write word line control circuit is used for writing the BL signal into the storage module;
and the read matching circuit is used for reading the data in the storage module.
Optionally, the states of the bit line control circuit include a write state and a read-back state, and the signal is a word line signal;
in a write state, the write word line control circuit writes the BL signal into the memory module when the word line signal is 1;
in a read state, the read support circuit reads the output signal when the word line signal is 1.
Optionally, the buffer is bidirectional.
Optionally, the memory module includes a MOS transistor and an inverter connected to each other.
Optionally, the MOS transistor includes a first MOS transistor and a second MOS transistor, and the inverter includes a first inverter and a second inverter;
the first MOS tube and the second MOS tube are connected in series, and the first phase inverter and the second phase inverter are connected in parallel and arranged between the first MOS tube and the second MOS tube.
In order to solve the above problem, the present invention further provides an FPGA bit line control system, including: a configuration register, a programmable logic module, and a configuration memory bit line control circuit as claimed in any one of claims 1-7; the programmable logic module comprises at least one region, and a bit line control circuit of the configuration memory is arranged in each region;
the configuration register is used for configuring a frame address and outputting the frame address and data to the bit line control circuit of the configuration memory;
the configuration memory bit line control circuit is used for writing the data into the memory module corresponding to the address when writing operation is carried out; and when the reading operation is carried out, reading the data in the corresponding storage module according to the address.
Optionally, the positive configuration register includes a frame address register, a frame data input register, and a frame data output register; the configuration memory bit line control circuit also comprises a frame address data conversion module;
the frame address register is used for configuring a frame address and sending frame address data to the frame address data conversion module;
the frame data input register is used for outputting data to the data read-write control module;
the data read-write control module is used for writing the data into the storage module corresponding to the address through the buffer; the data reading module is also used for reading data from the storage module according to the address and sending the read data to the frame data input register;
the frame data input register is also used for receiving the data read from the storage module by the data read-write control module;
and the data read-write control module is also used for reading the data from the frame data input register and sending the data to the frame data output register.
Optionally, the FPGA bit line control system further includes at least one multi-stage buffer and at least one two-stage nand gate;
the multistage buffer is used for receiving the data input by the frame data input register and sending the data to the bit line control circuit of the configuration memory in the corresponding area;
and the two-stage NAND gate is used for outputting the read data to the frame data output register during read-back.
The invention has the beneficial effects that:
according to the configuration memory bit line control circuit and the FPGA bit line control system, the data control read-write module writes received data into the storage module or reads the data in the storage module according to the state and the signal of the bit line control circuit, and drives the data control read-write module in the transmission process of writing the received data into the storage module; therefore, the invention can avoid the influence of the parasitic capacitance resistance by adding the driving buffer, improve the expandability of the system, shorten the time for new products to appear and reduce the research and development cost of the products.
Additional features and corresponding advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.
Drawings
FIG. 1 is a schematic diagram of a general structure of an FPGA;
FIG. 2 is a schematic diagram of a very large-scale FPGA;
FIG. 3 is a schematic diagram of a generic FPGA configuration memory interface structure;
fig. 4 is a schematic control structure diagram of a very large-scale FPGA according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of a bit line control circuit for a local configuration memory according to an embodiment of the present invention;
FIG. 6 is a circuit diagram of a configuration memory according to an embodiment of the present invention;
fig. 7 is a schematic diagram of data transmission of bit line control signals and frame data input/output between a plurality of regions in the FPGA system according to the second embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 2, a schematic structural diagram of a very large scale FPGA is shown, where the structure of the very large scale FPGA mainly includes five parts, a Configuration Control System 201 (CCS), a programmable input/output IO module 202, high-speed serdes203, a DLL204(Delay-locked Loop), and a programmable logic module 205.
The configuration control system is mainly used for completing the function configuration and control operation of a full chip and mainly comprises a configuration data stream, a configuration control circuit, a configuration memory and the like; the configuration control system writes configuration bit stream data of a user into a corresponding configuration data memory SRAM, controls gating or closing of each circuit module through the output of the SRAM, and finally combines the circuit modules into a circuit system with a specific function.
The most basic and important function of the FPGA configuration control system is to write huge configuration data with a certain format into a configuration memory quickly and accurately. The configuration process is independent of the actual circuit of the user, and no matter how complex the design of the user is, as long as the chip scale can meet the design requirements of the user, the working process of the configuration control system is not different. The FPGA full chip is divided into a plurality of similar regions, main programmable logic resources are divided into a plurality of regions, and with the increase of the gate level number and the chip area, higher requirements are put forward to a control system of the whole FPGA, for example, a configuration memory requires that the FPGA configuration control system can select any region, line, column and frame storage units, so that the configuration memory can be flexibly configured, the configuration and the reconfiguration can be rapidly and accurately carried out, the configuration time is reduced, and the configuration efficiency is improved.
Referring to fig. 3, fig. 3 is a schematic diagram of a general FPGA configuration memory interface structure. As shown in the figure, the interface structure of the FPGA configuration memory comprises a frame address data conversion module and a data read-write control module, and the configuration register comprises a frame address register, a frame data input register and a frame data output register; when the configuration operation is carried out, the configuration register outputs the address configured by the frame address register and the data of the frame data input register to the configuration memory interface, and the configuration memory interface writes the data into the memory cell of the corresponding address of the configuration memory. When the read-back operation is carried out, the configuration memory interface reads out the data content stored in the storage unit of the address corresponding to the configuration memory to the frame data input register in the configuration register according to the address configured by the frame address register given by the configuration register, then the configuration memory interface reads out the data content from the frame data input register, outputs the data to the frame data output register according to the time sequence of the interface standard specification, and finally outputs the data to the user for use.
In the configuration memory interface, a frame address data conversion module processes frame address data obtained from a frame address register, converts the frame address data into a corresponding area address, a column address and a frame address in the configuration memory and outputs the area address, the column address and the frame address to the configuration memory, and a data read-write control module writes data into a storage unit of a corresponding address of the configuration memory or reads the data from the storage unit of the corresponding address of the configuration memory according to whether the configuration control system carries out configuration operation or read-back operation.
However, in the existing ultra-large-scale FPGA, because parasitic resistance and capacitance exist in the same region, normal data writing is influenced, and bit line control among a plurality of regions has certain limitation, so that the ultra-large-scale FPGA is influenced to continue to increase the regions for expansion.
In order to solve the above problems, the present invention provides a bit line control circuit for a configuration memory, which includes a data read-write control module, a storage module, a transmission module and a buffer, wherein the data read-write control module writes received data into the storage module or reads data in the storage module according to a state and a signal of the bit line control circuit, and drives the data read-write control module in a transmission process of writing the received data into the storage module; therefore, the influence of parasitic capacitance resistance can be avoided by adding the driving buffer, the expandability of the system is improved, the time for new products to appear is shortened, and the research and development cost of the products is reduced. The present invention will be described in further detail with reference to the following detailed description and accompanying drawings.
The first embodiment is as follows:
the bit line control circuit for the configuration memory provided by the embodiment comprises a data read-write control module, a storage module, a transmission module and a buffer;
the data read-write control module is used for writing the received data into the storage module or reading the data in the storage module according to the state and the signal of the bit line control circuit;
the storage module is used for storing the data written in or read out by the data reading and writing module;
the transmission module is used for transmitting the data received by the data read-write control module or the data read from the storage module;
and the buffer is used for increasing drive in the transmission process that the data read-write control module writes the received data into the storage module.
The control structure of the ultra-large-scale FPGA comprises a plurality of regions, specifically, as shown in fig. 4, 401, 402, 403, and 403 are region1, region2, region3, and region4, respectively. It should be noted that, the number of the regions divided by the ultra-large-scale FPGA in the embodiment is only used for describing the present invention, and is not used for limiting the present invention.
The present embodiment is described in detail with a configuration memory bit line control circuit (see fig. 5) in one area.
In this embodiment, the transmission module specifically includes a bit line transmission channel, and the buffer is disposed on the bit line transmission channel according to a predetermined distance. It should be understood that there is parasitic resistance capacitance on the bit line transmission channel, and in order to avoid the influence on the normal writing data, a double buffer is arranged on the bit line transmission channel at intervals to ensure that the parasitic resistance capacitance between the two buffers does not exceed the parasitic resistance capacitance capable of writing data normally. In some application scenarios of the present embodiment, the preset distance may be determined according to the maximum parasitic resistance and capacitance of the circuit; it should be noted that the maximum parasitic resistance and capacitance needs to be determined specifically according to a specific process.
In this embodiment, the buffer is bidirectional; the buffer is used on the bus to improve the driving ability and isolate the front and rear stages, so that the buffer mostly has a tri-state output function. Specifically, when the load does not have the non-gating output and has high resistance, the isolation function is achieved; when the driving capability of the bus is not enough to drive the load, the driving function is played.
In this embodiment, the data read-write control module specifically includes a write word line control circuit, a write driving circuit, and a read matching circuit; the write driving circuit can generate BL signals according to the received data, and the BL signals are respectively transmitted from left to right; the write word line control circuit writes the BL signal into the storage module; the read supporting circuit reads data in the storage module, so that the expansion design of the FPGA in the transverse direction can be supported.
Specifically, as shown in fig. 5, data received by the write driving circuit is input by a frame data input register in the CCS, and the received data passes through the write driving circuit to generate BL signals respectively transmitted to the left and the right, where the BL signals in this embodiment are 3232-bit BL signals. In this embodiment, a bidirectional buffer 501 is inserted into the bit line transmission channel at intervals to ensure that the parasitic resistance capacitance between the two buffers does not exceed the parasitic resistance capacitance capable of normally writing data; the write word line control circuit writes the BL signal into the memory block.
In this embodiment, the storage module may be a configuration memory, including but not limited to CRAM.
Referring to fig. 6, a circuit diagram for configuring a memory includes a MOS transistor and a phase inverter, which are connected to each other, specifically, the MOS transistor includes a first MOS transistor MN1 and a second MOS transistor MN2, the phase inverter includes a first phase inverter I1 and a second phase inverter I2, the first MOS transistor MN1 and the second MOS transistor MN2 are connected in series, and the first phase inverter I1 and the second phase inverter I2 are connected in parallel and disposed between the first MOS transistor MN1 and the second MOS transistor MN 2. The gate connection voltages of MN1 and MN2 are the supply voltage ADDR, which is also the word line signal; the source of MN1 is connected to the data signal value written when the voltage ADDR is 1, the drain of MN1 is connected to one end of I1 and I2 which are connected in parallel; the source of MN2 is connected with the other end of I1 and I2 which are connected in parallel, and the drain of MN2 is connected with datan; the q signal value read when the voltage ADDR at one end of I2 is 1, and the voltage qb at the other end of I2.
In this embodiment, the state of the bit line control circuit includes a write state and a read-back state, and specifically, when data is written, a value of a data signal is written when an ADDR of the configuration memory is 1 through the write word line control circuit and the write driver circuit. When reading data, the value of the q signal is read when the ADDR of the configuration memory is 1 through a read supporting circuit, such as a precharge circuit, a sensitive amplifying circuit and the like and a read word line control circuit. It should be noted that when data is written into the configuration memory, the data needs to be discharged to a low level, and if the data cannot be discharged to the low level within the time of starting the ADDR, the written data fails; and the final low-level voltage value after data discharge is determined by the related resistance voltage division in the write data path.
In this embodiment, the bit line control circuit of the configuration memory shown in fig. 5 can write the configuration bit stream, i.e., 3,232 bit BL signal, into the configuration memory in the programmable logic module 502 when the word line signal ADDR is 1, so as to implement a specific function.
In the bit line control circuit for the configuration memory provided by this embodiment, the bit line control circuit for the configuration memory includes a data read-write control module, a storage module, a transmission module and a buffer, the data read-write control module writes received data into the storage module or reads data in the storage module according to a state and a signal of the bit line control circuit, and a drive is added in a transmission process of the data read-write control module writing the received data into the storage module; in the ultra-large-scale FPGA circuit, due to the influence of parasitic resistance and capacitance in the same region, the bit line driven bidirectional buffer is added within a certain distance range, so that the transverse extension design of the ultra-large-scale FPGA is supported, the system expandability is improved, the time for new products to come out is shortened, and the research and development cost of the products is reduced.
Example two:
based on the foregoing embodiments, the present embodiment provides an FPGA bit line control system, including: the device comprises a configuration register, a programmable logic module and a configuration memory bit line control circuit; the configuration register is used for configuring a frame address and outputting frame address data and data to the bit line control circuit of the configuration memory; configuring a memory bit line control circuit, which is used for writing data into a memory module corresponding to an address when writing operation is carried out; and when the reading operation is carried out, reading out the data in the corresponding memory module according to the address.
In this embodiment, the programmable logic module includes at least one region, and a configuration memory bit line control circuit is disposed in each region, and is described in detail in the above embodiments, and is not described here again.
The configuration register comprises a frame address register, a frame data input register and a frame data output register, and the configuration memory bit line control circuit also comprises a frame address data conversion module;
the frame address register is used for configuring a frame address and sending frame address data to the frame address data conversion module;
the frame data input register is used for outputting data to the data read-write control module;
the data read-write control module is used for writing data into the storage module corresponding to the address through the buffer, reading the data from the storage module according to the address and sending the read data to the frame data input register;
the frame data input register is also used for receiving the data read from the storage module by the data read-write control module;
and the data read-write control module is also used for reading out the data content from the frame data input register and sending the read-out data content to the frame data output register.
In this embodiment, the bit line control circuit of the configuration memory includes a configuration memory and a configuration memory interface, the configuration memory corresponds to the storage module, and the data read-write control module is disposed in the configuration memory interface.
In this embodiment, the control structure of the very large-scale FPGA includes a plurality of regions, and thus the FPGA bit line control system further includes at least one multi-stage buffer and at least one two-stage nand gate;
the multistage buffer is used for receiving data input by the frame data input register and sending the data to the bit line control circuit of the configuration memory in the corresponding area;
and a two-stage NAND gate for outputting the read data to the frame data output register at the time of read-back.
In this embodiment, the multi-stage buffer is formed by connecting at least two buffers in series, the two-stage nand gate is formed by connecting at least two nand gates in series, and specific connection modes between the buffers, between the nand gates, between the buffers and the regions, and between the nand gates and the regions are shown in fig. 7.
Fig. 7 is a schematic diagram of data transmission of bit line control signals and frame data input/output between multiple regions in an FPGA system.
As shown in the figure, the frame data input signal output by the frame data input register in the CCS is respectively fed into the bit line control circuit of the configuration memory of each region through the multi-stage buffer; during read-back, the frame data output signal is controlled in each region by the two-stage nand gate and the adjacent region read-back signals and control signals 601, 603, 604, 605, etc., and the final output signal is transmitted to the frame data output register inside the CCS, which is initially 1 in 602 in this embodiment. The configuration bit stream writing and reading back functions of the whole chip can be completed through the structure.
In the FPGA bit line control system provided in this embodiment, the frame data input signal is respectively sent to the bit line control circuit of the configuration memory of each region through the multi-stage buffer, and the frame data output signal is controlled to output the frame data output signal through the two-stage nand gate and the read-back signal and the control signal of the adjacent region; the method and the device realize signal transmission and connection among a plurality of regions in the super-large-scale FPGA circuit, further support the continuous increase of the regions in the longitudinal direction for extended design, improve the expandability of the system, shorten the time for new products to appear and reduce the research and development cost of the products.
The foregoing is a more detailed description of the present invention that is presented in conjunction with specific embodiments, and the practice of the invention is not to be considered limited to those descriptions. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.
Claims (10)
1. A configuration memory bit line control circuit, comprising: the device comprises a data read-write control module, a storage module, a transmission module and a buffer;
the data read-write control module is used for writing the received data into the storage module or reading the data in the storage module according to the state and the signal of the bit line control circuit;
the storage module is used for storing the data written or read by the data read-write control module;
the transmission module is used for transmitting the data received by the data read-write control module or the data read from the storage module;
and the buffer is used for increasing drive in the transmission process of writing the received data into the storage module by the data read-write control module.
2. The configuration memory bit line control circuit of claim 1, wherein the transfer module comprises a bit line transfer channel, and the buffer is disposed on the bit line transfer channel at a predetermined distance.
3. The bit line control circuit of claim 1, wherein the data read/write control module comprises a write word line control circuit, a write driver circuit, and a read companion circuit;
the write driving circuit is used for generating BL signals according to the received data, and the BL signals are respectively transmitted from left to right;
the write word line control circuit is used for writing the BL signal into the storage module;
and the read matching circuit is used for reading the data in the storage module.
4. The configuration memory bitline control circuit of claim 3, wherein the bitline control circuit is in a state comprising a write state and a read-back state, the signal being a wordline signal;
in a write state, the write word line control circuit writes the BL signal into the memory module when the word line signal is 1;
in a read state, the read support circuit reads the output signal when the word line signal is 1.
5. The configuration memory bit line control circuit of any of claims 1-4, wherein the buffer is bidirectional.
6. The configuration memory bit line control circuit of any one of claims 1-4, wherein the memory block comprises interconnected MOS transistors and inverters.
7. The configuration memory bit line control circuit of claim 6, wherein the MOS transistor comprises a first MOS transistor and a second MOS transistor, and the inverter comprises a first inverter and a second inverter;
the first MOS tube and the second MOS tube are connected in series, and the first phase inverter and the second phase inverter are connected in parallel and arranged between the first MOS tube and the second MOS tube.
8. An FPGA bit line control system, comprising: a configuration register, a programmable logic module, and a configuration memory bit line control circuit as claimed in any one of claims 1-7; the programmable logic module comprises at least one region, and a bit line control circuit of the configuration memory is arranged in each region;
the configuration register is used for configuring a frame address and outputting the frame address and data to the bit line control circuit of the configuration memory;
the configuration memory bit line control circuit is used for writing the data into the memory module corresponding to the address when writing operation is carried out; and when the reading operation is carried out, reading the data in the corresponding storage module according to the address.
9. The FPGA bitline control system of claim 8, wherein the configuration registers include a frame address register, a frame data input register, and a frame data output register; the configuration memory bit line control circuit also comprises a frame address data conversion module;
the frame address register is used for configuring a frame address and sending frame address data to the frame address data conversion module;
the frame data input register is used for outputting data to the data read-write control module;
the data read-write control module is used for writing the data into the storage module corresponding to the address through the buffer; the data reading module is also used for reading data from the storage module according to the address and sending the read data to the frame data input register;
the frame data input register is also used for receiving the data read from the storage module by the data read-write control module;
and the data read-write control module is also used for reading the data from the frame data input register and sending the data to the frame data output register.
10. The FPGA bitline control system of claim 8, further comprising at least one multi-stage buffer and at least one two-stage nand gate;
the multistage buffer is used for receiving the data input by the frame data input register and sending the data to the bit line control circuit of the configuration memory in the corresponding area;
and the two-stage NAND gate is used for outputting the read data to the frame data output register during read-back.
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| CN101425329A (en) * | 2007-11-01 | 2009-05-06 | 松下电器产业株式会社 | Semiconductor storage device |
| CN101740107A (en) * | 2009-11-20 | 2010-06-16 | 中国科学院声学研究所 | Bit line cutting buffer |
| CN101826038A (en) * | 2010-04-28 | 2010-09-08 | 复旦大学 | Circuit and method for resisting SEU of SRAM FPGA device |
| CN102566982A (en) * | 2012-01-10 | 2012-07-11 | 复旦大学 | Two-stage FPGA (field programmable gate array) pipeline configuration circuit |
| CN104951411A (en) * | 2014-03-28 | 2015-09-30 | 萧志成 | Low power consumption memory |
| CN105976858A (en) * | 2016-07-05 | 2016-09-28 | 苏州无离信息技术有限公司 | SRAM storage unit capable of stably working under low voltage |
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| CN116450216A (en) * | 2023-06-12 | 2023-07-18 | 上海灵动微电子股份有限公司 | Local caching method for shared hardware operation unit |
| CN116450216B (en) * | 2023-06-12 | 2023-08-29 | 上海灵动微电子股份有限公司 | Local caching method for shared hardware operation unit |
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