CN112749524A - Hardware Trojan horse circuit detection method based on residual error encoder neural network - Google Patents
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Abstract
The invention relates to the technical field of hardware Trojan horse circuit detection, in particular to a hardware Trojan horse circuit detection method based on a residual error encoder neural network, which comprises the following steps: acquiring a Verilog file in a circuit design stage, and extracting effective features according to the Verilog file to obtain an effective feature set of a hardware Trojan circuit; based on the correlation of the effective features to the Trojan horse circuit, selecting strong correlation features from an effective feature set of the hardware Trojan horse circuit by adopting a key feature selection method; and inputting the strong correlation characteristics into a residual convolutional encoder network, and identifying the Trojan horse circuit by the residual convolutional encoder network according to the input characteristics. The invention provides a residual error Encoder neural network model, which combines a residual error neural network (ResNet) and an Encoder (Encoder), can prevent the network degradation problem, and has lower error rate and higher accuracy compared with the traditional machine learning algorithm.
Description
Technical Field
The invention relates to the technical field of hardware Trojan horse circuit detection, in particular to a hardware Trojan horse circuit detection method based on a residual error encoder neural network.
Background
With the development of semiconductor process technology, the demand of hardware products is increasing, and in order to meet the demand of hardware products, an integrated circuit supplier needs to outsource the products to a third party supplier. Since third party vendors are not always reliable, hardware trojans may be inserted during the design or manufacturing process of integrated circuits, and particularly, malicious vendors need only modify design files to insert hardware trojans during the design stage, which strongly requires the necessity of detecting hardware trojans during the design stage.
The traditional detection method (see fig. 1) of the hardware trojan circuit can be divided into destructive detection and non-destructive detection, wherein 1) the destructive detection mainly refers to physical detection, such as: a Trojan horse circuit is obtained by adopting reverse engineering and is compared with an original circuit, so that whether a hardware Trojan horse exists or not is determined. 2) Non-destructive testing can be subdivided into invasive methods with intervening self-test circuitry, and non-invasive methods involving, for example, logic tests, channel analysis, etc.
The Trojan circuit detection based on the traditional detection method needs to consume too much time to trigger the Trojan circuit, and then results are compared. This requires that we must know the trigger state of the trojan circuit and the detection result is limited by the input, so recently researchers have proposed a machine learning based method to detect the trojan circuit. In a machine learning-based method, an existing data set basically adopts a design phase data set, and a reference data set with a hardware Trojan horse circuit and a normal Trojan horse circuit is selected at the same time. In the machine learning perspective, the Trojan circuit detection can be regarded as a traditional binary problem, namely, whether the Trojan circuit or the normal circuit is detected.
Application of machine learning to Trojan circuits researchers have studied feature selection and models.
1) The feature selection method can be divided into an integrated circuit image, a signal analysis, a gate level list network feature, a function and structure feature analysis, a side channel correlation feature analysis method, and the like, and can be specifically shown in fig. 2.
2) Traditional machine learning algorithms are mostly adopted on models, for example: SVM, K-means, RF, etc. In addition, researchers have also investigated the detection of trojan horse circuits based on multi-layer artificial neural networks.
Whether a traditional detection method or a machine learning-based detection method is adopted, the extraction of the characteristics of the data set in the related research is very poor.
Disclosure of Invention
In order to solve the above problems, the present invention provides a hardware Trojan horse circuit detection method based on a residual error encoder neural network.
A hardware Trojan horse circuit detection method based on a residual error encoder neural network comprises the following steps:
s1, acquiring a Verilog file in a circuit design stage, and extracting effective features according to the Verilog file to obtain an effective feature set of the hardware Trojan horse circuit;
s2, selecting strong correlation characteristics from the effective characteristic set of the hardware Trojan horse circuit by adopting a key characteristic selection method based on the correlation of the effective characteristics to the Trojan horse circuit;
and S3, inputting the strong correlation characteristics into a residual convolutional encoder network, and identifying the Trojan horse circuit by the residual convolutional encoder network according to the input characteristics.
In a preferred embodiment, in step S1, the set of valid features of the hardware trojan circuit is predefined, and the set of valid features of the hardware trojan circuit includes: the number of input gates, the number of output gates, the maximum distance from the input gates to the output gates, the number of input gates to different gate levels, the number of output gates to different gate levels, and the number of logic gates.
In a preferred embodiment, in step S1, extracting effective features of the hardware trojan horse circuit from the Verilog file by using a language marking method includes:
s11, marking input gates, output gates and other gate levels of Verilog with different colors;
s12, counting the occurrence times of each color;
and S13, calculating the average value of the color occurrence times, and summarizing the gate levels larger than the average value, wherein the summarized characteristic is the effective characteristic of the hardware Trojan horse circuit.
In a preferred embodiment, in step S2, selecting a strong correlation feature from the valid feature set of the hardware trojan horse circuit by using a key feature selection method specifically includes:
s21, firstly, calculating the correlation between different effective characteristics and the Trojan horse circuit by using the Pearson correlation coefficient, and sequencing to obtain a Pearson correlation result;
s22, processing the effective feature set of the hardware Trojan horse circuit by using a recursive feature elimination method to obtain a recursive feature elimination method result;
and S23, arranging the Pearson correlation result and the recursive feature elimination result in the front union as a strong correlation feature.
In a preferred embodiment, the structure of the residual convolutional encoder network comprises a residual neural network structure and an encoder network, wherein the residual neural network structure adopts a basic block (basic block) structure, two continuous basic block structures are arranged in the residual convolutional encoder network, and the main function is to prevent the network degradation problem; and then input to an encoder architecture that employs two convolutional neural networks.
In a preferred embodiment, the identifying the trojan horse circuit according to the input data by the residual convolutional encoder network specifically comprises:
s31, grid list data with input dimensions of 1 × 12 for the residual convolutional encoder network;
s32, firstly, passing through the convolution layer of 1 × 1, filling with the step size of 1 and 0, and obtaining data with the dimension of 64 × 12;
s33, the data with the dimension of 64 × 12 passes through a basic block (basic block) structure of a residual neural network to obtain the data with the dimension of 64 × 12;
s34, processing by an encoder (encoder) to obtain data with the dimension of 256 × 4;
s35, passing through a maximum pooling layer (max-pool), and obtaining data with the dimension of 256 x 2;
and S36, finally outputting a prediction result through the full connection layer, wherein if the output prediction result is 1, the circuit is abnormal, namely the Trojan horse circuit, and if the output prediction result is 0, the circuit is normal.
The invention has the beneficial effects that:
1. the invention defines the key characteristic description of the hardware Trojan horse circuit and has the detailed description of each characteristic; the language marking method can be used for extracting important features in Verilog.
2. The invention provides a residual error Encoder neural network model, which combines a residual error neural network (ResNet) and an Encoder (Encoder), can prevent the network degradation problem and reduce the false alarm rate; in addition, compared with the traditional machine learning algorithm, the neural network has the advantages of lower error rate, higher accuracy and unique advantages in the aspect of classification.
3. The invention provides a key feature selection method, which combines a Pearson correlation coefficient method and a recursive feature screening method to respectively calculate results, obtains strong correlation features (key features) according to the Pearson correlation results and the recursive feature elimination method results, and can select the most representative features, thereby obtaining more accurate results in a model.
Drawings
The present invention will be described in further detail with reference to the accompanying drawings and specific embodiments.
Fig. 1 is a schematic diagram illustrating a conventional detection of a trojan circuit according to the present embodiment;
fig. 2 is a schematic diagram of a feature selection method provided in this embodiment;
fig. 3 is a schematic diagram of a residual convolutional encoder network according to this embodiment.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The embodiment provides a hardware Trojan horse circuit detection method based on a residual error encoder neural network, which comprises the following steps of:
and S1, acquiring a Verilog file in the circuit design stage, and extracting effective features according to the Verilog file to obtain an effective feature set of the hardware Trojan horse circuit.
Wherein, the valid feature set of the hardware trojan circuit is predefined, in a preferred embodiment, the valid feature set of the hardware trojan circuit is defined, and comprises the following features: the number of input gates, the number of output gates, the maximum distance from the input gates to the output gates, the number of input gates to different gate levels, the number of output gates to different gate levels, and the number of logic gates. The specific introduction is as follows:
1) the number of input gates specifically refers to the number of input gate parameters in the verilog file of each reference data set.
2) The number of output gates specifically refers to the number of output gate parameters in each verilog file of the reference data set.
3) The maximum distance from the input gate to the output gate, specifically, the maximum distance from the input gate to the output gate in each reference data set Verilog file, is a plurality of input gates and output gates, and therefore, the maximum distance is taken, and the implementation is performed according to the above equations (1) and (2).
4) The number of input gates to different gate levels, in particular the input gates, is half the maximum distance from the third step, for example: the maximum distance calculation of the third step is 4, then half is 2, the different gate-level distances of the input gate are 1 and 2, at this time, the number of the input gate level 1 and the number of the input gate level 2 need to be counted, and the implementation is performed according to the formula (3).
5) The number of output gates to different gate stages, in particular the output gate is half the maximum distance from the third step, for example: the maximum distance calculation of the third step is 4, then half is 2, the different gate-level distances of the output gate are 1 and 2, at this time, the number of the output gates with the distance of 1 and the number of the output gates with the distance of 2 need to be counted, and the implementation is performed according to the formula (4).
6) The number of logic gates, specifically the number of logic gate parameters in each reference data set Verilog file, is implemented according to formula (5).
In a preferred embodiment, a language marking method is adopted to extract effective characteristics of a hardware Trojan horse circuit from a Verilog file, and the specific process comprises the following steps:
s11, marking input gates, output gates and other gate levels of Verilog with different colors;
s12, counting the occurrence times of each color;
and S13, calculating the average value of the color occurrence times, and summarizing the gate levels larger than the average value, wherein the summarized characteristic is the effective characteristic of the hardware Trojan horse circuit.
Assuming n input gates and m output gates, the maximum distance calculation from the input gate to the output gate is given by the following equation (1):
max_dis＝max(disij,max_dis) (1)
wherein disijIndicating the distance between the current ith input gate to the jth output gate.
Since the different gates in the circuit are connected, the distance between the input gate and the output gate is increased by 1 for every pass through an AND gate, an OR gate or a NOT gate, so that the distance dis between the ith input gate and the jth output gateijThe calculation formula is shown in the following formula (2):
disij＝disij+gateis norgate1:0 (2)
wherein, the gateway norgate is used for judging whether the current front door is an AND gate or a NOT gate, if so, the distance is added with 1, otherwise, the distance is not changed.
Through the above calculation, the maximum distance from the input gate to the output gate can be obtained.
In order to equalize the distances from different gate levels to the input gate and the output gate, half of the maximum distance is used as the maximum distance from different gate levels to the input gate or to the output gate, and different gate levels refer to the distances from the AND gate, the OR gate, and the NOT gate to the input gate or the output gate, so that the number of input gates to different gate levels is shown in the following formula (3).
Wherein i represents the ith input gate and the jth gate level, and the above formula expresses the total number of the ith input gate to the jth gate level, so that the number of the input gates to different gate levels can be calculated.
Similarly, the calculation formula of the number of output gates to different gate stages is shown in the following formula (4).
The output gate calculation is the same as the input gate calculation.
The number of logic gates is shown in the following formula (5), and the number of logic gates is equal to the sum of the numbers of all logic gates.
logic_gate＝∑gates(5)
And S2, selecting strong correlation characteristics from the effective characteristic set of the hardware Trojan horse circuit by adopting a key characteristic selection method based on the correlation of the effective characteristics to the Trojan horse circuit. The "strongly correlated features" refer to features that have a relatively large influence on the classification or prediction result.
In a preferred embodiment, the key feature selection method comprises a pearson correlation coefficient calculation method and a recursive feature elimination method. The method comprises the following specific steps:
s21, firstly, calculating the correlation between different effective characteristics and the Trojan horse circuit by using the Pearson correlation coefficient, and sequencing to obtain the Pearson correlation result.
Further, using the pearson correlation coefficient to calculate the correlation between different significant features and the Trojan horse circuit includes: firstly, calculating Pearson correlation coefficients of different characteristics in an effective characteristic set and a Trojan circuit; then generating a Pearson correlation matrix by using Python; according to the principle: "correlation coefficient is 1, completely positive correlation; the correlation coefficient is-1, and is completely negative correlated; the larger the absolute value of the correlation coefficient, the stronger the correlation ", and the feature sorting is performed.
And S22, processing the effective feature set of the hardware Trojan horse circuit by using a recursive feature elimination method to obtain a recursive feature elimination method result.
Further, the specific process of processing the valid feature set by using the recursive feature elimination method includes:
1) consideration of previously correlated gate-level features as a feature set for recursive feature elimination
2) The characteristics are sorted by scoring, and the characteristics are sorted by the method that the lower the score is, the better the score is
And S23, taking the intersection of the Pearson correlation result and the recursive feature elimination result as a strong correlation feature.
And S3, inputting the strong correlation characteristics into a residual convolutional encoder network, and identifying the Trojan horse circuit by the residual convolutional encoder network according to the input characteristics.
As shown in fig. 3, the structure of the residual convolutional encoder network includes a combination of a residual neural network structure and an encoder network, wherein the encoder network is an encoder structure of an AutoEncoder, and the encoder network structure is mainly used for acceleration. The residual error neural network structure adopts a basic block structure, two continuous basic block structures are arranged in a residual error convolutional encoder network, and the main function of the basic block structures is to prevent the network degradation problem; and then input to an encoder architecture that employs two convolutional neural networks.
In a preferred embodiment, the basic block structure consists of 4 convolution layers of 3 x 3, and the encoder consists of 1 convolution layer of 2 x 2 and 3 x 3.
In a preferred embodiment, this embodiment first introduces a basic block structure of the residual neural network (corresponding to basic block in fig. 3), then performs dimensionality reduction processing using an encoder, and finally inputs data into a Fully connected layer (full connected) after Pooling through a Max-Pooling layer (Max-Pooling).
As shown in fig. 3, the specific process of identifying the trojan horse circuit by the residual convolutional encoder network according to the input features includes:
s31, using the netlist data (the netlist data refers to the strong correlation feature data extracted in step S2) as the input of the residual convolutional coding neural network, and then using 64 convolutional kernels of 1 × 1, with a step size of 1 and a filling of 0, to obtain a dimension of 64 × 12.
And S32, subsequently, two basic block (basic block) structures are adopted to prevent network degradation, each basic block adopts 64 convolution kernels 3 x 3, the step size is 1, the padding is 1, the output dimension is not changed, and the basic blocks are sequentially input into the encoder structure.
S33, in the encoder, each convolution kernel in the encoder structure is different, the first time is 128 convolution kernels of 2 × 2, the step size is 2, and the padding is 1, resulting in dimension of 128 × 7. The second time is 256 convolution kernels of 3 x 3 with a step size of 2, padded to 1, resulting in a dimension of 256 x 4.
And S34, finally, after pooling through the maximum pooling layer, inputting data into the full-connection layer to obtain a final result predicted through the neural network, wherein the final result is data of 0 or 1, 0 represents a normal circuit, and 1 represents an abnormal circuit, namely a Trojan circuit.
When introducing elements of various embodiments of the present application, the articles "a," "an," "the," and "said" are intended to mean that there are one or more of the elements. The terms "comprising," "including," and "having" are intended to be inclusive and mean that there may be additional elements other than the listed elements.
It should be noted that, as one of ordinary skill in the art would understand, all or part of the processes of the above method embodiments may be implemented by a computer program to instruct related hardware, where the computer program may be stored in a computer readable storage medium, and when executed, the computer program may include the processes of the above method embodiments. The storage medium may be a magnetic disk, an optical disk, a Read-0nly Memory (ROM), a Random Access Memory (RAM), or the like.
The foregoing is directed to embodiments of the present invention and it will be appreciated by those skilled in the art that changes may be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.
Claims (6)
1. A hardware Trojan horse circuit detection method based on a residual error encoder neural network is characterized by comprising the following steps:
s1, acquiring a Verilog file in a circuit design stage, and extracting effective features according to the Verilog file to obtain an effective feature set of the hardware Trojan horse circuit;
s2, selecting strong correlation characteristics from the effective characteristic set of the hardware Trojan horse circuit by adopting a key characteristic selection method based on the correlation of the effective characteristics to the Trojan horse circuit;
and S3, inputting the strong correlation characteristics into a residual convolutional encoder network, and identifying the Trojan horse circuit by the residual convolutional encoder network according to the input characteristics.
2. The method as claimed in claim 1, wherein in step S1, the set of valid features of the hardware trojan circuit is predefined, and the set of valid features of the hardware trojan circuit includes: the number of input gates, the number of output gates, the maximum distance from the input gates to the output gates, the number of input gates to different gate levels, the number of output gates to different gate levels, and the number of logic gates.
3. The method as claimed in claim 1, wherein in step S1, a language markup method is used to extract the effective features of the hardware Trojan horse circuit from the Verilog file, and the specific process includes:
s11, marking input gates, output gates and other gate levels of Verilog with different colors;
s12, counting the occurrence times of each color;
and S13, calculating the average value of the color occurrence times, and summarizing the gate levels larger than the average value, wherein the summarized characteristic is the effective characteristic of the hardware Trojan horse circuit.
4. The method according to claim 1, wherein in step S2, a key feature selection method is used to select a strong correlation feature from an effective feature set of the hardware Trojan horse circuit, and specifically comprises:
s21, firstly, calculating the correlation between different effective characteristics and the Trojan horse circuit by using the Pearson correlation coefficient, and sequencing to obtain a Pearson correlation result;
s22, processing the effective feature set of the hardware Trojan horse circuit by using a recursive feature elimination method to obtain a recursive feature elimination method result;
and S23, arranging the Pearson correlation result and the recursive feature elimination result in the front union as a strong correlation feature.
5. The hardware Trojan horse circuit detection method based on the residual error encoder neural network is characterized in that the structure of the residual error convolutional encoder network comprises a residual error neural network structure and an encoder network, the residual error neural network structure adopts a basic block structure, two basic block structures are continuous in the residual error convolutional encoder network, and the main function is to prevent the network degradation problem; and then input to an encoder architecture that employs two convolutional neural networks.
6. The method as claimed in claim 1, wherein the identifying of the trojan circuit by the residual convolutional encoder network according to the input data specifically comprises:
s31, grid list data with input dimensions of 1 × 12 for the residual convolutional encoder network;
s32, firstly, passing through the convolution layer of 1 × 1, filling with the step size of 1 and 0, and obtaining data with the dimension of 64 × 12;
s33, the data with the dimension of 64 × 12 passes through a basic block (basic block) structure of a residual neural network to obtain the data with the dimension of 64 × 12;
s34, processing by an encoder (encoder) to obtain data with the dimension of 256 × 4;
s35, passing through a maximum pooling layer (max-pool), and obtaining data with the dimension of 256 x 2;
and S36, finally outputting a prediction result through the all-connection layer, wherein if the output prediction result is 1, the circuit is abnormal, and if the output prediction result is 0, the circuit is normal.
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