CN112740633B

CN112740633B - Method and circuit for reducing crest factor for cable television amplifier

Info

Publication number: CN112740633B
Application number: CN201980062088.0A
Authority: CN
Inventors: C·H·迪克; H·赵; H·M·帕雷克; X·陈
Original assignee: Xilinx Inc
Current assignee: Xilinx Inc
Priority date: 2018-09-26
Filing date: 2019-09-10
Publication date: 2024-05-24
Anticipated expiration: 2039-09-10
Also published as: JP2022502907A; EP3857832A1; KR20210063368A; CN112740633A; WO2020068414A1; JP7499758B2

Abstract

A Crest Factor Reduction (CFR) system includes a digital ramp filter coupled to an input of the CFR system. In some embodiments, the digital tilt filter is configured to receive the system input signal and generate a digital tilt filter output signal at a digital tilt filter output. In some examples, the CFR system further includes a CFR module coupled to the digital tilt filter output, wherein the CFR module is configured to receive the digital tilt filter output signal and perform CFR processing on the digital tilt filter output signal to generate a CFR module output signal at the CFR module output. Additionally, the CFR system may further include a digital tilt equalizer coupled to the CFR module output, wherein the digital tilt equalizer is configured to receive the CFR module output signal and generate a system output signal.

Description

Method and circuit for reducing crest factor for cable television amplifier

Technical Field

Examples of the present disclosure relate generally to integrated circuits ("ICs") and, in particular, to embodiments related to crest factor reduction of cable television (CATV) amplifiers.

Background

To meet the demand for higher Data rates for internet, telephony, and video services, the Cable industry is deploying new high Data rate and broadband remote PHY nodes based on the new Cable Data service interface Specification (DOCSIS) 3.1 standard. DOCSIS 3.1 supports 4096 Quadrature Amplitude Modulation (QAM) and uses Orthogonal Frequency Division Multiplexing (OFDM). Thus, the transmitted signal quality requirements of DOCSIS 3.1 are higher than the current standard DOCSIS 3.0. Cable television (CATV) amplifiers may operate in the nonlinear region due to the more complex functions associated with DOCSIS 3.1. The nonlinear effects of CATV amplifiers will greatly degrade the quality of the transmitted signal. In addition, the new components that provide the high data rates and more complex functions of DOCSIS 3.1 themselves consume power. However, since the power supply to each node (e.g., each remote PHY node) is fixed, the power consumption of other components (e.g., CATV amplifiers) should be reduced. Thus, while it is desirable to provide advanced performance of DOCSIS 3.1, it is challenging to provide both improved transmit signal quality and reduced power consumption of other components (e.g., CATV amplifiers).

Accordingly, there is a need for improved methods and circuits for reducing the crest factor of CATV amplifiers.

Disclosure of Invention

In some embodiments according to the present disclosure, a Crest Factor Reduction (CFR) system includes a digital ramp filter (DIGITAL TILT FILTER) coupled to an input of the CFR system. In some embodiments, the digital tilt filter is configured to receive the system input signal and generate a digital tilt filter output signal at a digital tilt filter output. In some examples, the CFR system further includes a CFR module coupled to the digital tilted filter output, wherein the CFR module is configured to receive the digital tilted filter output signal and perform CFR processing on the digital tilted filter output signal to generate a CFR module output signal at the CFR module output. Additionally, the CFR system may include a digital tilt equalizer (DIGITAL TILT equalizer) coupled to the CFR module output, wherein the digital tilt equalizer is configured to receive the CFR module output signal and generate a system output signal.

In some embodiments, the CFR system further comprises a Digital Predistortion (DPD) module coupled to the CFR module output, wherein the DPD module is configured to receive the CFR module output signal and perform DPD processing on the CFR module output signal to generate a DPD module output signal at the DPD module output. In some cases, a digital tilt equalizer is coupled to the DPD module output and the digital tilt equalizer is configured to receive the DPD module output signal and generate a system output signal.

In some embodiments, the system input signal has a first peak-to-average power ratio (PAPR) and the CFR module output signal has a second PAPR that is less than the first PAPR.

In some embodiments, the CFR system further includes a first linear data path coupled to an input of the CFR system and in parallel with the CFR module and the DPD module to generate a first time delay signal. In some examples, the CFR system further includes a first combiner configured to combine the digital tilt equalizer output signal and the first time delay signal to generate a system output signal.

In some embodiments, the CFR system further includes a second linear data path coupled to an input of the CFR system and in parallel with the CFR module to generate a second time delayed signal. For example, the second combiner is configured to combine the CFR module output signal and the second time-delayed signal to generate a first output signal, and the third combiner is configured to combine the first output signal and the DPD module output signal to generate a system output signal.

In some embodiments, the CFR system further comprises a nonlinear data path coupled to the CFR module output, wherein the nonlinear data path comprises a plurality of parallel data path units each coupled to the CFR module output, wherein each of the plurality of parallel data path units is configured to add a different inverse nonlinear component corresponding to the nonlinear component of the amplifier to the CFR module output signal, and wherein the combiner is configured to combine the outputs of each of the plurality of parallel data path units to generate the DPD module output signal.

In some embodiments, a digital-to-analog converter (DAC) is configured to receive a system output signal and generate a DAC output signal, wherein an analog tilt filter is configured to receive the DAC output signal and generate an analog tilt filter output signal, and wherein the digital tilt filter is configured to model the analog tilt filter.

In some embodiments, the digital tilt equalizer is configured to model the inverse of the analog tilt filter.

In some embodiments, the CFR system further comprises a single sideband Hilbert filter (Hilbert filter), wherein the single sideband Hilbert filter input is configured to receive the DPD module output signal and the single sideband Hilbert filter output is coupled to the digital tilt equalizer input.

In some embodiments, the CFR system further comprises an adaptation engine configured to receive feedback data from the amplifier output, wherein based on the feedback data, the adaptation engine is configured to update the configuration of the CFR module.

In some embodiments according to the present disclosure, a Digital Front End (DFE) system is configured to perform Crest Factor Reduction (CFR) processing, and the DFE system includes a digital up-converter (DUC) configured to receive and convert a baseband data input signal to generate a composite signal. In various embodiments, the DFE system further includes a CFR system including a digital tilt filter, a CFR module, and a digital tilt equalizer, wherein the digital tilt filter is configured to receive the composite signal and to generate a digital tilt filter output signal, wherein the CFR module is configured to receive the digital tilt filter output signal and to perform CFR processing on the digital tilt filter output signal to generate a CFR module output signal; wherein the digital tilt equalizer is configured to receive the CFR module output signal and generate a CFR system output signal, and wherein the CFR system output signal is coupled to the amplifier. In some examples, the DFE system further includes an adaptation engine configured to receive feedback data from an output of the amplifier, wherein the adaptation engine is configured to update a configuration of the CFR system based on the feedback data.

In some embodiments, the CFR process is configured to reduce a peak-to-average power ratio (PAPR) of the digital oblique filter output signal.

In some embodiments, the CFR system further comprises a Digital Predistortion (DPD) module comprising a nonlinear data path coupled to the CFR module output, wherein the nonlinear data path comprises a plurality of parallel data path units, each parallel data path unit coupled to the CFR module output, wherein each parallel data path unit of the plurality of parallel data path units is configured to model a different inverse nonlinear component corresponding to the nonlinear component of the amplifier, wherein the combiner is configured to combine the outputs of each data path unit of the plurality of parallel data path units to generate the DPD module output signal, and wherein the digital tilt equalizer is configured to receive the DPD module output signal and generate the CFR system output signal.

In some embodiments, a digital-to-analog converter (DAC) is configured to receive the CFR system output signal and generate a DAC output signal, wherein the analog tilt filter is configured to receive the DAC output signal and generate an analog tilt filter output signal, and wherein the digital tilt filter is configured to model the analog tilt filter.

In some embodiments according to the present disclosure, a method includes receiving an input signal at a digital tilt filter of a Crest Factor Reduction (CFR) system and generating a digital tilt filter output signal at a digital tilt filter output. In various examples, the method further includes performing, at a CFR module of the CFR system, CFR processing on the digital tilted filter output signal to generate a CFR module output signal, wherein the CFR processing is configured to reduce a peak-to-average power ratio (PAPR) of the digital tilted filter output signal. In some examples, the method further includes receiving the CFR module output signal at a digital tilt equalizer of the CFR system and generating a system output signal. In some embodiments, the method further comprises providing the system output signal to an amplifier.

In some embodiments, the method further comprises updating a configuration of the CFR system in response to feedback data received from an output of the amplifier.

In some embodiments, the method further comprises performing DPD processing on the CFR module output signal at a Digital Predistortion (DPD) module of the CFR system to generate a DPD module output signal. In some examples, the method further comprises receiving the DPD module output signal at a digital tilt equalizer of the CFR system and generating a system output signal.

In some embodiments, the DPD module further comprises a nonlinear data path coupled to an output of the CFR module, wherein the nonlinear data path comprises a plurality of parallel data path units, each coupled to the CFR module output, wherein each of the plurality of parallel data path units is configured to model a different inverse nonlinear component corresponding to the nonlinear component of the amplifier, and wherein the combiner is configured to combine the outputs of each of the plurality of parallel data path units to generate the DPD module output signal.

In some embodiments, the method further comprises reducing power consumption of the amplifier in response to providing the system output signal to the amplifier while operating the amplifier in a nonlinear region.

In some embodiments according to the present disclosure, a Digital Predistortion (DPD) system includes an input configured to receive a DPD input signal. In some embodiments, the DPD system further comprises a nonlinear data path coupled to the input, wherein the nonlinear data path comprises a plurality of parallel data path units each coupled to the input, wherein each of the plurality of parallel data path units is configured to add a different inverse nonlinear component corresponding to the nonlinear component of the amplifier to the DPD input signal, and wherein the first combiner is configured to combine the outputs of each of the plurality of parallel data path units to generate the first predistortion signal. In some embodiments, the DPD system further includes a linear data path coupled to the input in parallel with the nonlinear data path to generate a second predistortion signal, and a second combiner configured to combine the first predistortion signal and the second predistortion signal to generate the DPD output signal.

In some embodiments, the plurality of parallel data path elements includes a baseband DPD data path, a video bandwidth DPD data path, a second harmonic DPD data path, and a third harmonic DPD data path.

In some embodiments, the baseband DPD data path is configured to add an inverse nonlinear baseband component to the DPD input signal.

In some embodiments, the video bandwidth DPD data path is configured to add an inverse nonlinear video bandwidth component to the DPD input signal.

In some embodiments, the second harmonic DPD data path is configured to add an inverse second harmonic component to the DPD input signal.

In some embodiments, the third harmonic DPD data path is configured to add an inverse third harmonic component to the DPD input signal.

In some embodiments, the DPD system further comprises a digital tilt filter configured to model the analog tilt filter, wherein the digital tilt filter input is coupled to the input and the digital tilt filter output is coupled to the non-linear data path.

In some embodiments, the DPD system further comprises a digital tilt equalizer configured to model an inverse of the analog tilt filter, wherein the digital tilt equalizer input is configured to receive the first predistortion signal, and the second combiner is configured to combine the digital tilt equalizer output to the second predistortion signal to generate the DPD output signal.

In some embodiments, the DPD system further comprises a single sideband hilbert filter, wherein the single sideband hilbert filter input is configured to receive the first predistortion signal and the single sideband hilbert filter output is coupled to the digital tilt equalizer input.

In some embodiments, the DPD output signal is coupled to an amplifier input to generate an amplified output signal, and the DPD output signal is configured to compensate for multiple nonlinear components of the amplifier.

In some embodiments according to the present disclosure, a Digital Front End (DFE) system configured to perform Digital Predistortion (DPD) processing includes a Digital Up Converter (DUC) configured to receive and convert a baseband data input signal to generate a composite signal. In some embodiments, the DFE system further includes a DPD system configured to receive the composite signal at a DPD input and perform DPD processing on the composite signal, wherein the DPD input is coupled to a plurality of parallel data path units, wherein at least one of the plurality of parallel data path units is configured to add an inverse harmonic component corresponding to a nonlinear harmonic component of the amplifier to the composite signal, wherein the combiner is configured to combine an output of each of the plurality of data path units to generate a DPD output signal, and wherein the DPD output signal is coupled to the amplifier. In some embodiments, the DPD output signal is configured to compensate for nonlinear harmonic components of the amplifier.

In some embodiments, the DUC is configured to perform interpolation processing on the baseband data input signal to generate an interpolated signal, and the DUC is configured to perform mixing processing on the interpolated signal to generate a composite signal.

In some embodiments, the DPD system further comprises a digital tilt filter configured to model the analog tilt filter, wherein the digital tilt filter input is configured to receive the composite signal, and wherein the digital tilt filter output is coupled to the plurality of parallel data path elements.

In some embodiments, the DPD system further comprises a digital tilt equalizer configured to model an inverse of the analog tilt filter, wherein the digital tilt equalizer input is configured to receive a combined output of each of the plurality of data path elements, and wherein the other combiner is configured to combine the digital tilt equalizer outputs into a linear DPD signal to generate the DPD output signal.

In some embodiments according to the present disclosure, a method includes receiving a Digital Predistortion (DPD) input signal at an input of a DPD system. In some embodiments, the method further comprises receiving the DPD input signal at a non-linear data path coupled to an input of the DPD system, wherein the non-linear data path includes a plurality of parallel data path units, wherein each parallel data path unit is coupled to the input. In some embodiments, the method further comprises adding, by each of the plurality of parallel data path units, an inverse nonlinear component corresponding to the nonlinear component of the amplifier to the DPD input signal. In some embodiments, the method further comprises combining, by the first combiner, the output of each of the plurality of parallel data path units to generate the first predistortion signal. In some embodiments, the method further comprises receiving the DPD input signal at a linear data path coupled to the input in parallel with the nonlinear data path to generate a second predistortion signal. In some embodiments, the method further comprises combining, by a second combiner, the first predistortion signal and the second predistortion signal to generate the DPD output signal.

In some embodiments, the method further comprises: adding an inverse nonlinear baseband component to the DPD input signal through a baseband DPD data path; adding an inverse nonlinear video bandwidth component to the DPD input signal over a video bandwidth DPD data path; adding an inverse second harmonic component to the DPD input signal through a second harmonic DPD data path; and adding the inverse third harmonic component to the DPD input signal through the third harmonic DPD data path.

In some embodiments, the method further comprises providing a DPD output signal to the amplifier input to generate an amplified output signal, wherein the DPD output signal is configured to compensate for a plurality of nonlinear components of the amplifier.

In some embodiments, the method further comprises reducing power consumption of the amplifier in response to providing the DPD output signal to the amplifier while operating the amplifier in a non-linear region.

Other aspects and features will become apparent upon review of the following detailed description and the accompanying drawings.

Drawings

Fig. 1 is a block diagram illustrating an exemplary architecture for an IC according to some embodiments of the present disclosure.

Fig. 2 is a schematic diagram of an exemplary cable network according to some embodiments.

Fig. 3 is a schematic diagram of an exemplary Digital Front End (DFE) system according to some embodiments.

Fig. 4A provides a diagram of a Digital Predistortion (DPD) -Crest Factor Reduction (CFR) system in accordance with some embodiments.

Fig. 4B provides an example of a DPD module according to some embodiments.

Fig. 5A and 5B provide exemplary DPD-CFR input spectra and DPD-CFR output spectra, respectively, according to some embodiments.

Fig. 6A provides an exemplary graph showing normalized amplitude of an analog tilt filter output sampled over time and showing the effect of performing CFR processing, according to some embodiments.

Fig. 6B illustrates a power spectrum at the output of the analog tilt filter after performing CFR processing according to some embodiments.

Fig. 7A, 7B, and 7C provide exemplary graphs showing normalized amplitude of CATV amplifier output sampled over time and showing the effect of performing CFR processing, according to some embodiments.

Fig. 8A illustrates a cumulative distribution function (CCDF) plot for a single carrier, showing the effect of performing CFR processing, in accordance with some embodiments.

Fig. 8B illustrates a power spectrum after performing CFR processing and corresponding to the data of fig. 8A, in accordance with some embodiments.

Fig. 9A and 9B provide graphs of CATV amplifier transfer functions showing amplitude-to-amplitude distortion (AM/AM) and showing the effect of performing one or both of DPD processing and CFR processing, in accordance with some embodiments.

Fig. 10A and 10B provide graphs of DPD output stability performance according to some embodiments, showing the effect of performing CFR processing.

Fig. 11 provides a table including Modulation Error Ratio (MER) data for CATV amplifiers, which illustrates the effect of applying corrections provided by DPD-CFR systems to MER data, in accordance with some embodiments.

Fig. 12 is a flow chart illustrating a method of performing crest factor reduction processing and digital predistortion processing in a DPD-CFR system in accordance with some embodiments.

Fig. 13, 14, 15, and 16 illustrate equations, including graphical representations, according to some embodiments, wherein the equations provide a derivation for each nonlinear data path element of fig. 4.

Fig. 17 illustrates a power spectrum of a single carrier, illustrating the nonlinear effects of a CATV amplifier, in accordance with some embodiments.

Fig. 18 illustrates a power spectrum showing the result of applying baseband DPD correction to the power spectrum of fig. 17, according to some embodiments.

Fig. 19 illustrates a power spectrum showing the result of applying a second harmonic DPD correction to the power spectrum of fig. 17, according to some embodiments.

Fig. 20 illustrates a power spectrum showing the result of applying third harmonic DPD correction to the power spectrum of fig. 17, according to some embodiments.

Fig. 21 illustrates a power spectrum showing the results of applying baseband DPD correction and video bandwidth DPD correction simultaneously, according to some embodiments.

Fig. 22 illustrates a power spectrum showing Adjacent Channel Power Ratio (ACPR) correction resulting from the application of correction provided by the DPD system, in accordance with some embodiments.

Fig. 23 provides a table including Modulation Error Ratio (MER) data for a CATV amplifier, which illustrates the effect of applying the correction provided by the DPD system to MER data, in accordance with some embodiments.

Fig. 24 is a flowchart showing a method for performing digital predistortion processing in a DPD system, according to some embodiments.

Detailed Description

Various embodiments are described below with reference to the accompanying drawings, in which exemplary embodiments are shown. The claimed invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Like numbers refer to like elements throughout. Accordingly, similar elements will not be described in detail with respect to each of the drawings. It should also be noted that the drawings are only intended to assist in describing the embodiments. They are not intended as an exhaustive description of the claimed invention or as a limitation on the scope of the claimed invention. Additionally, the illustrated embodiments need not have all of the aspects or advantages shown. Aspects or advantages described in connection with a particular embodiment are not necessarily limited to that embodiment and may be practiced in any other embodiment even if not so shown or explicitly described. These features, functions, and advantages can be achieved independently in various embodiments or may be combined in yet other embodiments.

Before describing the exemplary embodiments schematically illustrated in the several figures, a general description is provided for further understanding.

As noted above, the cable industry is deploying new high data rate and broadband remote PHY nodes based on DOCSIS3.1 standards to meet the demand for higher data rates for internet, telephony, and video services. DOCSIS3.1 supports 4096 (4K) Quadrature Amplitude Modulation (QAM) and uses Orthogonal Frequency Division Multiplexing (OFDM). Thus, the transmitted signal quality requirements of DOCSIS3.1 are higher than those of DOCSIS 3.0 of the current standard. Because of the more complex functions associated with DOCSIS3.1, cable television (CATV) amplifiers may operate in the nonlinear region. The nonlinear effects of CATV amplifiers will greatly degrade the quality of the transmitted signal. In addition, the new components that provide the high data rates and the more complex functions of DOCSIS3.1 themselves consume power. However, since the power supply to each node (e.g., each remote PHY node) is fixed, the power consumption of other components (e.g., CATV amplifiers) should be reduced. Thus, while it is desirable to provide advanced performance of DOCSIS3.1, it is challenging to provide both improved transmit signal quality and reduced power consumption of other components (e.g., CATV amplifiers).

In at least some prior art, a tilt equalizer (tilt filter) with deep attenuation of up to 22dB over the 1.2GHz cable spectrum is implemented in the analog transmission path to compensate for the loss of the coaxial cable (e.g., from CATV amplifier to cable modem). DOCSIS 3.1 waveforms modulated using 4K QAM OFDM show a higher peak-to-average power ratio (PAPR) than the current DOCSIS 3.0 standard. Thus, for the same RMS power output of the CATV amplifier in DOCSIS 3.0, the peaks of the DOCSIS 3.1 waveform will lie in the non-linear region of the CATV amplifier. Therefore, the quality of the transmitted signal may be degraded. Digital Predistortion (DPD) may be used to improve the signal quality of CATV amplifiers, for example, by operating CATV in a more efficient area. DPD has been used in wireless communication technologies where the signal bandwidth is much narrower than for wired communication technologies. Furthermore, in wireless communications, harmonics of the nonlinear effects of the wireless components do not fall within the signal bandwidth. Thus, DPD for wireless communication only needs to model the nonlinear components projected around the baseband frequency. For cable applications, however, harmonics of the nonlinear effects of the CATV amplifier signal may fall within the signal bandwidth. Thus, DPD implementations for cable applications should model the harmonic components of the nonlinear effects of CATV amplifiers. In addition, a tilt equalizer with deep attenuation cannot be implemented in the digital domain, and an implementation of a digital tilt equalizer will degrade the transmission waveform quality of the low frequency carrier due to the limited digital resolution of the digital-to-analog converter (DAC).

In addition, as described above, DOCSIS 3.1 waveforms modulated using 4K QAM OFDM show higher PAPR compared to the current DOCSIS 3.0 standard. Some effects of high PAPR include in-band distortion and out-of-band distortion (e.g., including increased Adjacent Channel Leakage Ratio (ACLR)). Crest Factor Reduction (CFR) may be used to reduce the PAPR of a signal by clipping the signal and allowing additional gain to be obtained at the CFR output. Clipping is performed by deliberately limiting the signal so that the amplitude is limited to a maximum value within a desired range. By using CFR, an amplifier (e.g., CATV amplifier) can be made to operate around its 1dB compression point, thereby improving the efficiency of the CATV amplifier; furthermore, when used in conjunction with DPD, CFR can significantly improve the stability of the DPD (e.g., avoid DPD divergence) and further improve the efficiency of the CATV amplifier. For Integrated Circuit (IC) solutions, it has been found that the CFR and DPD datapaths implemented in Digital Front End (DFE) chips can provide solutions for the high PAPR of DOCSIS 3.1 waveforms, DPD stability and the efficiency of CATV amplifiers, and can be used to model harmonic components of CATV amplifier nonlinear effects and deep attenuation over the transmit spectrum in CATV amplifiers. Accordingly, embodiments of the present disclosure provide improved transmit signal quality, increased CATV amplifier efficiency, and reduced CATV amplifier power consumption.

With the above general understanding in mind, various embodiments of methods and circuits for providing CFR for CATV amplifiers are generally described below. Because one or more of the above-described embodiments are illustrated using a particular type of IC, a detailed description of such ICs is provided below. However, it should be understood that other types of ICs may benefit from one or more of the embodiments described herein.

Programmable logic devices ("PLDs") are well known integrated circuits that can be programmed to perform specified logic functions. One type of PLD, a field programmable gate array ("FPGA"), typically includes an array of programmable tiles (programmable tiles). These programmable tiles may include, for example, input/output blocks ("IOBs"), configurable logic blocks ("CLBs"), dedicated random access memory blocks ("BRAMs"), multipliers, digital signal processing blocks ("DSPs"), processors, clock managers, delay locked loops ("DLLs"), and the like. As used herein, "including" and "comprising" mean including, but not limited to.

Each programmable tile typically includes programmable interconnects and programmable logic. Programmable interconnects typically include many different lengths of interconnect lines interconnected by programmable interconnect points ("PIPs"). Programmable logic uses programmable units to implement user-designed logic, which may include, for example, function generators, registers, arithmetic logic, and the like.

The programmable interconnect and programmable logic can typically be programmed by loading a configuration data stream into internal configuration memory cells that define how the programmable cells are configured. The configuration data may be read from memory (e.g., from an external PROM) or written to the FPGA through an external device. The collective states of the individual memory cells then determine the function of the FPGA.

Another type of PLD is a Complex Programmable Logic Device (CPLD). The CPLD contains two or more "functional blocks" that are connected together and to input/output ("I/O") resources through an interconnection switch matrix. Each functional block of the CPLD includes a two-level AND/OR structure similar to that used in programmable logic arrays ("PLAs") AND programmable array logic ("PAL") devices. In CPLDs, configuration data is typically stored on-chip in non-volatile memory. In some CPLDs, the configuration data is stored on-chip in non-volatile memory and then downloaded into volatile memory as part of an initial configuration (programming) sequence.

Typically, for each of these programmable logic devices ("PLDs"), the function of the device is controlled by configuration data provided to the device for this purpose. The configuration data may be stored in volatile memory (e.g., static memory cells common in FPGAs and some CPLDs), non-volatile memory (e.g., in some CPLDs, such as FLASH memory), or any other type of memory cell.

Other PLDs are programmed by applying a processing layer, such as a metal layer, that programmably interconnects the various cells on the device. These PLDs are known as mask programmable devices. PLDs may also be implemented in other ways (e.g., using fuse or antifuse technology). The terms "PLD" and "programmable logic device" include, but are not limited to, these exemplary devices, as well as devices that are only partially programmable. For example, one type of PLD includes a combination of hard-coded transistor logic and programmable switch structures that programmably interconnect the hard-coded transistor logic.

As described above, advanced FPGAs can include several different types of programmable logic blocks in an array. For example, FIG. 1 shows an exemplary FPGA architecture 100.FPGA architecture 100 includes a number of different programmable tiles including multi-gigabit transceivers ("MGTs") 101, configurable logic blocks ("CLBs") 102, random access memory blocks ("BRAMs") 103, input/output blocks ("IOBs") 104, configuration and clock logic ("CONFIG/CLOCKS") 105, digital signal processing blocks ("DSPs") 106, dedicated input/output blocks ("I/O") 107 (e.g., configuration ports and clock ports), and other programmable logic 108, such as digital clock managers, analog-to-digital converters, system monitoring logic, and the like. Some FPGAs also include a dedicated processor block ("PROC") 110. In some embodiments, FPGA architecture 100 includes an RF data converter subsystem that includes a plurality of radio frequency analog-to-digital converters (RF-ADCs) and a plurality of radio frequency digital-to-analog converters (RF-DACs). In various examples, the RF-ADC and RF-DAC may each be configured for real data, or may be configured in pairs for real and imaginary I/Q data. In at least some examples, FPGA architecture 100 may implement RFSoC devices.

In some FPGAs, each programmable tile can include at least one programmable interconnect unit ("INT") 111 having connections to the inputs and outputs 120 of the programmable logic units within the same tile, as shown in the example included at the top of fig. 1. Each programmable interconnect unit 111 may also include connections to interconnect segments 122 of adjacent programmable interconnect units in the same tile or other tiles. Each programmable interconnect unit 111 may also include connections (not shown) to interconnect segments 124 of the common routing resources between logic blocks. The generic routing resources may include routing channels between logic blocks (not shown) including interconnect segments (e.g., interconnect segment 124) and switch blocks (not shown) for connecting the interconnect segments. The interconnect segments of the generic routing resource (e.g., interconnect segment 124) may span one or more logical blocks. The programmable interconnect unit 111 together with the general routing resources implements a programmable interconnect structure ("programmable interconnect") for the FPGA shown.

In one exemplary embodiment, CLB 102 may include a configurable logic unit ("CLE") 112 that may be programmed to implement user logic, and a single programmable interconnect unit ("INT") 111.BRAM 103 may include a BRAM logic cell ("BRL") 113 in addition to one or more programmable interconnect cells. In general, the number of interconnected cells included in a tile depends on the height of the tile. In the illustrated example, the BRAM tile has the same height as five CLBs, but other numbers (e.g., four) may be used. In addition to an appropriate number of programmable interconnect units, DSP slice 106 may also include DSP logic units ("DSPLs") 114. In addition to one instance of programmable interconnect unit 111, IOB 104 may include two instances of, for example, input/output logic unit ("IOL") 115. It will be clear to one skilled in the art that, for example, the actual I/O pads typically connected to I/O logic cells 115 are generally not limited to the area of input/output logic cells 115.

In the example of fig. 1, regions near the center of the die (shown horizontally) (e.g., formed by regions 105, 107, and 108 shown in fig. 1) may be used for configuration, clock, and other control logic. Columns 109 (shown vertically) or other columns extending from the horizontal region may be used to distribute the clocks and configuration signals across the width of the FPGA.

Some FPGAs utilizing the architecture shown in fig. 1 include additional logic blocks that disrupt the largely regular columnar structure making up the FPGA. The additional logic blocks may be programmable blocks and/or dedicated logic. For example, PROC 110 spans several columns of CLBs and BRAMs. PROC 110 may include various components, which may range from a single microprocessor to a fully programmable processing system including a microprocessor, memory controller, peripheral devices, and the like.

In one aspect, PROC 110 is implemented as a dedicated circuit, e.g., as a hardwired processor, that is manufactured as part of a die that implements programmable circuitry of an IC. PROC 110 may represent a variety of different processor types and/or systems ranging in complexity from a single processor (e.g., a single core capable of executing program code) to an overall processor system having one or more cores, modules, cooperating processors, interfaces, etc.

On the other hand, PROC 110 is omitted from architecture 100 and may be replaced with one or more other variations in the programmable blocks described. Furthermore, such blocks may be used to form a "soft processor" in that the various blocks of programmable circuitry may be used to form a processor of executable program code, like PROC 110.

The phrase "programmable circuit" may refer to programmable circuit elements within an IC, such as the various programmable or configurable circuit blocks or slices described herein, as well as interconnect circuits that selectively couple the various circuit blocks, slices, and/or elements according to configuration data loaded into the IC. For example, the portions shown in fig. 1, such as CLB 102 and BRAM 103, external to PROC 110 may be considered programmable circuits of an IC.

In some embodiments, the functionality and connectivity of the programmable circuit is not established until configuration data is loaded into the IC. A set of configuration data may be used to program programmable circuitry of an IC (e.g., FPGA). In some cases, the configuration data is referred to as a "configuration bitstream". Typically, the programmable circuit will not work or function without first loading the configuration bitstream into the IC. The configuration bitstream effectively implements or instantiates a particular circuit design within the programmable circuit. The circuit design specifies, for example, functional aspects of the programmable circuit blocks and the physical connections between the various programmable circuit blocks.

In some embodiments, a "hard-wired" or "hardened" circuit, i.e., a non-programmable circuit, is fabricated as part of an IC. Unlike programmable circuits, hardwired circuits or circuit blocks are not implemented by loading a configuration bitstream after an IC is manufactured. Hardwired circuitry is generally considered to have, for example, specialized circuit blocks and interconnections that operate without first loading a configuration bitstream into an IC (e.g., PROC 110).

In some cases, the hardwired circuitry may have one or more modes of operation, which may be set or selected based on register settings or values stored in one or more memory cells within the IC. For example, the operation mode may be set by loading a configuration bitstream into the IC. Despite this capability, hard-wired circuitry is not considered programmable circuitry because it is operational and has specific functionality when manufactured as part of an IC.

Fig. 1 is intended to illustrate an exemplary architecture that may be used to implement an IC that includes programmable circuitry (e.g., programmable structures). For example, the number of logic blocks in a row included at the top of FIG. 1, the relative widths of the rows, the number and order of the rows, the types of logic blocks included in the rows, the relative sizes of the logic blocks, and the interconnect/logic implementation are merely exemplary. For example, in an actual IC, wherever a CLB appears, more than one adjacent CLB row is typically included to facilitate efficient implementation of user logic, but the number of adjacent CLB rows varies with the overall size of the IC. Furthermore, the FPGA of fig. 1 illustrates one example of a programmable IC that may employ examples of the interconnect circuitry described herein. The interconnect circuit described herein may be used in other types of programmable ICs, such as CPLDs or any type of programmable IC having a programmable interconnect structure for selectively coupling logic cells.

It should be noted that the ICs that may implement the method and circuit for the CFR of the CATV amplifier are not limited to the exemplary ICs shown in fig. 1, and that ICs having other configurations or other types of ICs may also implement the method and circuit for the CFR of the CATV amplifier.

Referring now to fig. 2, a cable network 200 is shown, the cable network 200 showing signal paths from data fibers (which may include optical fibers, for example) through remote nodes and to end user locations (at premises, for example). Cable network 200 may be part of a hybrid fiber coax network in which data fibers travel from a central headend to remote nodes from which coax cables travel to end users. In some examples, the remote node includes a remote PHY node based on DOCSIS 3.1 standards. In some embodiments, the remote PHY node may include a baseband and Digital Front End (DFE) chip 202, a digital-to-analog converter (DAC) 204, a driver 206 (which may include, for example, an amplifier), an analog tilt filter 208, a power splitter 210, and a CATV amplifier 212. In various examples, baseband and DFE chips 202 may be implemented as a single chip or as separate chips including a baseband processor chip and a separate DFE chip. In some embodiments, for example, DAC 204 may be implemented as an RF DAC or an IF DAC, depending on the input to DAC 204. Further, in some embodiments, the baseband and DFE chips 202 and DAC 204 may be implemented as a single chip (e.g., in RFSoC devices). Further, one or more components of the remote PHY node may be implemented in a programmable logic device, such as the programmable logic device of fig. 1. As shown in fig. 2, the data fiber is connected as an input to the baseband and DFE chip 202, and the output of the baseband and DFE chip 202 is connected as an input to the DAC 204. The power spectrum 214 (no slope) provides one example of the signal shape at the output of the baseband and DFE chip 202. The output of DAC 204 is connected as an input to driver 206 and the output of driver 206 is connected as an input to analog tilt filter 208. For cable applications, the analog tilt filter 208 may be used to change the gain over the signal power spectrum. In other words, the analog tilt filter 208 is used to increase the slope in the signal power level over the power spectrum. The power spectrum 216 shows the slope (e.g., positive slope in this example) in the signal at the output of the analog tilt filter 208 as compared to the power spectrum 214.

In some embodiments, the output of the analog tilt filter 208 is connected as an input to a power divider 210. As shown in fig. 2, the power splitter 210 includes a 1x 4 power splitter having a single input and four outputs. However, in some embodiments, the power splitter 210 may include a 1x 2 power splitter having a single input and two outputs, a cascade of 1x 2 power splitters (e.g., to produce four outputs), or another type of power splitter. In this example, each of the four outputs of the power splitter 210 is connected as an input to the CATV amplifier 212. The output of each CATV amplifier 212 is then coupled to a coaxial cable that is further coupled to a cable modem at an end-user location (e.g., at a house). In at least some embodiments, the cable network 200 implements a "node +0" architecture, meaning that there are no additional CATV amplifiers along the coax path between the remote PHY node and the end-user location (other than the CATV amplifier 212 at the remote PHY node). Fig. 2 also shows a power spectrum 218 showing the coaxial cable loss spectrum (e.g., with a negative slope), a power spectrum 219 showing the output signal of CATV amplifier 212, and a power spectrum 220 showing the power (no slope) of the signal reaching the end-user location. As previously described, the analog tilt filter 208 is used to compensate for coaxial cable losses (e.g., from the CATV amplifier 212 to a cable modem at the end user location).

In at least some existing cable networks, CATV amplifiers operate in a linear region. This means that the degree of nonlinearity at the output of the CATV amplifier is low enough that no further signal processing is required and the signal at the output of the CATV amplifier can be sent directly through the coaxial cable to the cable modem at the end-user location for demodulation and information transmission. However, with the transition to more complex functionality and the advent of additional power consuming components associated with DOCSIS 3.1, and since the power supply to each node (e.g., each remote PHY node) is fixed, it is desirable to reduce the power consumption of other components such as CATV amplifiers. Currently, CATV amplifiers are about 2-3% efficient, so, for example, a CATV amplifier with 20 watts of input power will output about one-half of the watts of output power. For four CATV amplifiers (e.g., as shown in fig. 2), an input power of 100 watts will output an output power of about 2 watts. It is therefore highly desirable to make CATV amplifiers more efficient.

At least one option being explored to make CATV amplifiers more efficient is to operate CATV amplifiers in a more nonlinear region. However, doing so means that the signal at the output of the CATV amplifier may not be directly transmitted over the coaxial cable to the end user location without some additional digital signal processing, as provided in accordance with embodiments of the present disclosure. For example, embodiments disclosed herein add functionality within baseband and DFE chip 202, as discussed in more detail below, such that baseband and DFE chip 202 is able to invert or alter the signal even if the CATV amplifier is operating in the nonlinear region, such that the signal at the output of the CATV amplifier is still linear and can be conveniently demodulated by a cable modem at the end user location. In other words, if the CATV amplifier has a non-linearity "x", the functions within the baseband and DFE chip 202 are configured to add a "1/x" of the inverse non-linearity that will be canceled by the non-linearity "x" of the cable television amplifier. In this way, the signal at the output of the CATV amplifier is clean and linear. In general, the process of pre-adding nonlinearities (e.g., such as adding inverse nonlinearities at baseband and DFE chips 202) is referred to as pre-distortion or predistortion. In the context of baseband and DFE chip 202, predistortion may be referred to as Digital Predistortion (DPD) because the distortion is digitally added. According to various embodiments, DPD processing is performed with knowledge of the type of non-linearity "x" that a CATV amplifier (such as CATV amplifier 212, for example) has, so that DPD processing can add the appropriate inverse non-linearity "1/x". Thus, according to an embodiment of the present disclosure, DPD processing is the first function added within baseband and DFE chip 202.

In addition, a second function added in baseband and DFE chip 202 may include CFR processing. As described above, CFR processing may be used to reduce the PAPR of a signal by clipping the signal and allowing additional gain to be obtained at the CFR output. By employing CFR, the CATV amplifier can be operated closer to its 1dB compression point, thereby improving the efficiency of the CATV amplifier. Furthermore, when combined with DPD processing, CFR processing can be used to significantly improve DPD stability (e.g., avoid DPD divergence) and further increase the efficiency of the CATV amplifier. In various embodiments, DPD processing and CFR processing are performed with knowledge of the signal chain between the baseband and DFE chips 202 and CATV amplifier 212, including any effects and/or distortions introduced by each of the DAC 204, driver 206, and analog tilt filter 208. In various embodiments, the efficiency of the CATV amplifier is improved and the power consumption is reduced by the DPD and CFR processes disclosed herein.

In some embodiments, the functions within baseband and DFE chip 202 (e.g., including DPD processing and CFR processing) may be implemented largely as DFE functions, with the baseband output signal provided as an input to the DFE chip. As such, referring now to fig. 3, illustrated therein is a DFE system 300 that provides a DFE design configured to perform one or more aspects of the present disclosure. In some embodiments, DFE system 300 includes digital up-converter (DUC) 302. In various examples, DUC 302 is to convert one or more data channels from baseband to passband signals, where the passband signals comprise modulated carriers at one or more specified radio frequencies or groups of intermediate frequencies (RF or IF). For example, DUC 302 achieves this by performing interpolation (e.g., increasing the sampling rate), filtering (e.g., providing spectral shaping and rejection of the interpolated image), and mixing (e.g., shifting the signal spectrum to a desired carrier frequency). Typically, the sampling rate at the input of DUC 302 is low (e.g., the symbol rate of a digital communication system), while the sampling rate at the output is much higher (e.g., the input sampling rate to the DAC), which converts the digital samples to analog waveforms for further analog processing and frequency conversion.

As shown in the example of fig. 3, the baseband data input is provided to DUC 302. The baseband data input includes a plurality of different carriers denoted s ₁(n)、s₂(n)、s₃(n)、s₄(n)、s₅ (n) and s ₆ (n), respectively. In some embodiments, the sampling rate of the baseband data input is approximately 204.8MHz, corresponding to the OFDM symbol clock. For example, DUC 302 generates a plurality of different carriers (e.g., from baseband data inputs) by initially performing interpolation of the baseband data inputs, in this example to increase the sampling rate eight times, and thereby transition from a first clock domain (e.g., 204.8MHz clock domain) to a second clock domain (e.g., 1638.4MHz clock domain). After the interpolation process, each of the plurality of different carriers is mixed with a signal from a Numerically Controlled Oscillator (NCO), each NCO having a different frequency, to shift the frequency of each of the plurality of different carriers to a desired carrier frequency. For example, carrier s ₁ (n) is mixed with a first NCO (NCO 1) having a first frequency, carrier s ₂ (n) is mixed with a second NCO (NCO 2) having a second frequency, carrier s ₃ (n) is mixed with a third NCO (NCO 3) having a third frequency, carrier s ₄ (n) is mixed with a fourth NCO (NCO 4) having a fourth frequency, carrier s ₅ (n) is mixed with a fifth NCO (NCO 5) having a fifth frequency, and carrier s ₆ (n) is mixed with a sixth NCO (NCO 6) having a sixth frequency. After the mixing process, each of the plurality of different carriers is combined to form a composite signal c (n). Thus, the composite signal c (n) includes each of a plurality of different carriers mixed at different frequencies. In some embodiments, and as a result of the mixing process, the composite signal c (n) may appear substantially the same as the signal shown in fig. 5A, with each of the plurality of different carriers arranged side-by-side in frequency. In some cases, after the composite signal c (n) is generated, another interpolation process may optionally be performed, which in the example of fig. 3 may be used to increase the sampling rate of the composite signal c (n) by a factor of two, thereby transitioning from the second clock domain (e.g., 1638.4MHz clock domain) to the third clock domain (e.g., 3276.8MHz clock domain). After signal processing by DUC 302, composite signal c (n) is provided as an input to DPD-CFR system 304, as will be described in more detail below. In some embodiments, the output of DPD-CFR system 304 may undergo complex-to-real signal conversion 306, and the output of complex-to-real signal conversion 306 is provided as an input to a DAC (e.g., may be DAC 204 of fig. 2). In addition, one or more components of DFE system 300 can be implemented in a programmable logic device, such as the programmable logic device of fig. 1.

As previously discussed, DPD and CFR processing and thus DPD-CFR system 304 functions with the type of nonlinearity "x" that the CATV amplifier is known to have and with the signal chain between the baseband and DFE chip 202 and CATV amplifier 212 known so that DPD-CFR system 304 can effectively implement the appropriate DPD and CFR processing (e.g., including adding the appropriate inverse nonlinearity "1/x" and reducing the PAPR of the signal). For example, the DPD-CFR system 304 may be used to model CATV amplifiers (e.g., including nonlinear effects and signal chains). As such, the model provided by the DPD-CFR system 304 may be generated and/or updated based on the feedback data 308, wherein the feedback data 308 may include the output signals of the CATV amplifier (e.g., the CATV amplifier 212). In some embodiments, feedback data 308 is processed by an analog-to-digital converter (ADC) 310 and provided as digital feedback data 311 to DPD/CFR adaptation engine 312. In various examples, based on digital feedback data 311, DPD/CFR adaptation engine 312 updates DPD-CFR system 304 so that DPD-CFR system 304 may adapt to the run-time behavior of the CATV amplifier. More specifically, in some embodiments, DPD/CFR adaptation engine 312 may determine a configuration of filter coefficients or other elements within DPD-CFR system 304, and may generally configure the CFR and DPD modules within DPD-CFR system 304, as discussed below. Thus, by continually monitoring and updating the model provided by DPD-CFR system 304 (e.g., via feedback data 308 and DPD/CFR adaptation engine 312), optimal DPD and CFR processing may be achieved. For example, aspects of monitoring and updating the model (e.g., functions such as DPD/CFR adaptation engine 312) may be implemented as software stored in memory (e.g., within BRAM 103 or within another on-chip memory location) and executed by one or more on-chip processors (e.g., PROC 110). Note that in some embodiments, baseband and DFE chips 202, DAC 204, and ADC 310 may be implemented as a single chip (e.g., in RFSoC devices). The examples of monitoring and updating the model provided above are not meant to be limiting in any way, and it will be appreciated that although other methods are possible, embodiments of the present disclosure are not limited by any examples provided.

Referring now to fig. 4A, there is shown a more detailed view of a DPD-CFR system 304 that is used to implement aspects of the present disclosure. As shown, DPD-CFR system 304 may include a digital tilt filter 402, a CFR module 404, a DPD module 406, a single sideband hilbert filter 412, and a digital tilt equalizer 414. Note that one or more components of DPD-CFR system 304 may be implemented in a programmable logic device, such as the programmable logic device of fig. 1.

Still referring to fig. 4A, the functionality of DPD-CFR system 304 is described in more detail. For example, in some embodiments, an input signal x (n), which may include the composite signal c (n) discussed above, is provided to the digital tilt filter 402. In various cases, the digital tilt filter 402 may be used to model the analog tilt filter 208 (fig. 2). Thus, as an example, the output of digital tilt filter 402 may be similar to the output of analog tilt filter 208. In some embodiments, the output of digital tilt filter 402 is labeled asIs provided as an input to the CFR module 404. In various embodiments, the CFR module 404 may perform CFR processing to reduce the incoming signal (e.g., the output of the digital tilt filter 402,/>) Is a PAPR of (2). Although the present embodiment is not limited to any particular CFR technique used by CFR module 404, exemplary CFR techniques may include: adaptive baseband, intermediate Frequency (IF) clipping and filtering, peak window, or other suitable techniques. After CFR processing, CFR module 404 provides DPD module 406 with a label/>Is provided. As shown, the output of digital tilt filter 402Also provided along data path 421, in which a delay is introduced to the signal/>(E.g., at block 423). For example, the output/>, of the CFR module 404Further along data path 427, then combiner 425 is used to combine the outputs/>, of CFR module 404And delayed signal/>Generating a signal

In some embodiments, DPD module 406 is used to model the inverse baseband, video, and harmonic components of the CATV amplifier and add them to the incoming signalIs a kind of medium. Referring to fig. 4B, a more detailed view of DPD module 406 is shown. As shown, the output of CFR module 404/>Is provided as an input to DPD module 406 which includes a non-linear data path 405. In various embodiments, the non-linear data path 405 includes a plurality of different parallel data path elements including a video bandwidth DPD data path 408, a baseband DPD data path 409, a second harmonic DPD data path 410, and a third harmonic DPD data path 411. Typically, the nonlinear data path 405 is used to model the inverse nonlinear behavior of the CATV amplifier and add it to the input signal. More specifically, each different parallel data path element of the nonlinear data path 405 is used to model and add different aspects of the inverse nonlinear behavior of the CATV amplifier to the input signal (e.g., output/>, of the CFR module 404). For example, video bandwidth DPD data path 408 may model and add an inverse nonlinear video bandwidth component, baseband DPD data path 409 may model and add an inverse nonlinear baseband component, second harmonic DPD data path 410 may model and add an inverse second harmonic component, and third harmonic DPD data path 411 may model and add an inverse third harmonic component. As shown, the outputs of each of video bandwidth DPD data path 408, baseband DPD data path 409, second harmonic DPD data path 410, and third harmonic DPD data path 411 are combined together to provide a composite signal x' (n) that models the baseband, video, and harmonic components of the CATV amplifier. /(I)

Returning to fig. 4A, the output of the nonlinear data path 405 (e.g., composite signal x' (n)) and the signal are combined by a combiner 429The combination is performed to produce the signal x "(n). Thereafter, the signal x "(n) is provided as an input to the single sideband hilbert filter 412, which may be used to further modulate the signal x' (n), and the output of the single sideband hilbert filter 412 is provided as an input to the digital tilt equalizer 414. As an example, digital tilt equalizer 414 may be used to model the inverse of analog tilt filter 208 (fig. 2) and add to the incoming signal. Thus, as an example, the output of the digital tilt equalizer 414 may not be affected (e.g., or may cancel the effects of) the analog tilt filter 208. As shown in fig. 4A, in some embodiments, the input signal x (n) also travels along path 416, where path 416 is a linear data path. In some examples, data path 416 may introduce only a time delay in input signal x (n) (e.g., at block 417). In addition, the input signal x (n) transmitted along the data path 416 bypasses the digital tilt filter 402, the CFR module 404, the DPD module 406, the single sideband hilbert filter 412, and the digital tilt equalizer 414. In this way, the quality of the signal modulation of the input signal x (n) transmitted along the data path 416 will remain unaffected by the other elements of the DPD-CFR system 304. In addition, as shown in fig. 4A, the output of the digital tilt equalizer 414 and the time-delayed input signal x (n) 419 are combined by a combiner 431 to provide an output signal z (n). Referring to fig. 2, 3 and 4a, the output z (n) of dpd-CFR system 304 may be further processed by RF DAC 204 and analog tilt filter 208 to generate signal y (n). For example, the signal y (n) may be calculated as:

Where atf=analog tilt filter, dte=digital tilt equalizer, symbol '×' is used to represent mathematical convolution operations, and dte×atf=1 (unified transfer function).

Referring to fig. 5A, an exemplary input spectrum 502 is provided. In some embodiments, the input signal x (n) (fig. 4A) may include an input spectrum 502. As described above, the input spectrum 502 may include (e.g., by DUC 302) each of a plurality of different carriers mixed at different frequencies, as previously described, where each of the plurality of different carriers is arranged side-by-side over a full bandwidth frequency of about 66MHz to about 1218 MHz. Referring to fig. 5B, an exemplary output spectrum 504 is provided. In some embodiments, the output signal z (n) (fig. 4A) may include the output spectrum 504. As shown in fig. 5B, the output spectrum 504 includes one or more nonlinear components 506 that have been added to the signal by the DPD-CFR system 304. As a result of the processing performed by the DPD-CFR system 304, CATV amplifier efficiency and signal quality are improved and power consumption is reduced.

Referring now to fig. 6A, 6B, 7A, 7B, 7C, 8A, 8B, 9A, 9B, 10A, 10B and 11, a plurality of data are illustrated that show a plurality of data that demonstrate at least some of the benefits and advantages of various embodiments of the present disclosure. Referring first to fig. 6A, a graph 602 is shown that illustrates normalized amplitude of a tilt filter output (e.g., analog tilt filter 208) sampled over time. Graph 602 includes a first data set 604 that does not perform CFR processing. In this way, the first data set 604 exhibits a large peak (e.g., greater than about 0.78), which may result in more nonlinearities in the CATV amplifier. Graph 602 also includes a second data set 606 that performs CFR processing that shows reduced peak amplitude (e.g., less than about 0.78). Thus, the reduced peak provided by the CFR process results in an increase in the efficiency of the CATV amplifier. Further, CFR processing may be performed without sacrificing Modulation Error Rate (MER) performance. Fig. 6B provides a graph 608 that illustrates a power spectrum 610 (e.g., at the output of the analog tilt filter 208) for which CFR processing has been performed, illustrating the benefits of reduced peak amplitude provided by CFR processing. It should be noted that the data shown in fig. 6A and 6B includes analog data, wherein the analog tilt filter 208 has been replaced with a digital model for analog purposes.

Referring to fig. 7A, 7B and 7C, curves 702, 708, 714 are shown therein that illustrate normalized amplitude of an amplifier output (e.g., CATV amplifier 212) sampled over time. In general, the data of the graphs 702, 708, 714 provide verification of the effectiveness of the CFR process and may include a snapshot of feedback data (e.g., such as feedback data 308). As described above, such feedback data may include the output signal of the CATV amplifier that the DPD/CFR adaptation engine 312 may use to update the model within the DPD-CFR system 304 so that the DPD-CFR system 304 may adapt to the behavior of the CATV amplifier when operating. In some cases, the data of the curves 702, 708, 714 may provide a snapshot of the feedback data at the different CATV amplifiers in order to view and adapt the system in real-time (e.g., via the DPD-CFR system 304) to provide consistency between the different CATV amplifiers. Alternatively, in some examples, the data of the curves 702, 708, 714 may provide a snapshot of the feedback data at the particular CATV amplifier at different time windows in order to observe the performance of the particular CATV amplifier over time. Referring now to fig. 7A, a graph 702 includes a first data set that does not perform CFR processing, includes peaks 704 (e.g., having an amplitude greater than about 0.78), and may indicate more nonlinearities in a CATV amplifier. Graph 702 also includes a second data set 706 in which CFR processing is performed, which shows a reduced peak amplitude (e.g., less than about 0.78). Similarly, curve 708 (fig. 7B) and curve 714 (fig. 7C) show peaks 710, 716 of a data set in which CFR processing was not performed, and data sets 712, 718 in which CFR processing was performed. As previously described, the reduced peak provided by the CFR process results in an increase in the efficiency of the CATV amplifier.

Referring now to fig. 8A, there is shown a cumulative distribution function (CCDF) curve 802 for a single carrier at 1122MHz, which shows a first CCDF curve 804 that does not perform CFR processing and a second CCDF curve 806 that results from performing CFR processing. The CCDF curve is used to show the time that a signal spends at or above a given power level, where the power level is expressed in dB relative to the average signal power (e.g., crest factor). In other words, the CCDF curve is used to show the probability that the signal is equal to or higher than a given power level. Referring to fig. 8a, the x-axis shows dB values above average signal power (e.g., crest factor), and the y-axis shows the percentage of time that the signal spends at or above the power level specified by the x-axis. The second CCDF curve 806 (with CFR) exhibits a crest factor reduction of about 2dB compared to the first CCDF curve 804 (without CFR). As a result, CATV amplifiers are expected to provide more consistent and efficient performance. Fig. 8B provides a graph 808 showing a power spectrum 810 for which CFR processing has been performed, corresponding to the second CCDF curve 806 (with CFR), wherein the crest factor has been reduced by CFR processing.

Referring to fig. 9A and 9B, curves 902, 908 of CATV amplifier transfer functions are shown, which illustrate amplitude-to-amplitude distortion (AM/AM) for gain compression or expansion of a measurement signal. In other words, when the CATV amplifier gain is no longer constant with the input power (e.g., when the output power is no longer linearly related to the input power), the nonlinearity of the AM/AM distortion will increase. In this example, graph 902 (fig. 9A) provides data in which CFR processing is not performed, while graph 908 (fig. 9B) provides data in which CFR processing is performed. Further, the graph 902 includes a first curve 904 on which DPD processing is not performed and a second curve 906 on which DPD processing is performed. Referring to the first curve 904, it can be seen that a greater input power results in an increase in compression of the output power (e.g., evidence of a non-linear increase in the CATV amplifier). Using DPD processing (without CFR), the second curve 906 shows that the CATV amplifier nonlinearity can be substantially corrected and signal compression reduced. The graph 908 also includes a first curve 910 for which DPD processing is not performed and a second curve 912 for which DPD processing is performed. By performing CFR processing and reducing PAPR (for the data shown in curve 908), the normalized input power is limited to about 0.8. Referring to the first curve 910 (no DPD), there is relatively less signal compression, resulting in higher control and efficiency of the CATV amplifier. In this example, using DPD processing (with CFR), the second curve 912 shows less improvement compared to the first curve 910 because by limiting the input power (through CFR processing), the nonlinearity of the DPD processing is less corrected.

Fig. 10A and 10B provide exemplary DPD performance (e.g., DPD output stability performance) with and without CFR processing. Fig. 10A includes a graph 1002, the graph 1002 providing data in which CFR processing is not performed. Fig. 10B includes a graph 1008, the graph 1008 providing data for performing CFR processing. Further, plot 1002 (without CFR) includes a first plot 1004 representing a DPD input signal and a second plot 1006 representing a DPD output signal. In this example, if there is no CFR processing, the DPD output signal (1006) is unstable and begins to diverge beyond the DPD output signal range of approximately 2. As described above, a larger input power results in an increased compression in output power, giving the CATV amplifier more nonlinearity. To avoid CATV amplifiers operating in such high power regions, CFR processing may be performed. For example, graph 1008 (with CFR) includes a first curve 1010 representing a DPD input signal and a second curve 1012 representing a DPD output signal. In this example, the DPD output signal (1012) is stable and does not diverge because CFR processing is performed. For the data of curve 1008, a CFR of 1.3dB is applied. However, in various embodiments, the amount of CFR applied may be adjusted according to the needs of a particular CATV amplifier or a particular installation/deployment. Additionally, while the present disclosure has described the advantages of DPD and CFR, it should be understood that various embodiments may employ one or both of DPD and CFR processing. However, in at least some examples, by using both DPD processing and CFR processing for a given deployment, maximum CATV amplifier efficiency can be achieved while also avoiding DPD divergence.

Referring to fig. 11, a table is shown that includes Modulation Error Ratio (MER) data for a CATV amplifier that shows the effect of applying the correction provided by DPD-CFR system 304 to MER data. For example, an MER is a metric used to quantify the performance of a digital radio (or digital TV) transmitter or receiver in a communication system using digital modulation (e.g., QAM). For the example of fig. 11, the CATV amplifier module under test may operate at v=34V. To compare MER data to the cable industry specification (mer=41 db,4kqam,76.8db mv/75Ω), the CATV amplifier was tested using six carriers, where the first carrier was a 4K QAM signal having a carrier frequency of 204MHz, the second carrier was a 4K QAM signal having a carrier frequency of 396MHz, the third carrier was a 4K QAM signal having a carrier frequency of 588MHz, the fourth carrier was a 4K QAM signal having a carrier frequency of 786MHz, the fifth carrier was a 4K QAM signal having a carrier frequency of 930MHz, and the sixth carrier was a 4K QAM signal having a carrier frequency of 1122 MHz. In the first test 1102, with the CATV amplifier operating at a bias current of 440mA and without DPD or CFR correction, none of the tested carriers met the mer=41 dB indicator. In the second test 1104, the first carrier does not meet the mer=41 dB indicator with the CATV amplifier operating at a bias current of 440mA with DPD correction but without CFR correction. Further, in the second test 1104, DPD stability is reduced and DPD diverges. In a third test 1106, with the CATV amplifier operating at a bias current of 440mA and DPD and CFR corrections applied, all carriers tested met the mer=41 dB indicator and DPD dispersion was avoided. It should also be noted that by operating the CATV amplifiers at a bias current of 440mA (as compared to some applications that operate CATV amplifiers at a bias current of 530 mA), the power consumption of each amplifier can be reduced by about 3 watts while maintaining MERs.

Referring now to fig. 12, a method 1200 for performing crest factor reduction processing and digital predistortion processing in a DPD-CFR system is illustrated in accordance with various embodiments. The method 1200 begins at block 1202, where an input signal is received at an input of a DPD-CFR system, such as the DPD-CFR system 304 of fig. 4A. As described above, in some embodiments, the input signal may include an input signal x (n) (fig. 4A), which may also include a composite signal c (n) generated by DUC 302 (fig. 3). In some examples, method 1200 proceeds to block 1204, where at a CFR module of the DPD-CFR system, CFR processing is performed on the input signal to generate a first output signal. For example, CFR processing may be performed by CFR module 404 (fig. 4A). In various cases, CFR processing is performed in order to reduce the peak-to-average power ratio (PAPR) of an input signal. In some embodiments, the input signal includes a flag asAnd the first output signal comprises the signal labeled/> (fig. 4A)Is shown (fig. 4A). The method 1200 proceeds to block 1206, where DPD processing is performed on the first output signal at a DPD module of the DPD-CFR system to generate a DPD-CFR output signal. In some embodiments, the DPD module includes a nonlinear data path coupled to the CFR module output. In addition, the non-linear data path of the DPD module may include the non-linear data path 406 of fig. 4B. Thus, the non-linear data path may comprise a plurality of parallel data path elements. In some examples, the plurality of parallel data path elements includes a video bandwidth DPD data path 404, a baseband DPD data path 406, a second harmonic DPD data path 408, and a third harmonic DPD data path 410. In some examples, each different parallel data path element may be used to add a different aspect of the inverse nonlinear behavior of the CATV amplifier to the input signal. In some embodiments, the combiner combines the outputs of each of the plurality of parallel data path units to generate a composite signal x '(n) (fig. 4B), wherein the composite signal x' (n) models baseband, video, and harmonic components of the CATV amplifier. In various embodiments, the method 1200 proceeds to block 1208, where the DPD-CFR output signal is provided to a CATV amplifier (e.g., such as the CATV amplifier 212 of fig. 2). According to an embodiment of the present disclosure, the DPD-CFR output signal is configured to reduce the PAPR of the signal and compensate for multiple nonlinear components of the CATV amplifier. The method 1200 may then proceed to block 1210, where the configuration of the DPD-CFR system may be updated using feedback data (e.g., feedback data 308 of fig. 3) received from the output of the CATV amplifier. It is to be appreciated that additional method steps may be implemented before, during, and after the method 1200, and that some of the method steps described above may be replaced or eliminated in accordance with various embodiments of the method 1200 without departing from the scope of the invention.

It should be noted that the various configurations (e.g., components of cable network 200, DFE system 300, and DPD-CFR system 304 in fig. 4B, the number of parallel data path elements, and other features and components shown in the figures) are merely exemplary and are not intended to limit what is specifically recited in the appended claims. Those skilled in the art will appreciate that other configurations may be used. Additionally, while an exemplary cable network 200 is shown, the DPD-CFR system disclosed herein may be used in other communication systems, for example, where other communication systems deploy amplifiers that exhibit detrimental nonlinear behavior.

As noted above, the cable industry is deploying new high data rate and broadband remote PHY nodes based on DOCSIS3.1 standards to meet the demand for higher data rates for internet, telephony, and video services. DOCSIS3.1 supports 4096 (4K) Quadrature Amplitude Modulation (QAM) and uses Orthogonal Frequency Division Multiplexing (OFDM). Thus, the transmitted signal quality requirements of DOCSIS3.1 are higher than the current standard DOCSIS 3.0. Because of the more complex functions associated with DOCSIS3.1, cable television (CATV) amplifiers may operate in a nonlinear region. The nonlinear effects of CATV amplifiers will greatly degrade the quality of the transmitted signal. In addition, the new components that provide the high data rates and the more complex functions of DOCSIS3.1 themselves consume power. However, since the power supply to each node (e.g., each remote PHY node) is fixed, the power consumption of other components (e.g., CATV amplifiers) should be reduced. Thus, while it is desirable to provide advanced performance of DOCSIS3.1, it is challenging to provide both improved transmit signal quality and reduced power consumption of other components (e.g., CATV amplifiers).

In at least some prior art, a tilt equalizer (tilt filter) with deep attenuation of up to 22dB over the 1.2GHz cable spectrum is implemented in the analog transmission path to compensate for the loss of the coaxial cable (e.g., from CATV amplifier to cable modem). DOCSIS 3.1 waveforms modulated using 4K QAM OFDM show a higher peak-to-average power ratio (PAPR) than the current DOCSIS 3.0 standard. Thus, for the same RMS power output of the CATV amplifier in DOCSIS 3.0, the peaks of the DOCSIS 3.1 waveform will lie in the non-linear region of the CATV amplifier. Therefore, the quality of the transmitted signal may be degraded. Digital Predistortion (DPD) may be used to improve the signal quality of CATV amplifiers, for example, by operating CATV in a more efficient area. DPD has been used in wireless communication technologies where the signal bandwidth is much narrower than for wired communication technologies. Furthermore, in wireless communications, harmonics of the nonlinear effects of the wireless components do not fall within the signal bandwidth. Thus, DPD for wireless communication only needs to model the nonlinear components projected around the baseband frequency. For cable applications, however, harmonics of the nonlinear effects of the CATV amplifier signal may fall within the signal bandwidth. Thus, DPD implementations for cable applications should model the harmonic components of the nonlinear effects of CATV amplifiers. In addition, a tilt equalizer with deep attenuation cannot be implemented in the digital domain, and an implementation of a digital tilt equalizer will degrade the transmission waveform quality of the low frequency carrier due to the limited digital resolution of the digital-to-analog converter (DAC). For Integrated Circuit (IC) solutions, it has been found that DPD data paths implemented in Digital Front End (DFE) chips can provide a solution to model harmonic components of the nonlinear effects of CATV amplifiers and the depth attenuation over the transmit spectrum in CATV amplifiers. Accordingly, embodiments of the present disclosure provide improved transmit signal quality and reduced power consumption of CATV amplifiers.

With the above general understanding in mind, various embodiments of methods and circuits for predistortion of CATV amplifiers are generally described below. Because one or more of the above-described embodiments are illustrated using a particular type of IC, a detailed description of such ICs is provided below. However, it should be understood that other types of ICs may benefit from one or more of the embodiments described herein.

Programmable logic devices ("PLDs") are well known integrated circuits that can be programmed to perform specified logic functions. One type of PLD, a field programmable gate array ("FPGA"), typically includes an array of programmable tiles. These programmable tiles may include, for example, input/output blocks ("IOBs"), configurable logic blocks ("CLBs"), dedicated random access memory blocks ("BRAMs"), multipliers, digital signal processing blocks ("DSPs"), processors, clock managers, delay locked loops ("DLLs"), and the like. As used herein, "including" and "comprising" mean including, but not limited to.

As noted above, fig. 1 is intended to illustrate an exemplary architecture that may be used to implement an IC that includes programmable circuitry (e.g., programmable structures). For example, the number of logic blocks in a row included at the top of FIG. 1, the relative widths of the rows, the number and order of the rows, the types of logic blocks included in the rows, the relative sizes of the logic blocks, and the interconnect/logic implementation are merely exemplary. For example, in an actual IC, wherever a CLB appears, more than one adjacent CLB row is typically included to facilitate efficient implementation of user logic, but the number of adjacent CLB rows varies with the overall size of the IC. Furthermore, the FPGA of fig. 1 illustrates one example of a programmable IC that may employ examples of the interconnect circuitry described herein. The interconnect circuit described herein may be used in other types of programmable ICs, such as CPLDs or any type of programmable IC having a programmable interconnect structure for selectively coupling logic cells.

Referring now to fig. 2, a cable network 200 is shown, the cable network 200 showing signal paths from data fibers (which may include optical fibers, for example) through remote nodes and to end user locations (at premises, for example). Cable network 200 may be part of a hybrid fiber coax network in which data fibers travel from a central headend to remote nodes from which coax cables travel to end users. In some examples, the remote node includes a remote PHY node based on DOCSIS 3.1 standards. In some embodiments, the remote PHY node may include a baseband and Digital Front End (DFE) chip 202, a digital-to-analog converter (DAC) 204, a driver 206 (which may include, for example, an amplifier), an analog tilt filter 208, a power splitter 210, and a CATV amplifier 212. In various examples, baseband and DFE chips 202 may be implemented as a single chip or as separate chips including a baseband processor chip and a separate DFE chip. In some embodiments, for example, DAC 204 may be implemented as an RF DAC or an IF DAC, depending on the input to DAC 204. Further, in some embodiments, the baseband and DFE chips 202 and DAC 204 may be implemented as a single chip (e.g., in RFSoC devices). Further, one or more components of the remote PHY node may be implemented in a programmable logic device, such as the programmable logic device of fig. 1. As shown in fig. 2, the data fiber is connected as an input to the baseband and DFE chip 202, and the output of the baseband and DFE chip 202 is connected as an input to the DAC 204. The power spectrum 214 (no slope) provides one example of the signal shape at baseband and the output of the DFE chip 202. The output of DAC 204 is connected as an input to driver 206 and the output of driver 206 is connected as an input to analog tilt filter 208. For cable applications, the analog tilt filter 208 may be used to change the gain over the signal power spectrum. In other words, the analog tilt filter 208 is used to increase the slope in the signal power level over the power spectrum. The power spectrum 216 shows the slope (e.g., positive slope in this example) in the signal at the output of the analog tilt filter 208 as compared to the power spectrum 214.

At least one option being explored to make CATV amplifiers more efficient is to operate CATV amplifiers in a more nonlinear region. However, doing so means that the signal at the output of the CATV amplifier may not be directly transmitted over the coaxial cable to the end user location without some additional digital signal processing, as provided in accordance with embodiments of the present disclosure. For example, embodiments disclosed herein add functionality within baseband and DFE chip 202, as discussed in more detail below, such that baseband and DFE chip 202 is able to invert or alter the signal even if the CATV amplifier is operating in the nonlinear region, such that the signal at the output of the CATV amplifier is still linear and can be conveniently demodulated by a cable modem at the end user location. In other words, if the CATV amplifier has a non-linearity "x", the functions within the baseband and DFE chip 202 are configured to add a "1/x" of the inverse non-linearity that will be canceled by the non-linearity "x" of the cable television amplifier. In this way, the signal at the output of the CATV amplifier is clean and linear. In general, the process of pre-adding nonlinearities (e.g., such as adding inverse nonlinearities at baseband and DFE chips 202) is referred to as pre-distortion or predistortion. In the context of baseband and DFE chip 202, predistortion may be referred to as Digital Predistortion (DPD) because the distortion is digitally added. According to various embodiments, DPD processing is performed with knowledge of the type of non-linearity "x" that a CATV amplifier (such as CATV amplifier 212, for example) has, so that DPD processing can add the appropriate inverse non-linearity "1/x". Further, DPD processing is performed with knowledge of the baseband and signal chain between the DFE chip 202 and CATV amplifier 212, including any effects and/or distortions introduced by each of the DAC 204, driver 206, and analog tilt filter 208. In various embodiments, CATV amplifier efficiency is improved and power consumption is reduced by DPD processing as disclosed herein.

In some embodiments, the functions within baseband and DFE chip 202 (configured to add inverse nonlinearities) may be largely implemented as DFE functions, with the baseband output signal provided as an input to the DFE chip. As such, referring now to fig. 3, illustrated therein is a DFE system 300 that provides a DFE design configured to perform one or more aspects of the present disclosure. In some embodiments, DFE system 300 includes digital up-converter (DUC) 302. In various examples, DUC 302 is to convert one or more data channels from baseband to passband signals, where the passband signals comprise modulated carriers at one or more specified radio frequencies or groups of intermediate frequencies (RF or IF). For example, DUC 302 achieves this by performing interpolation (e.g., increasing the sampling rate), filtering (e.g., providing spectral shaping and rejection of the interpolated image), and mixing (e.g., shifting the signal spectrum to a desired carrier frequency). Typically, the sample rate at the input of DUC 302 is low (e.g., the symbol rate of a digital communication system), while the output samples are much higher (e.g., the input sample rate to the DAC), which converts the digital samples to analog waveforms for further analog processing and frequency conversion.

As previously discussed, DPD and thus DPD system 304 functions with the type of nonlinearity "x" that the CATV amplifier is known to have and with the signal chain between the baseband and DFE chip 202 and CATV amplifier 212 known so that DPD system 304 can effectively implement the appropriate DPD processing (e.g., including adding the appropriate inverse nonlinearity "1/x"). For example, the DPD system 304 may be used to model CATV amplifiers (e.g., including nonlinear effects and signal chains). As such, the model provided by the DPD system 304 may be generated and/or updated based on the feedback data 308, where the feedback data 308 may include the output signals of the CATV amplifier (e.g., CATV amplifier 212). In some embodiments, feedback data 308 is processed by an analog-to-digital converter (ADC) 310 and provided as digital feedback data 311 to DPD adaptation engine 312. In various examples, based on digital feedback data 311, DPD adaptation engine 312 updates DPD system 304 so that DPD system 304 may adapt to the runtime behavior of the CATV amplifier. More specifically, in some embodiments, DPD adaptation engine 312 may determine the configuration of filter coefficients or other elements within DPD system 304 and may generally configure DPD modules within DPD system 304, as discussed below. Thus, by continually monitoring and updating the model provided by DPD system 304 (e.g., via feedback data 308 and DPD adaptation engine 312), optimal DPD processing can be achieved. For example, aspects of monitoring and updating the model (e.g., functions such as DPD adaptation engine 312) may be implemented as software stored in memory (e.g., within BRAM 103 or within another on-chip memory location) and executed by one or more on-chip processors (e.g., PROC 110). Note that in some embodiments, baseband and DFE chips 202, DAC 204, and ADC 310 may be implemented as a single chip (e.g., in RFSoC devices). The examples of monitoring and updating the model provided above are not meant to be limiting in any way, and it will be appreciated that although other methods are possible, embodiments of the present disclosure are not limited by any examples provided.

Referring now to fig. 4A, therein is shown a more detailed view of DPD system 304 described above for implementing aspects of the present disclosure. As described above, DPD system 304 may be used to model the nonlinear effects of CATV amplifiers. As such, the model provided by the DPD system 304 may be generated and/or updated based on feedback data (e.g., such as feedback data 308), which may include the output signal of the CATV amplifier processed by the ADC (e.g., such as ADC 310), which may be provided to the DPD adaptation engine 312 so that the DPD system 304 may adapt to the non-linear behavior of the CATV amplifier. Thus, the DPD system 304 model of the nonlinear effects of the CATV amplifier may be used to implement various features of the DPD system 304 (e.g., digital tilt filter 402, nonlinear data path 405, single sideband Hilbert filter 412, and digital tilt equalizer 414). Note that one or more components of DPD system 304 may be implemented in a programmable logic device, such as the programmable logic device of fig. 1.

Still referring to fig. 4A, the functionality of DPD system 304 is described in more detail. For example, in some embodiments, an input signal x (n), which may include the composite signal c (n) discussed above, is provided to the digital tilt filter 402. In various cases, the digital tilt filter 402 may be used to model the analog tilt filter 208 (fig. 2). Thus, as an example, the output of digital tilt filter 402 may be similar to the output of analog tilt filter 208. In some embodiments, the output of digital tilt filter 402 is provided as an input to a non-linear data path 405, which non-linear data path 405 includes a plurality of different parallel data path units including video bandwidth DPD data path 404, baseband DPD data path 406, second harmonic DPD data path 408 and third harmonic DPD data path 410. Typically, the nonlinear data path 405 is used to model and add the inverse nonlinear behavior of the CATV amplifier to the input signal. More specifically, each different parallel data path element of the non-linear data path 405 is used to model and add different aspects of the inverse non-linear behavior of the CATV amplifier to the input signal (e.g., the output of the digital tilt filter 402). For example, video bandwidth DPD data path 404 may model and add an inverse nonlinear video bandwidth component, baseband DPD data path 406 may model and add an inverse nonlinear baseband component, second harmonic DPD data path 408 may model and add an inverse nonlinear second harmonic component, and third harmonic DPD data path 410 may model and add an inverse third harmonic component. As shown, the output of each of the video bandwidth DPD data path 404, baseband DPD data path 406, second harmonic DPD data path, and third harmonic DPD data path 410 is then combined to provide a composite signal x' (n) that models the baseband, video, and harmonic components of the CATV amplifier.

In some embodiments, the output of the nonlinear data path 405 (e.g., the composite signal x '(n)) is provided as an input to a single-sideband hilbert filter 412, which may be used to further modulate the composite signal x' (n), and the output of the single-sideband hilbert filter 412 is provided as an input to a digital tilt equalizer 414. For example, the digital tilt equalizer 414 may be used to model and add the inverse of the analog tilt filter 208 (fig. 2) to the input signal. Thus, for example, the output of the digital tilt equalizer 414 may not be affected (e.g., or may be eliminated) by the analog tilt filter 208. As shown in fig. 4, in some embodiments, DPD input signal x (n) is also transmitted along path 416, where path 416 is a linear data path. In some examples, data path 416 may introduce only a time delay in DPD input signal x (n) (e.g., at block 417). In addition, DPD input signal x (n) transmitted along data path 416 bypasses digital tilt filter 402, nonlinear data path 405, single sideband hilbert filter 412 and digital tilt equalizer 414. In this way, the quality of the signal modulation of DPD input signal x (n) transmitted along data path 416 will remain unaffected by other elements of DPD system 304. In addition, as shown in fig. 4, the output of the digital tilt equalizer 414 and the delayed DPD input signal x (n) 419 are combined to provide the DPD output signal y (n).

Referring to fig. 5A, an exemplary DPD input spectrum 502 is provided. In some embodiments, DPD input signal x (n) (fig. 4) may include DPD input spectrum 502. As described above, DPD input spectrum 502 may include each of a plurality of different carriers mixed at different frequencies (e.g., by DUC 302), as previously described, where each of the plurality of different carriers is arranged side-by-side over a full bandwidth frequency of about 66MHz to about 1218 MHz. Referring to fig. 5B, an exemplary DPD output spectrum 504 is provided. In some embodiments, DPD output signal y (n) (fig. 4A) may include DPD output spectrum 504. Referring to fig. 5b, DPD output spectrum 504 includes one or more nonlinear components 506 that have been added to the signal by DPD system 304. As described in more detail below, and as a result of the processing performed by DPD system 304, CATV amplifier efficiency and signal quality are improved and power consumption is reduced.

Referring now to fig. 13-16, there are shown equations including a graphical representation showing how each of the different parallel data path elements of the non-linear data path 405 (fig. 4A) are derived, e.g., as a function of DPD input signal x (n) (fig. 4A). For example, fig. 13 provides an equation for deriving an inverse nonlinear baseband component corresponding to baseband DPD data path 406, expressed as:

fig. 14 provides an equation for deriving an inverse nonlinear video bandwidth component corresponding to video bandwidth DPD data path 404, expressed as:

/>

fig. 15 provides an equation for deriving an inverse second harmonic component corresponding to the second harmonic DPD data path 408, expressed as:

Fig. 16 provides an equation for deriving an inverse third harmonic component corresponding to third harmonic DPD data path 410, expressed as:

Referring now to fig. 17-23, a number of data illustrating at least some of the benefits and advantages of various embodiments of the present disclosure are shown. Referring first to fig. 17, a power spectrum 1700 of a single carrier is shown illustrating the nonlinear effects of a CATV amplifier. The power spectrum 1700, as well as the power spectrums of fig. 18-22, is generated by a spectrum analyzer that uses a resolution bandwidth of 100kHz and a video bandwidth of 1 MHz. In this example, the carrier frequency of the single carrier is equal to 254mhz, the catv amplifier operates at v=34V with bias current=320 ma, and the catv amplifier output=76 dbmV. In some embodiments, the waveform shown for power spectrum 1700 is a 4K QAM DOCSIS 3.1 waveform. As shown in fig. 17, the power spectrum 1700 also includes a nonlinear baseband component 1704, a nonlinear video bandwidth component 1706, a second harmonic component 1708, and a third harmonic component 1710. As described above, the power spectrum 1700 is for a single carrier. However, as previously mentioned, it is contemplated to arrange a plurality of different carriers side-by-side in frequency. In this case, the nonlinear components of the power spectrum 1700 (e.g., nonlinear baseband component 1704, nonlinear video bandwidth component 1706, second harmonic component 1708, and third harmonic component 1710) must affect and degrade the power spectrum of the adjacent carrier.

Referring now to fig. 18, there is shown a power spectrum 1700 (including the nonlinear effects of a CATV amplifier) and a power spectrum 1800 superimposed on the power spectrum 1700, showing the results of applying baseband DPD correction. In other words, the power spectrum 1800 illustrates the beneficial effect of adding an inverse nonlinear baseband component (e.g., at the output of a CATV amplifier) through the baseband DPD data path 406. Specifically, as shown in fig. 18, and as a result of applying the baseband DPD correction, the nonlinear baseband component 1704 of the power spectrum 1700 has been corrected (removed), as shown by component 1802 of the power spectrum 1800. In the example of fig. 18, baseband DPD correction brings about a 10dB improvement in power spectrum 1800, as indicated by arrow 1804.

Fig. 19 shows a power spectrum 1700 (including the nonlinear effects of CATV amplifiers) and a power spectrum 1900 superimposed on power spectrum 1700, showing the results of applying second harmonic DPD correction. In other words, the power spectrum 1900 shows the beneficial effect of adding the inverse second harmonic component (e.g., at the output of the CATV amplifier) through the second harmonic DPD data path 408. Specifically, as shown in fig. 19, and as a result of applying the second harmonic correction, the second harmonic component 1708 of the power spectrum 1700 has been corrected (removed), as shown by the component 1902 of the power spectrum 1900. As shown in the example of fig. 19, second harmonic DPD correction may result in an improvement of approximately 5dB in the power spectrum 1900.

Referring to fig. 20, a power spectrum 1700 (including the nonlinear effects of a CATV amplifier) and a power spectrum 2000 superimposed on the power spectrum 1700 are shown, showing the results of applying third harmonic DPD correction. In other words, the power spectrum 2000 shows the beneficial effect of adding the reverse third harmonic component (e.g., at the output of the CATV amplifier) through the third harmonic DPD data path 410. Specifically, as shown in fig. 20, and as a result of applying the third harmonic correction, the third harmonic component 1710 of the power spectrum 1700 has been corrected (removed), as shown by the component 2002 of the power spectrum 2000. As shown in the example of fig. 20, third harmonic DPD correction brings about 5dB improvement in the power spectrum 2000.

Referring to fig. 21, there is shown a power spectrum 2100 of two carriers 2103, 2105 illustrating the nonlinear effects of a CATV amplifier. Fig. 21 also includes a power spectrum 2102 superimposed on power spectrum 2100, showing the results of applying baseband DPD correction, and power spectrums 2104 superimposed on power spectrums 2100 and 2102, showing the results of applying baseband DPD correction and video bandwidth DPD correction. In other words, the power spectrum 2102 illustrates the beneficial effect of adding an inverse nonlinear baseband component (e.g., at the output of the CATV amplifier) through the baseband DPD data path 406. Similarly, the power spectrum 2104 shows the beneficial effects of adding both the inverse nonlinear baseband component through the baseband DPD data path 406 and the inverse nonlinear video bandwidth component through the video bandwidth DPD data path 404 (e.g., at the output of the CATV amplifier). As a result of the baseband DPD correction alone (power spectrum 2102), power spectrum 2102 shows a correction (e.g., as indicated by arrow 2112) as compared to power spectrum 2100. Also, as a result of applying the baseband DPD correction and the video bandwidth DPD correction (power spectrum 2104), the power spectrum 2104 shows corrections (e.g., as shown by arrows 2106 and 2110) as compared to the power spectrum 2100. In particular, the improvement in the presentation of the power spectrum 2104 in the region shown by arrow 2110 is particularly significant compared to the region shown by arrow 2108 (e.g., prior to the application of the baseband DPD correction and video bandwidth DPD correction). This is because carrier 2105 has higher power, resulting in a higher level of nonlinearity. In this way, carrier 2105 will benefit more from the correction provided by DPD system 304.

Fig. 22 shows a power spectrum 2200 comprising six different carriers arranged side-by-side over a full bandwidth frequency of about 66MHz to about 1218 MHz. In some embodiments, the waveform shown for power spectrum 2200 is a 4K QAM DOCSIS 3.1 waveform. In some examples, the power spectrum 2200 may be at the output of the analog tilt filter 208 (fig. 2). Fig. 22 also shows Adjacent Channel Power Ratio (ACPR) correction 2202 generated as a result of the correction provided by DPD system 304 being applied. For purposes of this disclosure, ACPR may be described as the ratio of power in adjacent channels to the power of the main channel, and it is desirable that the ACPR value be as low as possible. Therefore, the ACPR correction 2202 shown in fig. 22 is advantageous.

Referring to fig. 23, a table is shown that includes Modulation Error Ratio (MER) data for a CATV amplifier that shows the effect of applying the correction provided by DPD system 304 to MER data. For example, an MER is a metric used to quantify the performance of a digital radio (or digital TV) transmitter or receiver in a communication system using digital modulation (e.g., QAM). For the example of fig. 23, the CATV amplifier module under test may operate at v=34V. MER data was compared to the cabling industry specifications (mer=41 db,4kqam,76.8dbmv/75Ω). The CATV amplifier was tested using six carriers, where the first carrier was a 4K QAM signal with a carrier frequency of 204MHz, the second carrier was a 4K QAM signal with a carrier frequency of 396MHz, the third carrier was a 4K QAM signal with a carrier frequency of 588MHz, the fourth carrier was a 4K QAM signal with a carrier frequency of 786MHz, the fifth carrier was a 4K QAM signal with a carrier frequency of 930MHz, and the sixth carrier was a 4K QAM signal with a carrier frequency of 1122 MHz. In the first test 2302, the sixth carrier does not meet the mer=41 dB specification with the CATV amplifier operating at a bias current of 530mA and without DPD correction. However, with DPD correction applied (e.g., by DPD system 304), all carriers meet MER specifications. In a second test 2304, the CATV amplifiers were operated at a bias current of 440mA (each reduced by about 3 watts compared to a bias current of 530 mA) and without DPD correction, all tested carriers did not meet the mer=41 dB specification. However, with DPD correction applied (e.g., by DPD system 304), all carriers meet MER specifications.

Referring now to fig. 24, a method 2400 for performing digital predistortion processing in a DPD system is shown in accordance with various embodiments. Method 2400 begins at block 2402, a DPD input signal is received at an input of a DPD system, such as DPD system 304 of fig. 4. As described above, in some embodiments, the DPD input signal may include a DPD input signal x (n) (fig. 4), which may also include a composite signal c (n) generated by DUC 302 (fig. 3). In some examples, method 2400 proceeds to block 2404, at block 2404, providing a non-linear data path coupled to an input of a DPD system. For example, the non-linear data path may include the non-linear data path 405 of fig. 4A. Thus, the non-linear data path may comprise a plurality of parallel data path elements. In some examples, the plurality of parallel data path elements includes a video bandwidth DPD data path 404, a baseband DPD data path 406, a second harmonic DPD data path 408, and a third harmonic DPD data path 410. In some embodiments, the method 2400 proceeds to block 2406, where each different parallel data path unit may be used to add a different aspect of the inverse nonlinear behavior of the CATV amplifier to the input signal at block 2406. In some examples, method 2400 then proceeds to block 2408, where, at block 2408, a first combiner combines the outputs of each of the plurality of parallel data path elements to generate a first predistortion signal. In some cases, the first predistortion signal may include a composite signal x' (n) modeling baseband, video, and harmonic components of the CATV amplifier (fig. 4A). In some embodiments, method 2400 proceeds to block 2410, at block 2410, providing a linear data path coupled to the input in parallel with the nonlinear data path, and wherein the linear data path generates a second predistortion signal. In some embodiments, the second predistortion signal may include a time delayed DPD input signal x (n) 419 (fig. 4A). The method then proceeds to block 2412 where, at block 2412, the second combiner combines the first predistortion signal and the second predistortion signal to generate a DPD output signal. In some embodiments, the DPD output signal may include a DPD output signal y (n) (fig. 4A). In various embodiments, the method proceeds to block 2414, where the DPD output signal is provided to a CATV amplifier (e.g., CATV amplifier 212 of fig. 2) at block 2414. According to an embodiment of the present disclosure, the DPD output signal is configured to compensate for multiple nonlinear components of the CATV amplifier. It will be appreciated that additional method steps may be implemented before, during, and after method 2400, and that some of the method steps described above may be replaced or eliminated according to various embodiments of method 2400 without departing from the scope of the disclosure.

It should be noted that the various configurations (e.g., components of cable network 200, DFE system 300, and DPD system 304, the number of parallel data path elements in fig. 4A, and other features and components shown in the figures) are merely exemplary and are not intended to limit what is specifically recited in the appended claims. Those skilled in the art will appreciate that other configurations may be used. Moreover, although an exemplary cable network 200 is shown, the DPD systems disclosed herein can be used in other communication systems, for example, where other communication systems deploy amplifiers that exhibit detrimental nonlinear behavior.

The invention may be represented by, but is not limited to, one or more of the following embodiments.

Example 1: a Crest Factor Reduction (CFR) system comprising: a digital tilt filter coupled to an input of the CFR system, wherein the digital tilt filter is configured to receive the system input signal and generate a digital tilt filter output signal at a digital tilt filter output; a CFR module coupled to the digital tilt filter output, wherein the CFR module is configured to receive the digital tilt filter output signal and to CFR process the digital tilt filter output signal to generate a CFR module output signal at the CFR module output; a digital tilt equalizer coupled to the CFR module output, wherein the digital tilt equalizer is configured to receive the CFR module output signal and generate a system output signal.

Example 2: the CFR system of example 1, further comprising: a Digital Predistortion (DPD) module coupled to the CFR module output, wherein the DPD module is configured to receive the CFR module output signal and perform DPD processing on the CFR module output signal to generate a DPD module output signal at the DPD module output; wherein the digital tilt equalizer is coupled to the DPD module output, and wherein the digital tilt equalizer is configured to receive the DPD module output signal and generate a system output signal.

Example 3: the CFR system of example 1, wherein the system input signal has a first peak-to-average power ratio (PAPR), and wherein the CFR module output signal has a second PAPR that is less than the first PAPR.

Example 4: the CFR system of example 2, further comprising: a first linear data path coupled to an input of the CFR system and connected in parallel with the CFR module and the DPD module to generate a first delay signal; and a first combiner configured to combine the digital tilt equalizer output signal and the first delay signal to generate a system output signal.

Example 5: the CFR system of example 4, further comprising: a second linear data path coupled to an input of the CFR system and in parallel with the CFR module to generate a second latency signal; a second combiner configured to combine the CFR module output signal and the second time-delayed signal to generate a first output signal; and a third combiner for combining the first output signal and the DPD module output signal to generate a system output signal.

Example 6: the CFR system of example 2 wherein the DPD module further includes: a nonlinear data path coupled to the CFR module output, wherein the nonlinear data path comprises a plurality of parallel data path units, each parallel data path unit of the plurality of parallel data path units coupled to the CFR module output and configured to add a different inverse nonlinear component corresponding to the nonlinear component of the amplifier to the CFR module output signal, and wherein the combiner is configured to combine the outputs of each parallel data path unit of the plurality of parallel data path units to generate the DPD module output signal.

Example 7: the CFR system of example 1, wherein the digital-to-analog converter (DAC) is configured to receive the system output signal and generate a DAC output signal, wherein the analog tilt filter is configured to receive the DAC output signal and generate an analog tilt filter output signal, and wherein the digital tilt filter is configured to model the analog tilt filter.

Example 8: the CFR system of example 7, wherein the digital tilt equalizer is configured to model an inverse of the analog tilt filter.

Example 9: the CFR system of example 2 further comprising a single sideband hilbert filter, wherein the single sideband hilbert filter input is configured to receive the DPD module output signal, and wherein the single sideband hilbert filter output is coupled to the digital tilt equalizer input.

Example 10: the CFR system of example 1, further comprising an adaptation engine configured to receive feedback data from the amplifier output, wherein the adaptation engine is configured to update a configuration of the CFR module based on the feedback data.

Example 11: a Digital Front End (DFE) system configured to perform Crest Factor Reduction (CFR) processing, the DFE system comprising: a digital up-converter (DUC) configured to receive and convert the baseband data input signal to generate a composite signal; a CFR system including a digital tilt filter, a CFR module, and a digital tilt equalizer, wherein the digital tilt filter is configured to receive the composite signal and to generate a digital tilt filter output signal, the CFR module is configured to receive the digital tilt filter output signal and to perform CFR processing on the digital tilt filter output signal to generate a CFR module output signal, the digital tilt equalizer is configured to receive the CFR module output signal and to generate a CFR system output signal, the CFR system output signal coupled to the amplifier; and an adaptation engine configured to receive feedback data from the output of the amplifier, wherein the adaptation engine is configured to update the configuration of the CFR system based on the feedback data.

Example 12: the DFE system of example 11, wherein the CFR process is configured to reduce a peak-to-average power ratio (PAPR) of the digital oblique filter output signal.

Example 13: the DFE system of example 11, wherein the CFR system further comprises: a Digital Predistortion (DPD) module comprising a nonlinear data path coupled to the output of the CFR module, wherein the nonlinear data path comprises a plurality of parallel data path elements, each parallel data path element coupled to the output of the CFR module and configured to model a different inverse nonlinear component corresponding to the nonlinear component of the amplifier, wherein a combiner is configured to combine the outputs of each of the plurality of parallel data path elements to generate a DPD module output signal, and wherein the digital tilt equalizer is configured to receive the DPD module output signal and to generate a CFR system output signal.

Example 14: the DFE system of example 11, wherein the digital-to-analog converter (DAC) is configured to receive the CFR system output signal and generate a DAC output signal, wherein the analog tilt filter is configured to receive the DAC output signal and generate an analog tilt filter output signal, and wherein the digital tilt filter is configured to model the analog tilt filter.

Example 15: the DFE system of example 14, wherein the digital tilt equalizer is configured to model an inverse of the analog tilt filter.

Example 16: a method, comprising: receiving an input signal at a digital ramp filter of a Crest Factor Reduction (CFR) system and generating a digital ramp filter output signal at a digital ramp filter output; performing CFR processing at a CFR module of the CFR system on the digital tilted filter output signal to generate a CFR module output signal, wherein the CFR processing is configured to reduce a peak-to-average power ratio (PAPR) of the digital tilted filter output signal; receiving a CFR module output signal at a digital tilt equalizer of the CFR system and generating a system output signal; and providing the system output signal to an amplifier.

Example 17: the method of example 16, further comprising: the configuration of the CFR system is updated in response to feedback data received from the output of the amplifier.

Example 18: the method of example 16, further comprising: performing Digital Predistortion (DPD) processing on the CFR module output signal at a DPD module of the CFR system to generate a DPD module output signal; and receiving the DPD module output signal at a digital tilt equalizer of the CFR system and generating a system output signal.

Example 19: the method of example 18, wherein the DPD module further comprises: a nonlinear data path coupled to the CFR module output, wherein the nonlinear data path comprises a plurality of parallel data path units, each parallel data path unit coupled to the CFR module output and configured to model a different inverse nonlinear component corresponding to the nonlinear component of the amplifier, and wherein the combiner is configured to combine the outputs of each parallel data path unit of the plurality of parallel data path units to generate the DPD module output signal.

Example 20: the method of example 16, further comprising: the power consumption of the amplifier is reduced in response to providing the system output signal to the amplifier while operating the amplifier in a nonlinear region.

Example 21: a Digital Predistortion (DPD) system, comprising: an input configured to receive a DPD input signal; and a nonlinear data path coupled to the input, wherein the nonlinear data path comprises a plurality of parallel data path elements, each parallel data path element coupled to the input, wherein each parallel data path element of the plurality of parallel data path elements is configured to add a different inverse nonlinear component corresponding to the nonlinear component of the amplifier to the DPD input signal, and wherein the first combiner is configured to combine the outputs of each parallel data path element of the plurality of parallel data path elements to generate the first predistortion signal; a linear data path coupled to the input in parallel with the nonlinear data path to generate a second predistortion signal; and a second combiner configured to combine the first predistortion signal and the second predistortion signal to generate a DPD output signal.

Example 22: the DPD system of example 21, wherein the plurality of parallel data path units includes a baseband DPD data path, a video bandwidth DPD data path, a second harmonic DPD data path, and a third harmonic DPD data path.

Example 23: the DPD system of example 22, wherein the baseband DPD data path is configured to add an inverse nonlinear baseband component to the DPD input signal.

Example 24: the DPD system of example 22, wherein the video bandwidth DPD data path is configured to add an inverse nonlinear video bandwidth component to the DPD input signal.

Example 25: the DPD system of example 22, wherein the second harmonic DPD data path is configured to add an inverse second harmonic component to the DPD input signal.

Example 26: the DPD system of example 22, wherein the third harmonic DPD data path is configured to add an inverse third harmonic component to the DPD input signal.

Example 27: the DPD system of example 21, further comprising a digital tilt filter configured to model the analog tilt filter, wherein the digital tilt filter input is coupled to the input, and wherein the digital tilt filter output is coupled to the nonlinear data path.

Example 28: the DPD system of example 21, further comprising a digital tilt equalizer configured to model an inverse of the analog tilt filter, wherein the digital tilt equalizer input is configured to receive the first predistortion signal, and wherein the second combiner is configured to combine the digital tilt equalizer output to the second predistortion signal to generate the DPD output signal.

Example 29: the DPD system of example 28, further comprising a single sideband hilbert filter, wherein the single sideband hilbert filter input is configured to receive the first predistortion signal, and wherein the single sideband hilbert filter output is coupled to the digital tilt equalizer input.

Example 30: the DPD system of example 21, wherein the DPD output signal is coupled to the amplifier input to generate an amplified output signal, and wherein the DPD output signal is configured to compensate for a plurality of nonlinear components of the amplifier.

Example 31: a Digital Front End (DFE) system configured to perform Digital Predistortion (DPD) processing, the DFE system comprising: a digital up-converter (DUC) configured to receive and convert the baseband data input signal to generate a composite signal; and a DPD system configured to receive the composite signal at a DPD input and perform DPD processing on the composite signal, wherein the DPD input is coupled to a plurality of parallel data path units, wherein at least one of the plurality of parallel data path units is configured to add an inverse harmonic component to the composite signal that corresponds to the nonlinear harmonic component of the amplifier, wherein the combiner is configured to combine the outputs of each of the plurality of data path units to generate a DPD output signal, wherein the DPD output signal is coupled to the amplifier; wherein the DPD output signal is configured to compensate for nonlinear harmonic components of the amplifier.

Example 32: the DFE system of example 30, wherein the plurality of parallel data path elements includes a baseband DPD data path, a video bandwidth DPD data path, a second harmonic DPD data path, and a third harmonic DPD data path.

Example 33: the DFE system of example 31, wherein the DUC is configured to perform interpolation processing on the baseband data input signal to generate an interpolated signal, and wherein the DUC is configured to perform mixing processing on the interpolated signal to generate a composite signal.

Example 34: the DFE system of example 31, wherein the DPD system further includes a digital tilt filter configured to model the analog tilt filter, wherein the digital tilt filter input is configured to receive the composite signal, and wherein the digital tilt filter output is coupled to the plurality of parallel data path elements.

Example 35: the DFE system of example 31, wherein the DPD system further includes a digital tilt equalizer configured to model an inverse model of the analog tilt filter, wherein the digital tilt equalizer input is configured to receive a combined output of each of the plurality of data path elements, and wherein the other combiner is configured to combine the digital tilt equalizer output to the linear DPD signal to generate the DPD output signal.

Example 36: a method, comprising: receiving a Digital Predistortion (DPD) input signal at an input of a DPD system; receiving a DPD input signal on a non-linear data path coupled to an input of a DPD system, wherein the non-linear data path includes a plurality of parallel data path elements, each parallel data path element coupled to the input; adding an inverse nonlinear component corresponding to the nonlinear component of the amplifier to the DPD input signal through each of the plurality of parallel data path units; combining, by a first combiner, an output of each of a plurality of parallel data path units to generate a first predistortion signal; receiving the DPD input signal at a linear data path coupled to the input in parallel with the nonlinear data path to generate a second predistortion signal; the first predistortion signal and the second predistortion signal are combined by a second combiner to generate a DPD output signal.

Example 37: the method of example 36, wherein the plurality of parallel data path elements includes a baseband DPD data path, a video bandwidth DPD data path, a second harmonic DPD data path, and a third harmonic DPD data path.

Example 38: the method of example 37, further comprising: adding an inverse nonlinear baseband component to the DPD input signal through a baseband DPD data path; adding an inverse nonlinear video bandwidth component to the DPD input signal over a video bandwidth DPD data path; adding an inverse second harmonic component to the DPD input signal through a second harmonic DPD data path; and adding the inverse third harmonic component to the DPD input signal through the third harmonic DPD data path.

Example 39: the method of example 36, further comprising: the DPD output signal is provided to an amplifier input to generate an amplified output signal, wherein the DPD output signal is configured to compensate for a plurality of nonlinear components of the amplifier.

Example 40: the method of example 36, further comprising: in response to providing the DPD output signal to the amplifier while operating the amplifier in a non-linear region, power consumption of the amplifier is reduced.

While particular embodiments have been shown and described, it will be understood that there is no intent to limit the claimed invention to the preferred embodiments, and it will be obvious to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the claimed invention. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense. The claimed invention is intended to cover alternatives, modifications and equivalents.

Claims

1. A crest factor reduction CFR system, wherein said CFR system comprises:

A digital tilt filter coupled to an input of the CFR system, wherein the digital tilt filter is configured to receive a system input signal and generate a digital tilt filter output signal at a digital tilt filter output;

a CFR module coupled to the digital tilted filter output, wherein the CFR module is configured to receive the digital tilted filter output signal and CFR process the digital tilted filter output signal to generate a CFR module output signal at a CFR module output; and

A digital tilt equalizer coupled to the CFR module output, wherein the digital tilt equalizer is configured to receive the CFR module output signal and generate a system output signal;

a first linear data path coupled to an input of the CFR system and in parallel with the CFR module and DPD module to generate a first delay signal;

A first combiner configured to combine a digital tilt equalizer output signal and the first delay signal to generate the system output signal;

a second linear data path coupled to an input of the CFR module and in parallel with the CFR module to generate a second time-delayed signal; and

A second combiner configured to combine the CFR module output signal and the second time-delayed signal to generate a first output signal.

2. The CFR system of claim 1 further comprising:

A digital predistortion DPD module coupled to the CFR module output, wherein the DPD module is configured to receive the CFR module output signal and perform DPD processing on the CFR module output signal to generate a DPD module output signal at a DPD module output;

wherein the digital tilt equalizer is coupled to the DPD module output and the digital tilt equalizer is configured to receive the DPD module output signal and generate the system output signal.

3. The CFR system of claim 1, wherein the system input signal has a first peak-to-average power ratio, PAPR, and the CFR module output signal has a second PAPR that is less than the first PAPR.

4. The CFR system of claim 1 further comprising:

A third combiner configured to combine the first output signal and the DPD module output signal to generate the system output signal.

5. The CFR system of claim 2 wherein the DPD module further comprises:

A nonlinear data path coupled to the CFR module output, wherein the nonlinear data path comprises a plurality of parallel data path units, each of the parallel data path units coupled to the CFR module output, each of the plurality of parallel data path units configured to add a different inverse nonlinear component corresponding to the nonlinear component of the amplifier to the CFR module output signal, and wherein a combiner is configured to combine the outputs of each of the plurality of parallel data path units to generate the DPD module output signal.

6. The CFR system of claim 1 wherein a digital-to-analog converter, DAC, is configured to receive the system output signal and generate a DAC output signal, wherein an analog tilt filter is configured to receive the DAC output signal and generate an analog tilt filter output signal, and wherein the digital tilt filter is configured to model the analog tilt filter.

7. The CFR system of claim 6 wherein the digital tilt equalizer is configured to model an inverse of the analog tilt filter.

8. The CFR system of claim 2 further comprising:

A single sideband hilbert filter having a single sideband hilbert filter input configured to receive the DPD module output signal, the single sideband hilbert filter output coupled to the digital tilt equalizer input.

9. The CFR system of claim 1 further comprising:

an adaptation engine configured to receive feedback data from an amplifier output, wherein the adaptation engine is configured to update a configuration of the CFR module based on the feedback data.

10. A digital front end DFE system configured to perform crest factor reduction, CFR, processing, the DFE system comprising:

A digital up-converter DUC configured to receive and convert the baseband data input signal to generate a composite signal;

A CFR system including a digital tilt filter, a CFR module, and a digital tilt equalizer, wherein the digital tilt filter is configured to receive a composite signal and generate a digital tilt filter output signal, the CFR module is configured to receive the digital tilt filter output signal and perform CFR processing on the digital tilt filter output signal to generate a CFR module output signal, the digital tilt equalizer is configured to receive the CFR module output signal and generate a CFR system output signal, the CFR system output signal coupled to an amplifier; and

An adaptation engine configured to receive feedback data from an output of an amplifier, wherein the adaptation engine is configured to update a configuration of the CFR system based on the feedback data, the CFR system further comprising:

A first combiner configured to combine a digital tilt equalizer output signal and the first delay signal,

To generate the system output signal;

a second linear data path coupled to an input of the CFR module and connected in parallel with the CFR module,

To generate a second time-delayed signal; and

11. The DFE system of claim 10, wherein the CFR process is configured to reduce a peak-to-average power ratio, PAPR, of the digital ramp filter output signal.

12. The DFE system of claim 10, wherein the CFR system further comprises:

A digitally predistorted DPD module comprising a nonlinear data path coupled to a CFR module output, wherein the nonlinear data path comprises a plurality of parallel data path units, each of the parallel data path units coupled to the CFR module output, each of the plurality of parallel data path units configured to model a different inverse nonlinear component corresponding to a nonlinear component of an amplifier, a combiner configured to combine the outputs of each of the plurality of parallel data path units to generate a DPD module output signal, the digital tilt equalizer configured to receive the DPD module output signal and to generate the CFR system output signal.

13. The DFE system of claim 10, wherein a digital-to-analog converter, DAC, is configured to receive the CFR system output signal and generate a DAC output signal, wherein an analog tilt filter is configured to receive the DAC output signal and generate an analog tilt filter output signal, and wherein the digital tilt filter is configured to model the analog tilt filter.

14. The DFE system of claim 13, wherein the digital tilt equalizer is configured to model an inverse of the analog tilt filter.