CN112736854A

CN112736854A - MOS tube clamping circuit system

Info

Publication number: CN112736854A
Application number: CN202110201658.9A
Authority: CN
Inventors: 郭金彪
Original assignee: Nawa Electronics Shanghai Co ltd
Current assignee: Nawa Electronics Shanghai Co ltd
Priority date: 2020-12-03
Filing date: 2021-02-23
Publication date: 2021-04-30

Abstract

The present invention mainly provides a clamping circuit system of MOS transistor, which is electrically connected between a voltage input terminal and a voltage output terminal, the MOS tube clamping circuit system comprises at least one MOS tube clamping circuit, a triode switch circuit, a first voltage stabilizing circuit, a second voltage stabilizing circuit, a main switch circuit, a voltage dividing circuit and a voltage limiting protection circuit, wherein the MOS tube clamping circuit is electrically connected between the main switch circuit and the voltage input terminal, and the MOS tube clamping circuit is respectively connected with the first voltage stabilizing circuit and the voltage limiting protection circuit in parallel, the triode switch circuit and the second voltage stabilizing circuit are sequentially connected in series with the control end of the MOS tube clamping circuit, and two ends of the voltage division circuit are respectively and electrically connected in parallel with two ends of the MOS tube clamping circuit and the main switch circuit, so that the voltage control of the voltage output end is realized.

Description

MOS tube clamping circuit system

Technical Field

The invention belongs to the field of circuit design, and particularly relates to a hardware circuit for realizing transient anti-interference 3b high-voltage pulse test and input overvoltage protection by using clamping voltage of an MOS (metal oxide semiconductor) transistor, so as to solve the problems of secondary interference, TVS (transient voltage suppressor) damage and the like caused by the conventional hardware circuit.

Background

A conventional Transient Voltage Suppressor (TVS) diode is a high-performance protection device, and has a very fast response speed and a relatively large surge discharging capability. When two poles of the TVS diode are impacted by reverse transient high voltage, the TVS diode can quickly change high impedance between the two poles into low impedance and absorb surge power of thousands of watts, so that a voltage clamp between the two poles is positioned at a preset value, and precision components in an electronic circuit are effectively protected from being damaged by impact of various surge pulses.

The TVS diode has the advantages of high response speed, large transient power, low leakage current, small breakdown voltage deviation, easy control of clamping voltage, no damage limit, small size and the like, and is widely applied to various fields of computer systems, communication equipment, alternating/direct current power supplies, automobiles, electronic ballasts, household appliances, instruments and meters, sensors, industrial control loops, relays, suppression of contactor noise and the like so as to ensure the safe operation of circuit systems and modules.

With the continuous development of integrated circuit chips, the requirements of various mobile terminal devices on safety and reliability are higher and higher. At present, many electronic products need to pass relevant standard EMC experiments, wherein the power line transient anti-interference 3b pulse in ISO7637-2 is the difficulty of the experiments. The method realized at present is an overvoltage protection circuit formed by a piezoresistor and a TVS tube, and the method has the main defects that: the discharge of high voltage energy to the ground network through large currents is prone to secondary interference, and when the pulse repetition rate ratio (i.e., the ratio of pulse duration to pause time) is greater than 0.01%, the accumulation of pulse power can cause the TVS tube to burn out.

Disclosure of Invention

One advantage of the present invention is to provide an MOS tube clamping circuit system, which can solve the problem of secondary interference occurring in the MOS tube clamping circuit system in the prior art, thereby ensuring the stability of the circuit system.

One advantage of the present invention is to provide a MOS transistor clamping circuit system, which can utilize a MOS transistor clamping voltage to implement a transient anti-interference 3b high voltage pulse test, and can solve the problem that a TVS transistor is damaged by a circuit system in the prior art.

One advantage of the present invention is to provide a MOS transistor clamping circuit system, which can provide a hardware circuit with input overvoltage protection, so as to ensure that the MOS transistor clamping circuit system is not limited by voltage changes, thereby improving the operating stability of the MOS transistor clamping circuit system of the present invention.

One advantage of the present invention is to provide a MOS transistor clamping circuit system, which is disposed at an input end of a main power source of a product, so as to provide a good protection effect for the product, thereby preventing the product from being damaged during a test.

One advantage of the present invention is to provide a MOS transistor clamping circuit system, which can achieve a constant output voltage on the premise that an input voltage is unstable, thereby achieving a clamping protection function for the output voltage.

One advantage of the present invention is to provide a MOS transistor clamping circuit system, which clamps the change of the output voltage through the Vds voltage change in the MOS transistor, so as to limit the post-stage operating voltage to be maintained within a predetermined required value, thereby protecting the post-stage operating circuit.

One advantage of the present invention is to provide a MOS transistor clamping circuit system, which ensures that a MOS transistor works in a proper voltage linear region by using a MOS transistor Vds voltage accurate voltage limiting circuit formed by a MOS transistor clamping circuit, so that the MOS clamping circuit system realizes an overvoltage protection function.

One advantage of the present invention is to provide a MOS transistor clamping circuit system, which can pass transient anti-interference 3b high voltage pulse tests by controlling the operating voltage of the MOS transistor.

One advantage of the present invention is to provide a clamping circuit system for an MOS transistor, which can solve the problems of high clamping voltage, large low voltage current, and easy aging of a voltage dependent resistor protection circuit in the prior art, compared with the prior art.

To achieve at least the above advantages, the present invention provides a clamping circuit system for an MOS transistor, electrically connected between a voltage input terminal and a voltage output terminal, the clamping circuit system for an MOS transistor comprising at least a clamping circuit for an MOS transistor, a triode switch circuit, a first voltage regulator circuit, a second voltage regulator circuit, a main switch circuit, a voltage divider circuit, and a voltage limiting protection circuit, wherein the clamping circuit for an MOS transistor is electrically connected between the main switch circuit and the voltage input terminal, the clamping circuit for an MOS transistor is respectively connected in parallel with the first voltage regulator circuit and the voltage limiting protection circuit, the triode switch circuit and the second voltage regulator circuit are sequentially connected in series at a control terminal of the clamping circuit for an MOS transistor, two terminals of the voltage divider circuit are respectively electrically connected in parallel at two terminals of the clamping circuit for an MOS transistor and the main switch circuit, thereby realizing the voltage control of the voltage output end.

In some embodiments, the voltage limiting protection circuit includes a first resistor, a fourth resistor, and a second transistor, where the first resistor, the fourth resistor, and the second transistor are electrically connected, and the first resistor and the fourth resistor are respectively electrically connected in parallel to a base of the second transistor, that is, a base of the second transistor is electrically connected in parallel to a second end of the first resistor and a first end of the fourth resistor.

In some embodiments, the triode switch circuit includes a third triode electrically connected between the voltage limiting protection circuit and the second voltage stabilizing circuit, and a base of the third triode is electrically connected to the voltage dividing circuit.

In some embodiments, the first voltage regulation circuit is configured as a first diode connected in parallel between the voltage limiting protection circuit and the MOS clamp circuit.

In some embodiments, the second voltage regulating circuit is configured as a second diode, and the second diode is electrically connected in series between the triode switch circuit and the main switch circuit to regulate the on-voltage of the triode switch circuit.

In some embodiments, the MOS transistor clamping circuit includes a first capacitor, a second resistor, and a first MOS transistor, wherein the first MOS transistor is electrically connected in parallel between the first capacitor and the voltage output terminal, and the first capacitor and the second resistor are electrically connected in parallel between the first voltage regulator circuit and the first MOS transistor control terminal.

In some embodiments, a first terminal of the first diode in the first voltage stabilizing circuit is electrically connected in parallel between a collector of the second transistor and a first terminal of the second resistor in the MOS transistor clamping circuit, and a second terminal of the first diode is electrically connected in parallel between an emitter of the second transistor and a second terminal of the second resistor.

In some embodiments, the main switch circuit includes a fifth resistor, a fourth transistor, a second capacitor, and a ninth resistor, wherein the fifth resistor is electrically connected in series with the fourth transistor, one electrical end of the second capacitor and the ninth resistor is connected in parallel between the base of the fourth transistor and the firing signal terminal, and the other electrical end of the second capacitor and the ninth resistor is connected in parallel with the emitter of the fourth transistor.

In some embodiments, the voltage divider circuit comprises a third resistor and a sixth resistor, wherein the third resistor and the sixth resistor are connected in parallel to the triode switch circuit, and the other ends of the third resistor and the sixth resistor are respectively connected in parallel to the voltage output end and the ground end of the voltage output, so as to provide the turn-on voltage for the triode switch circuit.

In some embodiments, a first terminal of the fifth resistor is electrically connected to the MOS transistor clamping circuit, a second terminal of the fifth resistor is electrically connected to a third terminal of the fourth transistor, a second terminal of the fourth transistor is electrically connected in parallel to a second terminal of the second capacitor and a second terminal of the ninth resistor, respectively, and a first terminal of the second capacitor is electrically connected in parallel to a first terminal of the fourth transistor and a first terminal of the ninth resistor, respectively.

Further objects and advantages of the invention will be fully apparent from the ensuing description and drawings.

These and other objects, features and advantages of the present invention will become more fully apparent from the following detailed description, the accompanying drawings and the claims.

Drawings

Fig. 1 is a block diagram of a MOS transistor clamping circuit system according to a first embodiment of the present invention.

Fig. 2 is a schematic structural connection diagram of a MOS transistor clamping circuit system according to a first embodiment of the present invention.

Detailed Description

The following description is presented to disclose the invention so as to enable any person skilled in the art to practice the invention. The preferred embodiments in the following description are given by way of example only, and other obvious variations will occur to those skilled in the art. The basic principles of the invention, as defined in the following description, may be applied to other embodiments, variations, modifications, equivalents, and other technical solutions without departing from the spirit and scope of the invention.

It is understood that the terms "a" and "an" should be interpreted as meaning that a number of one element or element is one in one embodiment, while a number of other elements is one in another embodiment, and the terms "a" and "an" should not be interpreted as limiting the number.

In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.

As shown in fig. 1, the present invention mainly provides a MOS clamping circuit system 10, electrically connected between a voltage input terminal and a voltage output terminal, the MOS clamping circuit system 10 includes at least a MOS clamping circuit 11, a triode switch circuit 12, a first voltage regulator circuit 13, a second voltage regulator circuit 14, a voltage divider circuit 15, a main switch circuit 16, and a voltage limiting protection circuit 17, wherein the MOS clamping circuit 11 is electrically connected between the main switch circuit 16 and the voltage input terminal, the MOS clamping circuit 11 is respectively connected in parallel with the first voltage regulator circuit 13 and the voltage limiting protection circuit 17, the triode switch circuit 12 and the second voltage regulator circuit 14 are sequentially connected in series at a control terminal of the MOS clamping circuit 11, two terminals of the voltage divider circuit 15 are respectively connected in parallel at one terminal of the MOS clamping circuit 11 and one terminal of the main switch circuit 16, the other end of the voltage divider circuit 15 is electrically connected to the triode switch circuit 12, so as to provide a turn-on voltage for the triode switch circuit 12.

In detail, as shown in fig. 2, the voltage limiting protection circuit 17 includes a first resistor R1, a fourth resistor R4, and a second transistor T2, wherein the first resistor R1, the fourth resistor R4, and the second transistor T2 are electrically connected, and the first resistor R1 and the fourth resistor R4 are respectively electrically connected in parallel to a base of the second transistor T2, that is, a base of the second transistor T2 is electrically connected in parallel to a second end of the first resistor R1 and a first end of the fourth resistor R4.

The triode switch circuit 12 includes a third triode T3, the third triode T3 is electrically connected between the voltage limiting protection circuit 17 and the second voltage stabilizing circuit 14, and the base of the third triode T3 is electrically connected to the voltage dividing circuit 15. In other words, the third terminal of the third transistor T3 is electrically connected in series to the second terminal of the fourth resistor R4 in the voltage limiting protection circuit 17, the second terminal of the third transistor T3 is electrically connected to the second voltage stabilizing circuit 14, and the first terminal of the third transistor T3 is electrically connected to the voltage dividing circuit 15.

The first voltage stabilizing circuit 13 is configured as a first diode Z1, the first diode Z1 is connected in parallel between the voltage limiting protection circuit 17 and the MOS clamp circuit 11, wherein one end of the first diode Z1 is connected in parallel between the emitter of the second transistor T2 in the voltage limiting protection circuit 17 and the MOS clamp circuit 11, and the other end of the first diode Z1 is connected in parallel between the collector of the second transistor T2 in the voltage limiting protection circuit 17 and the MOS clamp circuit 11.

The second voltage regulating circuit 14 is configured as a second diode Z2, and the second diode Z2 is electrically connected in series between the triode switch circuit 12 and the main switch circuit 16 to achieve a voltage regulating effect.

The MOS clamping circuit 11 includes a first capacitor C1, a second resistor R2, and a first MOS transistor T1, wherein the first MOS transistor T1 is electrically connected in parallel between the first capacitor C1 and the voltage output terminal Vout, and the first capacitor C1 and the second resistor R2 are electrically connected in parallel between the first regulator circuit 13 and the S-pole of the first MOS transistor T1.

In detail, a first terminal of the first diode Z1 in the first voltage stabilizing circuit 13 is electrically connected in parallel between a collector of the second transistor T2 and a first terminal of the second resistor R2 in the MOS transistor clamping circuit 11, and a second terminal of the first diode Z1 is electrically connected in parallel between an emitter of the second transistor T2 and a second terminal of the second resistor R2.

A first end of the first capacitor C1 is electrically connected in parallel between the first end of the second resistor R2 and the third end (S pole) of the first MOS transistor T1, a second end of the first capacitor C1 is electrically connected in parallel between the second end of the second resistor R2 and the first end (G pole) of the first MOS transistor T1, and a second end (D pole) of the first MOS transistor T1 is electrically connected to the voltage output terminal Vout. A first end of the second diode Z2 is electrically connected to the second end of the third transistor T3, and a second end of the second diode Z2 is electrically connected to the main switch circuit 16.

The main switch circuit 16 includes a fifth resistor R5, a fourth transistor T4, a second capacitor C2 and a ninth resistor R9, wherein the fifth resistor R5 and the fourth transistor T4 are electrically connected in series, one electrical end of the second capacitor C2 and the ninth resistor R9 are connected in parallel between the base of the fourth transistor T4 and the ignition signal terminal, and the other electrical end of the second capacitor C2 and the ninth resistor R9 are connected in parallel between the second regulator circuit 14 and the voltage input terminal Vin.

The voltage divider circuit 15 includes a third resistor R3 and a sixth resistor R6, wherein the third resistor R3 and the sixth resistor R6 are connected in parallel between the triode switch circuit 12 and the voltage output terminal, so as to achieve the effect of adjusting the turn-on voltage of the triode switch circuit 12.

In detail, a first end of the fifth resistor R5 is electrically connected to the MOS clamp circuit 11, a second end of the fifth resistor R5 is electrically connected to the third end of the fourth transistor T4, a second end of the fourth transistor T4 is electrically connected in parallel to a second end of the second capacitor C2 and a second end of the ninth resistor R9, respectively, and a first end of the second capacitor C2 is electrically connected in parallel to a first end of the fourth transistor T4 and a first end of the ninth resistor R9, respectively.

Next, the operation of the MOS transistor clamping circuit system 10 according to the present invention will be briefly described with reference to fig. 1 and fig. 2.

The MOS tube clamping circuit system 10 is electrically connected to the input end of the main power supply of the product, so that the MOS tube clamping circuit system 10 of the invention can play a stable protection role on the product.

When the MOS clamping circuit 11 starts to operate, the fourth transistor T4 is turned on by the high-level ignition signal terminal 18, so that the low potential appears at the first terminal G of the first MOS transistor T1 in the MOS clamping circuit 11, and the negative voltage appears at the G and S poles of the first MOS transistor T1 to turn on the first transistor. When the ignition signal terminal 18 changes to the low level, the pin terminal of the chip outputs the high level to make the first MOS transistor T1 normally conduct and output voltage, and the G pole and S pole voltage of the first MOS transistor T1 under normal operation are stabilized and kept stable by the first diode Z1 in the first voltage stabilizing circuit 13; under normal operation voltage, the second transistor T2 and the third transistor T3 and the second diode Z2 in the second voltage regulation circuit 14 do not operate. When the voltage input end Vin of the main power supply rises, the voltage monitored by the third resistor R3 and the sixth resistor R6 in the voltage dividing circuit 15 rises, and when the main voltage rises to about 36V, the voltage of the sixth resistor R6 in the voltage dividing circuit 15 becomes high, so that the second diode Z2 and the third triode T3 in the second voltage stabilizing circuit 14 are caused to realize conducting operation.

At this time, the Ic current of the third transistor T3 causes the first resistor R1 and the fourth resistor R4 in the voltage limiting protection circuit 17 to be turned on, and the divided voltage of the first resistor R1 causes the second transistor T2 to be turned on. Then, the voltage input end Vin gradually increases, the Vce voltage in the second triode T2 tends to decrease under the action of the first diode Z1 in the first voltage stabilizing circuit 13, the first MOS transistor T1 operates from the linear region to the cut-off region, the on-resistances of the S-pole and the D-pole of the first MOS transistor T1 in the MOS clamping circuit 11 increase while the load current does not change, and it is known from the definition of ohm law U-IR that Vds of the first MOS transistor T1 increases and the voltage output end Vout-Vds increases, so that the voltage output end Vout can achieve voltage reduction, and further achieve overvoltage protection and tests such as transient anti-interference 3b high voltage pulse.

In other words, the MOS transistor clamping circuit system 10 clamps the change of the voltage output terminal Vout through the Vds voltage change in the MOS transistor, so as to limit the post-stage operating voltage to be kept within a certain required value, thereby protecting the post-stage operating circuit. Compared with the prior art, the MOS tube clamping circuit system 10 solves the problems of high clamping voltage, high low voltage current, easy aging and the like of a voltage dependent resistor protection circuit in the prior art, and also solves the problems of secondary interference generated by an overvoltage protection circuit consisting of TVS tubes and circuit damage caused by burning of the TVS tubes due to high pulse repetition rate in the prior art.

Therefore, the MOS transistor clamping circuit system 10 of the present invention can select appropriate components according to actual conditions, so as to achieve a clamping protection function that ensures that the voltage output terminal Vout is maintained constant when the voltage input terminal Vin is too high, and thus, test items and corresponding test contents similar to transient anti-interference 3b high voltage pulses can be implemented.

It will be appreciated by persons skilled in the art that the embodiments of the invention described above and shown in the drawings are given by way of example only and are not limiting of the invention. The objects of the invention have been fully and effectively accomplished. The functional and structural principles of the present invention have been shown and described in the examples, and any variations or modifications of the embodiments of the present invention may be made without departing from the principles.

Claims

1. A MOS transistor clamping circuit system is electrically connected between a voltage input terminal and a voltage output terminal, it is characterized in that the MOS tube clamping circuit system comprises at least one MOS tube clamping circuit, a triode switch circuit, a first voltage stabilizing circuit, a second voltage stabilizing circuit, a main switch circuit, a voltage dividing circuit and a voltage limiting protection circuit, wherein the MOS tube clamping circuit is electrically connected between the main switch circuit and the voltage input terminal, and the MOS tube clamping circuit is respectively connected with the first voltage stabilizing circuit and the voltage limiting protection circuit in parallel, the triode switch circuit and the second voltage stabilizing circuit are sequentially connected in series with the control end of the MOS tube clamping circuit, and two ends of the voltage division circuit are respectively and electrically connected in parallel with the output end of the MOS tube clamping circuit and two ends of the ground signal of the main switch circuit, so that the voltage control of the voltage output end is realized.

2. The MOS transistor clamping circuit system according to claim 1, wherein the voltage limiting protection circuit comprises a first resistor, a fourth resistor and a second transistor, the first resistor, the fourth resistor and the second transistor are electrically connected, and the first resistor and the fourth resistor are electrically connected in parallel to the base of the second transistor, respectively, that is, the base of the second transistor is electrically connected in parallel to the second end of the first resistor and the first end of the fourth resistor.

3. The MOS transistor clamping circuit system of claim 2, wherein the triode switch circuit comprises a third triode electrically connected between the voltage limiting protection circuit and the second voltage stabilizing circuit and a base of the third triode electrically connected to the voltage dividing circuit.

4. The MOS tube clamping circuit system according to claim 3, wherein said first voltage regulation circuit is configured as a first diode, said first diode being connected in parallel across said voltage limiting protection circuit.

5. The MOS tube clamping circuit system according to claim 4, wherein said second voltage regulation circuit is configured as a second diode, said second diode being electrically connected in series between said triode switch circuit and said main switch circuit for regulating the turn-on voltage of the triode switch circuit.

6. The MOS transistor clamping circuit system of claim 5, wherein said MOS transistor clamping circuit comprises a first capacitor, a second resistor, and a first MOS transistor, wherein said first MOS transistor is electrically connected in parallel between said first capacitor and said voltage output terminal, and said first capacitor and said second resistor are electrically connected in parallel between said first voltage regulator circuit and said first MOS transistor control terminal.

7. The MOS tube clamping circuit system of claim 6, wherein a first terminal of said first diode in said first voltage regulation circuit is electrically connected in parallel between a collector of said second transistor and a first terminal of said second resistor in said MOS tube clamping circuit, and a second terminal of said first diode is electrically connected in parallel between an emitter of said second transistor and a second terminal of said second resistor.

8. The MOS tube clamping circuit system according to claim 7, wherein said main switching circuit comprises a fifth resistor, a fourth transistor, a second capacitor and a ninth resistor, wherein said fifth resistor is electrically connected in series with said fourth transistor, one electrical end of said second capacitor and said ninth resistor is connected in parallel between the base of said fourth transistor and the firing signal striking end, and the other electrical end of said second capacitor and said ninth resistor is connected in parallel with the emitter of said fourth transistor.

9. The MOS transistor clamping circuit system as claimed in claim 8, wherein said voltage divider circuit comprises a third resistor and a sixth resistor, wherein said third resistor and said sixth resistor are connected in parallel to said triode switch circuit, and the other end of said third resistor and said sixth resistor are connected in parallel to said voltage output terminal and a ground of said voltage output terminal, respectively, so as to provide a turn-on voltage for said triode switch circuit.

10. The MOS transistor clamping circuit system of claim 9, wherein a first terminal of the fifth resistor is electrically connected to the MOS transistor clamping circuit, a second terminal of the fifth resistor is electrically connected to the third terminal of the fourth transistor, a second terminal of the fourth transistor is electrically connected in parallel with a second terminal of the second capacitor and a second terminal of the ninth resistor, respectively, and a first terminal of the second capacitor is electrically connected in parallel with a first terminal of the fourth transistor and a first terminal of the ninth resistor, respectively.