CN112731828A

CN112731828A - Terminal resistor circuit, chip and chip communication device

Info

Publication number: CN112731828A
Application number: CN202011449291.4A
Authority: CN
Inventors: 张千文; 梁爱梅; 温长清; 王齐尉
Original assignee: Shenzhen Ziguang Tongchuang Electronics Co ltd
Current assignee: Shenzhen Ziguang Tongchuang Electronics Co ltd; Shenzhen Pango Microsystems Co Ltd
Priority date: 2020-12-09
Filing date: 2020-12-09
Publication date: 2021-04-30
Anticipated expiration: 2040-12-09
Also published as: CN112731828B; US20220286128A1; US11909388B2; WO2022121134A1

Abstract

The embodiment of the application discloses a terminal resistor circuit, a chip and a chip communication device, and relates to the technical field of semiconductor integrated circuits. The terminal resistance circuit is applied to a high-speed differential I/O pair of a chip, the high-speed differential I/O pair comprises a first interface and a second interface, and the terminal resistance circuit comprises: the device comprises two resistance circuits and a control circuit, wherein one end of the two resistance circuits after being connected in series is electrically connected with a first interface, the other end of the two resistance circuits after being connected in series is electrically connected with a second interface, a target node is arranged on a lead between the two resistance circuits, and the two resistance circuits are symmetrically arranged around the target node; the control circuit is respectively electrically connected with the two resistance circuits and is used for controlling the two resistance circuits to be in a disconnected state in the power-on process of the chip. The method and the device can avoid the problem that the system works abnormally due to the short circuit of the two I/O circuits in the power-on process of the chip, and improve the working stability of the chip.

Description

Terminal resistor circuit, chip and chip communication device

Technical Field

The present invention relates to the field of semiconductor integrated circuit technology, and more particularly, to a termination resistor circuit, a chip, and a chip communication device.

Background

With the rapid development of integrated circuits, a Field Programmable Gate Array (FPGA) chip as a Programmable logic device gradually evolves from a peripheral device of electronic design to the core of a digital system in more than twenty years, and with the progress of semiconductor process technology, the design technology of the FPGA chip has also made a rapid development and breakthrough. The FPGA chip has the characteristics of high density, high confidentiality, low power consumption, low cost, system integration, dynamic reconfiguration and the like, and is widely applied to the fields of communication, aerospace, consumer electronics and the like.

However, the conventional chip usually has a terminal resistor between two ends of a high-speed differential I/O pair thereof, and the chip is turned on when being powered on, so that the two ends of the high-speed differential I/O pair of the chip are short-circuited, and a problem of abnormal operation of a chip system is caused.

Disclosure of Invention

In view of the above problems, the present application provides a termination resistance circuit, a chip and a chip communication device to solve the above problems.

In a first aspect, an embodiment of the present application provides a termination resistor circuit, which is applied to a high-speed differential I/O pair of a chip, where the high-speed differential I/O pair includes a first interface and a second interface, and the termination resistor circuit includes: two resistance circuits and control circuit, wherein: one end of the two resistance circuits after being connected in series is electrically connected with the first interface, and the other end of the two resistance circuits after being connected in series is electrically connected with the second interface, wherein a line connecting the two resistance circuits is provided with a target node, and the two resistance circuits are symmetrically arranged around the target node; the control circuit is respectively electrically connected with the two resistance circuits and is used for controlling the two resistance circuits to be in a disconnected state in the power-on process of the chip.

In a second aspect, an embodiment of the present application provides a chip, where the chip includes an FPGA chip body and a terminal resistor circuit of the first aspect, a high-speed differential I/O pair of the FPGA chip body includes a first interface and a second interface, and the terminal resistor is electrically connected to the first interface and the second interface, respectively.

In a third aspect, an embodiment of the present application provides a chip communication device, where the chip communication device includes a first FPGA chip, a second FPGA chip, a first transmission line, a second transmission line, and three terminal resistor circuits as in the first aspect, where the three terminal resistor circuits include a first terminal resistor circuit, a second terminal resistor circuit, and a third terminal resistor circuit, a high-speed differential I/O pair of the first FPGA chip includes a first port and a second port, and a high-speed differential I/O pair of the second FPGA chip includes a third port and a fourth port. Wherein: the first port of the first FPGA chip is electrically connected with the third port of the second FPGA chip through a first transmission line, and the second port of the first FPGA chip is electrically connected with the fourth port of the second FPGA chip through a second transmission line; the first terminal resistance circuit is electrically connected with a first port of the first FPGA chip and a second port of the first FPGA chip respectively, and the first terminal resistance circuit is integrated in the first FPGA chip; the second terminal resistance circuit is electrically connected with a third port of the second FPGA chip and a fourth port of the second FPGA chip respectively, and the second terminal resistance circuit is arranged outside the second FPGA chip; the third terminal resistance circuit is electrically connected with the third port of the second FPGA chip and the fourth port of the second FPGA chip respectively, and the third terminal resistance circuit is integrated in the second FPGA chip.

The terminal resistance circuit, chip and chip communication device that this application embodiment provided, terminal resistance circuit through two resistance circuit and control circuit constitution, wherein: one end of the two resistor circuits after being connected in series is electrically connected with a first interface of a high-speed differential I/O pair of the chip, the other end of the two resistor circuits after being connected in series is electrically connected with a second interface of the high-speed differential I/O pair of the chip, wherein a target node is arranged on a lead between the two resistor circuits, the two resistor circuits are symmetrically arranged relative to the target node, and the control circuit is respectively electrically connected with the two resistor circuits and is used for controlling the two resistor circuits to be in a disconnection state in the power-on process of the chip, so that the problem that the two I/O interfaces of the chip cause abnormal system work due to short circuit in the power-on process can be avoided, and the working stability of a chip system is improved.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

Fig. 1 shows an equivalent schematic diagram of a MOS switch provided according to an embodiment of the present application.

Fig. 2 is a schematic diagram illustrating a relationship between a resistance value of an equivalent resistor with parallel NMOS and PMOS and an input voltage according to an embodiment of the present application.

Fig. 3 shows a connection diagram of applying the differential termination resistance Rs to a high-speed differential I/O pair of a chip according to an embodiment of the present application.

Fig. 4 shows a schematic block diagram of a termination resistance circuit provided according to an embodiment of the present application.

Fig. 5 is a schematic diagram illustrating a termination resistor circuit according to an embodiment of the present application.

Fig. 6 shows a schematic circuit diagram of a termination resistance circuit provided according to an embodiment of the present application.

Fig. 7 is a schematic diagram illustrating a termination resistor circuit according to another embodiment of the present application.

Fig. 8 shows a schematic structural diagram of a chip provided according to an embodiment of the present application.

Fig. 9 shows a schematic structural diagram of a chip communication device provided according to an embodiment of the present application.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations.

Thus, the following detailed description of the embodiments of the present application, presented in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.

In the description of the present application, it is noted that the terms "first", "second", "third", and the like are used merely for distinguishing between descriptions and are not intended to indicate or imply relative importance.

In the description of the present application, it is further noted that, unless expressly stated or limited otherwise, the terms "disposed," "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

The FPGA chip can provide abundant input and output pin resources for users, an input and output module (IOB) of the FPGA chip needs to support one or more interface protocols, along with the development of a semiconductor process, the characteristic size of the chip is reduced to 28nm, 16nm, 7nm and even 5nm, the FPGA scale is continuously improved, the function is continuously strong, the chip needs to interact with various external chips and support various voltage types, like one I/O needs to support voltage standards of 1.8V, 1.5V and 1.2V to realize complex logic functions, and the I/O design of the FPGA, particularly the high-speed differential I/O design faces challenges.

According to the physical knowledge of the semiconductor device, as shown in fig. 1, the NMOS or PMOS transistor operating in the deep linear region may be equivalent to a resistor Rs, and the source and drain terminals thereof are equivalent to the terminals of the resistor Rs, where Ron _ N is the resistor of the NMOS switch when SN is VDD, and Ron _ P is the resistor of the PMOS switch when SP is VSS.

When the NMOS and the PMOS are connected in parallel, a complementary switch on-resistance is formed, as shown in fig. 2, an equivalent resistance value of the complementary switch on-resistance is Ron _ eq, and Vin in fig. 2 represents a voltage value at the a/B (or S/D) end of the resistor. In the related art, the complementary switch resistor composed of NMOS and PMOS may be designed as a terminal resistor of an I/O module according to a Low-Voltage Differential Signaling (LVDS) standard or a Mobile Industry Processor Interface (MIPI) standard, and when the control terminal Voltage SN is at a high level and SP is at a Low level, the resistance of the equivalent resistor Ron _ eq may be as shown in fig. 2.

According to LVDS and MIPI standards, a typical value of the differential termination resistance Rs is 100 ohms, that is, when IOB applications of LVDS and MIPI standards are supported, a differential termination resistance Rs needs to be connected in series between a pair of differential I/O, and the differential termination resistance Rs is applied to a high-speed differential I/O pair of a chip, and a specific connection manner thereof may be as shown in fig. 3, in an FPGA chip (hereinafter, referred to as a chip), I/O of LVDS and MIPI of general differential standards are placed in adjacent positions, and communication between the FPGA1 and the FPGA2 mainly includes three parts: LVDS/MIPI OBUF, transmission line, and LVDS/MIPI IBUF. The OBUF is used as a data transmitter and is responsible for transmitting data _ in of the FPGA1 through output I/O ports PAD _ TXP and PAD _ TXN of the OBUFP and the OBUFN, the data enter the FPGA2 through PAD _ RXP and PAD _ RXN after passing through a transmission line, LVDS/MIPI IBUF in the FPGA2 can recover data meeting LVDS and MIPI standards, and the data _ out is output to a chip internal logic circuit.

The inventor finds that in the design of the FPGA chip IOB, the termination resistor Rs1 may exist between two PADs of the OBUF or not be used, and can be configured through configuration points. In practical applications, at the receiving end of the chip, for the differential standard LVDS and MIPI (high speed mode) protocols, it is specified that a termination resistor with a resistance value of about 100 ohms is required, and the resistor may be placed on a PCB circuit or integrated inside the FPGA 2. As shown in fig. 3, Rs2 can be placed on the PCB near PAD _ RXP and PAD _ RXN, Rs3 is integrated inside FPGA2, and Rs2 and Rs3 can only conduct one of them.

As shown in fig. 3, the related art employs a complementary MOS switch resistor or a complementary switch resistor in series with a polysilicon resistor equivalent termination resistor Rs. When the resistor is used, the NMOS gate terminal SN and the PMOS gate terminal SP can be used as the control terminals of the resistor, the switch resistor is turned on when SN is VDD and SP is VSS, and the open-end resistor is turned off when SN is VSS and SP is VDD, and the open-end resistor is very large.

However, this circuit has a problem in use: when the chip FPGA is not powered on, the FPGA1 is not powered on, then the gate voltage SP of the P transistor of the termination resistor Rs1 is 0, the PMOS is in the "on" state, if at this time, PAD _ TXP and PAD _ TXN are driven by the FPGA2, and one is at a high level, and when the other is at a low level, the turn-on of Rs1 can make the PAD _ RXP and PAD _ RXN of the FPGA2 short-circuited with Rs1 through the transmission line, thereby causing a further requirement of the working mechanism on the power-on sequence of the chip, which may affect the use of the user to a certain extent.

Therefore, in view of the above problems, the inventor proposes a termination resistor circuit, a chip and a chip communication device in the embodiment of the present application, which can be applied to two ends of a high-speed differential I/O pair of a chip, so that the two ends of the high-speed differential I/O pair of the chip are kept in an off state in a power-on process of the chip, thereby avoiding a problem that a chip system works abnormally due to a short circuit between two I/os in the power-on process of the chip, and improving the working stability of the chip.

Referring to fig. 4, fig. 4 is a schematic block diagram of a termination resistor circuit 100 according to an embodiment of the present application, where the termination resistor circuit can be applied to a high-speed differential I/O pair of a chip, and the high-speed differential I/O pair includes a first interface a and a second interface B.

As shown in fig. 4, the termination resistance circuit 100 may include: the two resistor circuits 110 are connected in series, one end of each resistor circuit 110 is electrically connected to the first interface a, the other end of each resistor circuit 110 is electrically connected to the second interface B, a target node P is arranged on a conducting wire between the two resistor circuits 110, and the two resistor circuits 110 are symmetrically arranged with respect to the target node P.

The control circuit 120 may be electrically connected to the two resistor circuits 110, respectively, and is used for controlling the two resistor circuits 110 to be in an off state during the power-on process of the chip.

In practical applications, the control circuit 120 determines whether the chip is in the power-on process according to the power-on reset signal of the chip, and if the chip is determined to be in the power-on process, the control circuit 120 may send control information to the two resistance circuits 110 to control the two resistance circuits 110 to be in the off state, so as to avoid the problem that the chip system works abnormally due to the conduction of the terminal resistance circuit 100 in the power-on process of the chip, and further improve the working stability of the chip. Wherein the control information includes, but is not limited to, a control voltage. Here, since the two resistance circuits 110 are symmetrically disposed with respect to the target node P, differential output of high-speed differential I/O of the chip can be satisfied.

As shown in fig. 5, the resistor circuit 110 may include a resistor unit 113, a first switch unit 111, and a second switch unit 112, wherein a first end M of the resistor unit 113 is electrically connected to the target node P through the first switch unit 111, and a second end of the resistor unit 113 is electrically connected to the first interface a or the second interface B. The second switching unit 112 is electrically connected to the first end M of the resistance unit 113 and the target node P, respectively.

As an example, as shown in fig. 5, the resistance unit 113 is a resistance R, on the left side of the target node, the first interface a may be connected to a node M through one resistance R, the node M is connected to a target node P through one first switching unit 111, and both ends of one second switching unit 112 are connected to the node M and the target node P, respectively, so as to be connected in parallel with the first switching unit 111. On the right side of the target node, the target node P is also connected to the node through another first switching unit 111, and both ends of another second switching unit 112 are connected to the node N and the target node P, respectively, so as to be connected in parallel with the first switching unit 111 between the node N and the target node P, and the node N may be connected to the second interface B through another resistor R. Optionally, the number of the resistors R may be one or more, and when the number of the resistors R is multiple, the connection manner between the resistors R may include series connection or/and parallel connection.

It is to be understood that the connections mentioned in the above embodiments may refer to electrical connections.

In practical applications, the second switch unit 112 may be configured to be active high, and the control circuit 120 may control the control signal S2 (e.g., voltage) for the second switch unit 112 to remain low before the chip is powered on, reset and enabled, and at this time, the second switch unit 112 is in an off state. While the first switch unit 111 may be configured to be active low, the control circuit 120 may control the control signal S1 for the first switch unit 111 to maintain the same voltage as the terminal nodes, i.e., the first interface a and the second interface B, before the chip is powered on and reset, so as to inhibit the first switch unit 111 from being turned on, i.e., the first switch unit 111 is in an off state. At this time, the first switch unit 111 and the second switch unit 112 are both in an off state, so that the terminal resistance circuit 100 is kept in the off state as a whole, thereby avoiding the problem of abnormal operation of a chip system caused by the conduction of the terminal resistance circuit 100 in the power-on process of the chip, and further improving the working stability of the chip.

As shown in fig. 6, the first switch unit 111 includes a first MOS transistor PM1(PM2), a source of the first MOS transistor PM1(PM2) is electrically connected to the first end of the resistor unit, a drain of the first MOS transistor PM1(PM2) is electrically connected to the target node P, and a gate of the first MOS transistor PM1(PM2) is electrically connected to the control circuit 120, wherein the first MOS transistor PM1(PM2) is a P-type MOS transistor.

In practical applications, the resistor unit may be a resistor R1(R2), one side of the target node P, a source of the first MOS transistor PM1 is electrically connected to the first end M of the resistor R1, a drain of the first MOS transistor PM1 is electrically connected to the target node P, and a gate of the first MOS transistor PM1 is electrically connected to the control circuit 120. Correspondingly, on the other symmetrical side of the target node P, the source of the first MOS transistor PM2 is electrically connected to the first end N of the resistor R2, the drain of the second MOS transistor PM2 is electrically connected to the target node P, and the gate of the second MOS transistor PM2 is electrically connected to the control circuit 120. Alternatively, the resistances of the resistor R1 and the resistor R2 may be 50 ohms.

As shown in fig. 6, the control circuit includes a first P-type MOS transistor PM5(PM6), a second P-type MOS transistor PM7(PM8), a first N-type MOS transistor NM3(NM4), a second N-type MOS transistor NM5(NM6), and a third N-type MOS transistor NM7(NM 8).

The source of the first P-type MOS transistor PM5(PM6) is electrically connected to the first end m (n) of the resistor unit, the drain of the first P-type MOS transistor PM5(PM6) is electrically connected to the gate of the first MOS transistor PM1(PM2), and the gate of the first P-type MOS transistor PM5(PM6) is connected to the first designated control port TILE _ VCCIO.

The source of the second P-type MOS transistor PM7(PM8) is electrically connected to the first end of the resistor unit, the drain of the second P-type MOS transistor PM7(PM8) is electrically connected to the gate of the first MOS transistor PM1(PM2), and the gate of the second P-type MOS transistor PM7(PM8) is connected to the second designated control port S2N _ VCCIO.

The drain of the first N-type MOS transistor NM3(NM4) is electrically connected to the gate of the first MOS transistor PM1(PM2), the source of the first N-type MOS transistor NM3(NM4) is electrically connected to the drain of the second N-type MOS transistor NM5(NM6), and the gate of the first N-type MOS transistor NM3(NM4) is electrically connected to the first designated control port TILE _ VCCIO.

The source of the second N-type MOS transistor NM5(NM6) is electrically connected to the drain of the third N-type MOS transistor NM7(NM8), and the gate of the second N-type MOS transistor NM5(NM6) is electrically connected to the second designated control port S2N _ VCCIO.

The source of the third N-type MOS transistor NM7(NM8) is grounded, and the gate of the third N-type MOS transistor NM7(NM8) is electrically connected to the third designated control port S2N _ VCCAUX.

It is understood that, in the termination resistor circuit of the above embodiment, the first P-type MOS transistor PM5 and the first P-type MOS transistor PM6 are symmetric about the target node P, the second P-type MOS transistor PM7 and the second P-type MOS transistor PM8 are symmetric about the target node P, the first N-type MOS transistor NM3 and the first N-type MOS transistor NM4 are symmetric about the target node P, the second N-type MOS transistor NM5 and the second N-type MOS transistor NM6 are symmetric about the target node P, and the third N-type MOS transistor NM7 and the third N-type MOS transistor NM8 are symmetric about the target node P, so connection manners of components at two sides of the target node symmetry may be referred to each other, and are not repeated herein.

As shown in fig. 6, the second switch unit 112 includes a second MOS transistor NM1(NM2), a source of the second MOS transistor NM1(NM2) is electrically connected to the target node, a drain of the second MOS transistor NM1(NM2) is electrically connected to the first end m (N) of the resistor unit, and a gate of the second MOS transistor NM1(NM2) is electrically connected to the third designated control port, wherein the second MOS transistor NM1(NM2) is an N-type MOS transistor.

In some embodiments, as shown in fig. 7, the resistance circuit 110 further includes a third switching unit 114, and the third switching unit 114 is electrically connected to the first switching unit 111 and the target node P, respectively.

It is understood that the control circuit 120 may generate the control signal S1 for the first switching unit, the control signal S2 for the second switching unit, and the control signal S3 for the third switching unit.

As shown in fig. 6, the third switching unit 114 includes a third MOS transistor PM3(PM4), a source of the third MOS transistor PM3(PM4) is electrically connected to a drain of the first MOS transistor PM1(PM2), a drain of the third MOS transistor PM3(PM4) is electrically connected to a target node, and a gate of the third MOS transistor PM3(PM4) is electrically connected to the fourth designated control port S1P _ VCCAUX, where the third MOS transistor PM3(PM4) is a P-type MOS transistor.

In this embodiment, by making the resistor circuit 110 further include the third switching unit 114, and the third switching unit 114 is electrically connected to the first switching unit 111 and the target node P, respectively, after the VCCAUX is powered on, the second switching unit is kept in the off state before the switch is enabled, so as to further ensure that the termination resistor circuit is in the off state during the chip power-on process.

In some embodiments, as shown in fig. 7, the termination resistance circuit 100 may further include: and one end of the filter capacitor unit 130 is electrically connected to the target node P, and the other end of the filter capacitor unit 130 is grounded.

Considering that in high-speed application, especially when the data transmission rate reaches above 1Gbps, the difference between the driver output impedance and the impedance of the signal path may cause reflection of incident edge reaching the driver output end from the transmission medium, and weaken the driving capability of the driver, and at the same time, the output common mode of the signal may change greatly, and such high-frequency common mode voltage change is difficult to be corrected back through common mode feedback, and finally the data transmission rate is limited.

It should be noted that the first switch unit, the second switch unit, the third switch unit, the filter capacitor unit and the control circuit in the above embodiments may also be implemented by other embodiments, for example, the second switch unit may be formed by two NMOS transistors or a plurality of NMOS transistors connected in series; the control circuit can be realized by MOS in different series sequences; the filter capacitor unit may be implemented by other types of capacitors, such as metal capacitors and variable capacitors in a CMOS process, and specific embodiments thereof are not limited herein.

It should be noted that, if the termination resistor circuit of the above embodiment is applied to low frequency applications, the filter capacitor unit 130 can be omitted, because the large filter capacitor consumes chip area.

In addition, the termination resistor circuit of this embodiment may also be applied to I/O common mode feedback for detecting a common mode voltage of a differential I/O, and when the MOS switch resistor control terminal is in an disabled state, it may be ensured that both ends of the I/O are in an off state, and compared with a conventional mode in which a NMOS switch is connected in series with a resistor, the system is more reliable.

As shown in fig. 7, the termination resistor circuit provided in this embodiment may include: two resistance circuits 110, two resistance circuits 110 are connected in series each other, and two resistance circuits 110 one end after connecting in series is connected with first interface A, and the other end is connected with second interface B, and two resistance circuits 110 are around target node P symmetry setting. Each of the two resistance circuits 110 includes a first switch unit 111, a second switch unit 112, a resistance unit 113, and a third switch unit 114. The first switch unit 111, the second switch unit 112, and the resistor unit 113 are sequentially connected in series, one end of the series connection is connected to the first interface a, the other end of the series connection is connected to the target node P, and the third switch unit 114 is connected in parallel to the first switch unit 111 and the third switch unit 114.

In practical applications, please refer to fig. 6 again, the two symmetrical first switch units 111 may be formed by PMOS transistors PM1/PM2, and PM1 and PM2 have the same size; the two symmetrical third switch units 112 are composed of NMOS transistors NM1/NM2, and NM1 and NM2 have the same size; the two symmetrical third switch units 114 are formed by PMOS tubes PM3/PM4, and the PM3 and the PM4 are the same in size; the switch control circuit 120 on the left side of the line in the termination resistance circuit 100 may be composed of PM5, PM7, NM3, NM5, NM 7; the switch control circuit 120 on the right side of the line in the termination resistance circuit may be composed of PM6, PM8, NM4, NM6, NM8, where PM5 and PM6, PM7 and PM8, NM3 and NM4, NM5 and NM6, NM7 and NM8 are the same size; the filter capacitor unit consists of NM 9; the resistance unit 113 may include a resistor R1 and a resistor R2, and the resistor R1 and the resistor R2 are the same size and are symmetrical.

As shown in fig. 6, one end of the resistor R1 is connected to the first interface a, where the first interface a is one pin PAD of the high-speed differential I/O pair, the other end of the resistor R1 is connected to the M node, PM1 is connected in series with PM3, the source of PM1 is connected to the M node, the drain of PM3 is connected to the target node P, and the drain of PM1 is connected to the source of PM 3; NM1 is connected in parallel with PM1 and PM3 after series connection, NM1 source is connected to common mode node P end, NM1 drain is connected to node M; the source of PM5 of control circuit 120 is connected to node M, the drain of PM5 is connected to gate SP1 of PM 1; the PM7 of the first switch control circuit is connected with the PM5 in parallel, the source electrode of the PM7 is connected to the M node, and the drain electrode of the PM7 is connected to the SP 1; three NMOS tubes of NM3, NM5 and NM7 of the control circuit are connected in series, the drain of NM3 is connected to SP1, the source is connected to the drain of NM5, the source of NM5 is connected to the drain of NM7, and the source of NM7 is connected to the ground line.

As shown in fig. 6, one end of the resistor R2 is connected to the second interface B, where B is the other PAD of the high-speed differential I/O pair, the other end of the resistor R2 is connected to the N node, PM2 is connected in series with PM4, the source of PM2 is connected to the N node, the drain of PM4 is connected to the common mode node P, and the drain of PM2 is connected to the source of PM 4; NM2 is connected in parallel with PM2 and PM4 after series connection, the source of NM2 is connected to the P end of the target node, and the drain of NM2 is connected to the node N; the source of the PM6 of the control circuit 120 is connected to the N node, and the drain of the PM6 is connected to the gate SP2 of the PM 2; PM8 of control circuit 120 is connected in parallel with PM6, the source of PM8 is connected to node N, the drain of PM8 is connected to SP 2; three NMOS tubes of NM4, NM6 and NM8 of the control circuit are connected in series, the drain of NM4 is connected to SP2, the source is connected to the drain of NM6, the source of NM6 is connected to the drain of NM8, and the source of NM8 is connected to the ground line.

The filter capacitor unit may be formed by NM9, a gate of NM9 is connected to a target node P, and a source and drain of NM9 are connected to ground to form an NMOS capacitor, where the target node P is a common mode node.

Wherein, the gates of the PM3/PM4 of the third switch unit 114 are connected to the input control terminal S1P _ VCCAUX of the termination resistor circuit, the gates of the NM1/NM2 of the second switch unit 112 are connected to the input control terminal S1N _ VCCAUX of the termination resistor circuit, the gates of the PM5/PM6 and NM3/NM4 of the control circuit 120 are connected to the input control terminal TILE _ VCCIO of the termination resistor circuit, the gates of the PM7/PM8 and NM5/NM6 of the control circuit 120 are connected to the input control terminal S2N _ VCCIO of the termination resistor circuit, and the gates of the NM7/NM8 of the control circuit 120 and the gates of the NM1/NM2 of the second switch unit 112 are connected to S1N _ VCCAUX.

S1N _ VCCAUX in fig. 6 may be a first control positive terminal of the termination resistor circuit of the present embodiment, and a high level of S1N _ VCCAUX is active, where VCCAUX is an auxiliary power supply voltage of the IOB module of the FPGA chip; the input control terminal S1P _ VCCAUX is the first control negative terminal of the termination resistor circuit of this embodiment, the low level of S1P _ VCCAUX is active, the voltage value of S1P _ VCCAUX is VCCAUX, PM3/PM4 of the third switching unit 114 is turned off, and when the voltage value of S1P _ VCCAUX is VSS, PM3/PM4 of the third switching unit 114 is turned on.

In fig. 6, TILE _ VCCIO is a second control terminal of the termination resistor circuit in this embodiment, TILE _ VCCIO may be indirectly connected to the power supply VCCIO of I/O through a circuit design, VCCIO is a main power supply of the IOB module of the FPGA chip, generally, VCCIO may support different voltage domains, for example, 1.8V, 1.5V, 1.2V, etc. may be taken for different standard VCCIOs, while the auxiliary power supply VCCAUX is generally a fixed voltage, for example, VCCAUX is 1.8V, the gate of NM1/NM2 of the second switch unit 112 is controlled by VCCAUX voltage, which can ensure that the on-resistance of NM1 and NM2 does not change due to the change of the gate voltage, so as to reduce the sensitivity of the termination resistor, and make the equivalent termination resistor relatively stable.

In fig. 6, S2N _ VCCIO is the third control terminal of the termination resistor circuit in this embodiment, and may be configured to be active high, and the power domain is VCCIO.

In practical applications, the operation process of the termination resistor circuit of this embodiment may be as follows:

before power-on of VCCAUX and VCCIO, voltages of all control terminals are in a "0" state, and assuming that at this time, I/O pairs a and B of the FPGA are driven by an external circuit, pin a is in a "high" state, pin B is also in a "high" state, then nodes M and N are both in a high level state, since the chip is not powered on, gate voltages of PM5/PM6 and PM7/PM8 are in a "0" state, and PM5/PM6 and PM7/PM8 are both turned on, so that gates SP1 and SP2 of PM2 and PM1 of the first switch unit 111 are respectively connected to the M and N nodes and are in a "high" state, and thus PM1 and PM2 are in an off state before the chip is not powered on. Further, since S1N _ VCCAUX is in "0" state before VCCAUX is power-on reset, NM1/NM2 is in off state, and thus the terminal resistance across AB is in off state.

In the power-on process of the chip, the S1N _ VCCAUX, the S1P _ VCCAUX and the S2N _ VCCIO are controlled by the configuration point of the terminal resistor, and the TILE _ VCCIO follows the VCCIO power supply, so that the terminal resistor is always kept in a disconnected state before being enabled, and the problem of system abnormity caused by terminal short circuit in the power-on process is avoided.

When the chip is powered on and the configuration point is enabled, i.e. S1N _ VCCAUX ═ VCCAUX, S1N _ VCCAUX ═ VSS, TILE _ VCCIO ═ VCCIO, S2N _ VCCIO ═ VCCIO, SP1 and SP2 are pulled down to VSS, PM1/PM2, PM3/PM4 and NM1/NM2 are all turned on, the termination resistors are in the on state, and simultaneously, the common mode node P and the ground are connected with the NMOS filter capacitor NM9, and NM9 can make the common mode voltage of the differential I/O signals more stable in high frequency application.

Therefore, in this embodiment, by applying the termination resistor circuit of this embodiment to the termination resistors at the two ends of the high-speed differential I/O pair, the termination resistors are kept in the off state before the power-on reset of the chip or the entire application system is completed, so that the problem of system operation abnormality caused by the short circuit of the two I/os in the power-on process can be avoided. Meanwhile, a filter capacitor is added at a common mode point of the terminal resistor circuit, so that the problem of high-frequency common mode disturbance can be effectively solved, the common mode voltage of the I/O pair of the driving signals or the input signals at two ends is more stable, and the requirements of communication protocols of differential standards such as LVDS or MIPI are met.

Referring to fig. 8, fig. 8 is a schematic structural diagram of a chip according to an embodiment of the present application, where the chip 200 may include: the terminal resistor circuit comprises an FPGA chip body 210 and the terminal resistor circuit 100 of the embodiment.

The high-speed differential I/O pair of the FPGA chip body 210 includes a first interface PAD _ TXP and a second interface PAD _ TXN, and the termination resistor circuit 100 is electrically connected to the first interface PAD _ TXP and the second interface PAD _ TXN, respectively.

The working process of the chip 200 may refer to the working process of the termination resistance circuit 100 in the above embodiments, and therefore is not described herein.

Referring to fig. 9, fig. 9 shows a schematic structural diagram of a chip communication device according to an embodiment of the present invention, the chip communication device 300 may include a first FPGA chip 310, a second FPGA chip 320, a first transmission line 330, a second transmission line 340, and three termination resistor circuits 100 according to the above embodiments, where the three termination resistor circuits 100 may include a first termination resistor circuit 101, a second termination resistor circuit 102, and a third termination resistor circuit 103, a high-speed differential I/O pair of the first FPGA chip 310 includes a first port PAD _ p and a first port PAD TXN, and a high-speed differential I/O pair of the second FPGA chip 320 includes a third port PAD _ RXP and a fourth port PAD rxrxn.

The first port PAD _ TXP of the first FPGA chip 310 is electrically connected to the third port PAD _ RXP of the second FPGA chip 320 through a first transmission line 330, and the first port PAD _ TXN of the first FPGA chip 310 is electrically connected to the fourth port PAD _ RXN of the second FPGA chip 320 through a second transmission line 340.

The first terminal resistor circuit 101 is electrically connected to the first port PAD _ TXP of the first FPGA chip 310 and the first port PAD _ TXN of the first FPGA chip 310, respectively, and the first terminal resistor circuit 101 is integrated in the first FPGA chip 310.

The second terminal resistor circuit 102 is electrically connected to a third port PAD _ RXP of the second FPGA chip 320 and a fourth port PAD _ RXN of the second FPGA chip 320, respectively, and the second terminal resistor circuit 102 is disposed outside the second FPGA chip 320.

The third terminal resistor circuit 103 is electrically connected to the third port PAD _ RXP of the second FPGA chip 320 and the fourth port PAD _ RXN of the second FPGA chip 320, respectively, and the third terminal resistor circuit 103 is integrated in the second FPGA chip 320.

The working process of the chip communication device 300 can refer to the working process of the termination resistor circuit 100 in the above embodiments, and therefore is not described herein.

To sum up, the terminal resistance circuit, the chip and the chip communication device that this application embodiment provided, through the terminal resistance circuit that two resistance circuit and control circuit constitute, wherein: one end of the two resistor circuits after being connected in series is electrically connected with a first interface of a high-speed differential I/O pair of the chip, the other end of the two resistor circuits after being connected in series is electrically connected with a second interface of the high-speed differential I/O pair of the chip, wherein a target node is arranged on a lead between the two resistor circuits, the two resistor circuits are symmetrically arranged relative to the target node, and the control circuit is respectively electrically connected with the two resistor circuits and is used for controlling the two resistor circuits to be in a disconnection state in the power-on process of the chip, so that the problem that the two I/O interfaces of the chip cause abnormal system work due to short circuit in the power-on process can be avoided, and the working stability of a chip system is improved. Meanwhile, a filter capacitor is added at a common mode point of the terminal resistor circuit, so that the problem of high-frequency common mode disturbance can be effectively solved, the common mode voltage of the I/O pair of the driving signals or the input signals at two ends is more stable, and the requirements of communication protocols of differential standards such as LVDS or MIPI are met.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit the same; although the present application has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not necessarily depart from the spirit and scope of the corresponding technical solutions in the embodiments of the present application.

Claims

1. A termination resistance circuit for use with a high speed differential I/O pair of a chip, the high speed differential I/O pair including a first interface and a second interface, the termination resistance circuit comprising:

one end of the two resistor circuits after being connected in series is electrically connected with the first interface, and the other end of the two resistor circuits after being connected in series is electrically connected with the second interface, wherein a lead between the two resistor circuits is provided with a target node, and the two resistor circuits are symmetrically arranged relative to the target node; and

and the control circuit is respectively electrically connected with the two resistance circuits and is used for controlling the two resistance circuits to be in a disconnected state in the power-on process of the chip.

2. The termination resistor circuit according to claim 1, wherein the resistor circuit comprises a resistor unit, a first switch unit and a second switch unit, a first end of the resistor unit is electrically connected to the target node through the first switch unit, and a second end of the resistor unit is electrically connected to the first interface or the second interface;

the second switch unit is electrically connected with the first end of the resistance unit and the target node respectively.

3. The circuit of claim 2, wherein the first switch unit comprises a first MOS transistor, a source of the first MOS transistor is electrically connected to the first end of the resistor unit, a drain of the first MOS transistor is electrically connected to the target node, and a gate of the first MOS transistor is electrically connected to the control circuit, wherein the first MOS transistor is a P-type MOS transistor.

4. The termination resistor circuit according to claim 3, wherein the control circuit comprises a first P-type MOS transistor, a second P-type MOS transistor, a first N-type MOS transistor, a second N-type MOS transistor and a third N-type MOS transistor;

the source electrode of the first P-type MOS tube is electrically connected with the first end of the resistor unit, the drain electrode of the first P-type MOS tube is electrically connected with the grid electrode of the first MOS tube, and the grid electrode of the first P-type MOS tube is connected with a first appointed control port;

the source electrode of the second P-type MOS tube is electrically connected with the first end of the resistor unit, the drain electrode of the second P-type MOS tube is electrically connected with the grid electrode of the first MOS tube, and the grid electrode of the second P-type MOS tube is connected with a second specified control port;

the drain electrode of the first N-type MOS tube is electrically connected with the grid electrode of the first MOS tube, the source electrode of the first N-type MOS tube is electrically connected with the drain electrode of the second N-type MOS tube, and the grid electrode of the first N-type MOS tube is electrically connected with the first appointed control port;

the source electrode of the second N-type MOS tube is electrically connected with the drain electrode of the third N-type MOS tube, and the grid electrode of the second N-type MOS tube is electrically connected with the second designated control port;

and the source electrode of the third N-type MOS tube is grounded, and the grid electrode of the third N-type MOS tube is electrically connected with the third appointed control port.

5. The termination resistor circuit according to claim 2, wherein the second switch unit comprises a second MOS transistor, a source of the second MOS transistor is electrically connected to the target node, a drain of the second MOS transistor is electrically connected to the first end of the resistor unit, and a gate of the second MOS transistor is electrically connected to the third designated control port, wherein the second MOS transistor is an N-type MOS transistor.

6. The termination resistor circuit according to claim 2, further comprising a third switching unit electrically connected to the first switching unit and the target node, respectively.

7. The termination resistor circuit according to claim 6, wherein the third switching unit comprises a third MOS transistor, a source of the third MOS transistor is electrically connected to a drain of the first MOS transistor, a drain of the third MOS transistor is electrically connected to the target node, and a gate of the third MOS transistor is electrically connected to a fourth designated control port, wherein the third MOS transistor is a P-type MOS transistor.

8. The termination resistor circuit according to any of claims 1 to 7, further comprising:

and one end of the filter capacitor unit is electrically connected with the target node, and the other end of the filter capacitor unit is grounded.

9. A chip comprising an FPGA chip body and the termination resistor circuit of any one of claims 1 to 8, wherein the high-speed differential I/O pair of the FPGA chip body comprises a first interface and a second interface, and wherein the termination resistor circuit is electrically connected to the first interface and the second interface, respectively.

10. A chip communication device, comprising a first FPGA chip, a second FPGA chip, a first transmission line, a second transmission line, and three termination resistor circuits according to any one of claims 1 to 8, wherein the three termination resistor circuits comprise a first termination resistor circuit, a second termination resistor circuit, and a third termination resistor circuit, wherein the high-speed differential I/O pair of the first FPGA chip comprises a first port and a second port, and wherein the high-speed differential I/O pair of the second FPGA chip comprises a third port and a fourth port;

the first port of the first FPGA chip is electrically connected with the third port of the second FPGA chip through the first transmission line, and the second port of the first FPGA chip is electrically connected with the fourth port of the second FPGA chip through the second transmission line;

the first terminal resistance circuit is electrically connected with a first port of the first FPGA chip and a second port of the first FPGA chip respectively, and the first terminal resistance circuit is integrated in the first FPGA chip;

the second terminal resistance circuit is electrically connected with a third port of the second FPGA chip and a fourth port of the second FPGA chip respectively, and the second terminal resistance circuit is arranged outside the second FPGA chip;

the third terminal resistance circuit is electrically connected with the third port of the second FPGA chip and the fourth port of the second FPGA chip respectively, and the third terminal resistance circuit is integrated in the second FPGA chip.