CN112713191A

CN112713191A - Ring gate nano CMOS structure and preparation method thereof

Info

Publication number: CN112713191A
Application number: CN202011537255.3A
Authority: CN
Inventors: 张鹤鸣
Original assignee: Individual
Current assignee: Individual
Priority date: 2020-12-23
Filing date: 2020-12-23
Publication date: 2021-04-27

Abstract

The invention discloses a gate-all-around nano CMOS structure and a preparation method thereof, wherein the gate-all-around nano CMOS structure comprises an nMOS and a pMOS, and is characterized in that the nMOS comprises a first nano body structure arranged on a semiconductor substrate and a first gate electrode surrounding the first nano body structure, the pMOS comprises a second nano body structure arranged on the semiconductor substrate and a second gate electrode surrounding the second nano body structure, and the first nano body structure and the second nano body structure are formed by semiconductor materials with the same conductivity type; the first gate electrode and the second gate electrode are formed of a conductive material having the same work function. The gate-all-around nano CMOS reduces the process steps for preparing the gate-all-around nano CMOS and the process flow, thereby reducing the process difficulty and the preparation cost and being beneficial to improving the performance and the reliability of the gate-all-around nano CMOS and the integrated circuit thereof.

Description

Ring gate nano CMOS structure and preparation method thereof

Technical Field

The invention belongs to the technical field of semiconductors, and particularly relates to a ring grid nano CMOS structure and a preparation method thereof.

Background

As integrated circuit feature sizes break through 10nm, short channel effects can cause transistor performance to become very unstable. Meanwhile, the leakage current is significantly increased due to the quantum tunneling effect, further deteriorating the performance of the device. Furthermore, the transistor fabrication process is more complex at nanometer dimensions, which makes the development of moore's law challenging.

In order to suppress the short channel effect, researchers have proposed various novel nano device structures, including double-gate, triple-gate, and gate-all-around structures, which are expected to improve the performance of the MOSFET as the size of the MOSFET is continuously reduced.

Among the novel device structures, a gate-all-around nanowire field effect transistor (GAA NWFET) and a gate-all-around nanowire field effect transistor (GAA NSFET) can better inhibit short channel effects, so that the novel device structures have more development potential, are compatible with the current CMOSFET process, and are expected device structures of the next generation of CMOS.

However, the gate-all-around nanowire/chip field effect transistor has the problems of multiple manufacturing steps, complex technology, higher cost than the conventional CMOS and the like.

Disclosure of Invention

In order to solve the above problems in the prior art, the present invention provides a ring gate nano CMOS structure and a method for manufacturing the same. The technical problem to be solved by the invention is realized by the following technical scheme:

a ring-gated nano-CMOS structure comprising an nMOS comprising a first nano-body structure disposed on a semiconductor substrate and a first gate electrode surrounding the first nano-body structure, and a pMOS comprising a second nano-body structure disposed on the semiconductor substrate and a second gate electrode surrounding the second nano-body structure, wherein,

the first and second nanostructure are formed of semiconductor material of the same conductivity type;

the first gate electrode and the second gate electrode are formed of a conductive material having the same work function.

In one embodiment of the present invention, the material of the first and second nano-body structures is an n-type semiconductor material with the same doping concentration, the first source region and the first drain region of the nMOS are doped n-type, and the second source region and the second drain region of the pMOS are doped p-type.

In one embodiment of the present invention, work functions of the first gate electrode and the second gate electrode are in a range of 4.6 to 5.1 eV.

In one embodiment of the present invention, the material of the first and second nano-body structures is a p-type semiconductor material with the same doping concentration, the first source region and the first drain region of the nMOS are doped n-type, and the second source region and the second drain region of the pMOS are doped p-type.

In one embodiment of the present invention, work functions of the first gate electrode and the second gate electrode are in a range of 4.1 to 4.5 eV.

In an embodiment of the present invention, the first nanoparticle structure includes at least one first nanoparticle, when the number of the first nanoparticles is greater than or equal to two, all the first nanoparticles are arranged in a stacked manner in a vertical direction or arranged in a same layer manner in a horizontal direction, and the second nanoparticle structure includes at least one second nanoparticle, when the number of the second nanoparticles is greater than or equal to two, all the second nanoparticles are arranged in a stacked manner in a vertical direction or arranged in a same layer manner in a horizontal direction.

In one embodiment of the invention, the first nano-bodies and the second nano-bodies are in the same layer or adjacent layers.

In one embodiment of the invention, the first and second nano-bodies are nano-sheets or nano-wires.

An embodiment of the present invention further provides a method for manufacturing a gate-all-around nano CMOS structure, which is used for manufacturing the gate-all-around nano CMOS structure according to any one of the embodiments, and the method includes:

selecting a semiconductor substrate;

forming a first material lamination layer and a second material lamination layer on the semiconductor substrate;

etching the first material stack and the second material stack to form a first nanostructure and a second nanostructure, wherein the first nanostructure and the second nanostructure have a same conductivity type;

and forming a gate dielectric layer and a first gate electrode and a second gate electrode with the same work function around the first nano body structure and the second nano body structure.

In one embodiment of the present invention, forming a first material stack and a second material stack of the same conductivity type on the semiconductor substrate includes:

forming a first material layer and a second material layer which are alternately stacked on the semiconductor substrate;

and etching the first material layer and the second material layer which are alternately arranged to form the first material lamination and the second material lamination.

The invention has the beneficial effects that:

the nMOS and pMOS of the present invention are fabricated using semiconductor materials of the same conductivity type and preferably the same doping concentration, so that there is no need to separately dope the semiconductor materials forming the nanowires/sheets. Meanwhile, the gate electrodes of the nMOS and the pMOS are made of conductive materials with the same work function, preferably the same conductive material, so that the gate electrode of the nMOS and the gate electrode of the pMOS do not need to be prepared respectively, the gate-all-around nano CMOS structure reduces the process steps for preparing the gate-all-around nano CMOS, reduces the process procedures, reduces the preparation cost and the process difficulty, and is greatly beneficial to enhancing the performance and the reliability of the gate-all-around nano CMOS and the integrated circuit thereof.

The present invention will be described in further detail with reference to the accompanying drawings and examples.

Drawings

FIG. 1 is a schematic diagram of a gate-all-around nanowire/chip CMOS with nMOS and pMOS in the same layer provided by the prior art;

FIG. 2 is a schematic diagram of a prior art CMOS structure with nMOS and pMOS on top and bottom adjacent layers;

FIG. 3 is a schematic diagram of a ring-gate nano CMOS structure according to an embodiment of the present invention;

FIG. 4 is a schematic structural diagram of another gate-all-around nano CMOS structure provided by the embodiment of the invention;

FIG. 5 is a schematic diagram of a gate-all-around nano CMOS device according to an embodiment of the present invention;

fig. 6a to fig. 6n are schematic diagrams illustrating a process for fabricating stacked same-layer gate-all-around nanowire/CMOS chip according to an embodiment of the present invention;

fig. 7a to 7d are schematic diagrams illustrating a process for fabricating another stacked-layer gate-all-around nanowire/CMOS chip according to an embodiment of the present invention;

FIGS. 8a to 8d are schematic diagrams illustrating a process for fabricating a stacked-layer gate-all-around nanowire/CMOS chip according to an embodiment of the present invention;

FIGS. 9a to 9c are schematic diagrams illustrating a process for fabricating another stacked-layer gate-all-around nanowire/CMOS chip according to an embodiment of the present invention;

10 a-10 j are schematic diagrams illustrating a process for fabricating another stacked adjacent layer gate-all-around nanowire/CMOS chip according to an embodiment of the present invention;

fig. 11a to 11d are schematic diagrams illustrating a process of manufacturing another stacked adjacent-layer gate-all-around nanowire/CMOS chip according to an embodiment of the present invention.

Detailed Description

The present invention will be described in further detail with reference to specific examples, but the embodiments of the present invention are not limited thereto.

For better understanding of the present solution, prior to introducing the gate-all-around nano CMOS structure provided by the present invention, a description will be given to the existing stacked gate-all-around nanowire/CMOS chip structure.

The gate-all-around (GAA) is a gate metal surrounding the channel region of the MOSFET, the difference between the gate-all-around nanowire and the gate-all-around nanosheet is that the gate-all-around nanowire is a linear semiconductor, the gate-all-around nanowire is a sheet semiconductor, the nanowire is a nano-scale linear semiconductor material, and the nanosheet is a nano-scale thick sheet semiconductor material.

The ring grid nanowire/sheet CMOS is formed by interconnecting ring grid nanowire/sheet nMOS and ring grid nanowire/sheet pMOS drain electrodes, the nanowire/sheet of the ring grid nMOS is a p-type semiconductor, and the nanowire/sheet of the ring grid pMOS is an n-type semiconductor. The nanowire/sheet of the gate-all-around nanowire/sheet CMOS can have a single layer or multiple layers, and when the nanowire/sheet is multiple layers, the nanowire/sheet is a stacked gate-all-around nanowire/sheet CMOS.

In general, there are two types of stacked gate-all-around nanowire/sheet CMOS structures, the first is nMOS nanowires/sheets and pMOS nanowires/sheets on the same semiconductor layer, for example, see fig. 1, and the second is nMOS nanowires/sheets and pMOS nanowires/sheets on adjacent upper and lower semiconductor layers, for example, see fig. 2. The nano-wire is a nano-linear semiconductor material, and the nano-sheet is a nano-thick sheet semiconductor material.

For a gate-all-around nanowire/sheet CMOS structure, the nanowires/sheets of nMOS are made of p-type semiconductor material, and the nanowires/sheets of pMOS are made of n-type semiconductor material. The invention takes the method that after a fin structure is formed, a nanowire/sheet is prepared by a p-type semiconductor material and a nanowire/sheet is prepared by an n-type semiconductor material in the prior art as an example, concretely, processes such as ion implantation or doping and the like are carried out after the fin structure is formed on a substrate, and a p-type fin for preparing nMOS and an n-type fin for preparing pMOS are respectively formed, namely, the fin of the nMOS is p-type, so that p-type doping is needed, a medium is needed to shield a pMOS region during preparation, and the corresponding processes are adopted to carry out the p-type doping on the fin of the nMOS region so as to prepare the p-type fin; and the fins of the pMOS are n-type, so n-type doping is needed, a medium is needed to shield the nMOS region during preparation, and the corresponding process is adopted to perform n-type doping on the fins of the pMOS region to prepare the n-type fins. Wherein the fin is as a structure forming a nanowire/sheet.

In addition, when the gate electrode is prepared, firstly, gate dielectrics are deposited on the surfaces of the nanowire/sheet of the nMOS and the nanowire/sheet of the pMOS at the same time, and then, gate metals with different work functions are respectively deposited on the surfaces of the gate dielectrics of the nMOS and the gate dielectrics of the pMOS so as to respectively form the gate electrode of the nMOS and the gate electrode of the pMOS.

The ring grid nanosheet is different from the ring grid nanowire only in that the former is nanosheet-shaped, and the latter is nanowire-shaped. Therefore, when the stacked ring gate nano-sheet CMOS is prepared, the stacked ring gate nano-sheet CMOS is different from the stacked ring gate nano-wire CMOS only in the shape of the nano-sheet and the nano-wire.

In summary, in the current manufacturing technology, both the stacked gate-all nanosheets CMOS and the stacked gate-all nanowire CMOS have the following two disadvantages:

1. the nanosheet/wire of the ring grid nMOS and the nanosheet/wire of the ring grid pMOS need semiconductor materials of different conductive types;

2. the gate electrode of the ring gate nanosheet/wire nMOS and the gate electrode of the ring gate nanosheet/wire pMOS require conductive materials of different work functions.

Although only two technologies are used, the implementation of the two key technologies requires independent steps, methods and processes, and the processes are complicated, which not only increases the cost of the process, but also introduces process defects, which affect the performance and reliability of the devices and circuits, and thus, the two key technologies constitute a disadvantage of consistency for various types of ring-gate nanowires/CMOS chips, including stacked ring-gate nanowires/CMOS chips.

Example one

Referring to fig. 3, fig. 3 is a schematic view of a ring-gate nano CMOS structure according to an embodiment of the present invention, wherein fig. 3(1), fig. 3(3) are cross-sectional views of side views, and fig. 3(2) are partial cross-sectional views of front views. For the above reasons, the present embodiment provides a gate-all-around nano-CMOS structure including an nMOS including a first nano-body structure 20 disposed on a semiconductor substrate 10 and a first gate electrode 30 surrounding the first nano-body structure 20, and a pMOS including a second nano-body structure 40 disposed on the semiconductor substrate 10 and a second gate electrode 50 surrounding the second nano-body structure 40, wherein the first nano-body structure 20 and the second nano-body structure 40 are formed of semiconductor materials of the same conductivity type; the first gate electrode 30 and the second gate electrode 50 are formed of conductive materials having the same work function. It is emphasized that the thickness and doping concentration of the first and

second nanostructure

20, 40 should meet the requirement of complete depletion by gate electrode work function.

In one embodiment, the material of the first and second nano-

body structures

20 and 40 is an n-type semiconductor material with the same doping concentration, the first source region 60 and the first drain region 70 of nMOS are n-type doped, and the second source region 80 and the second drain region 90 of pMOS are p-type doped.

Further, if the materials of the first and second nano-

body structures

20 and 40 are n-type semiconductor materials with the same doping concentration, the same conductive material with the work function near the valence band top of the n-type semiconductor material is used as the first and

second gate electrodes

30 and 50, and the work functions of the first and

second gate electrodes

30 and 50 are selected to completely deplete the nano-body structures, preferably, the work functions of the first and

second gate electrodes

30 and 50 are in the range of 4.6 to 5.1eV, and the specific value is determined by the parameters of the nano-body structures, such as the thickness and the doping concentration, and is not limited herein.

In another embodiment, the material of the first and second nano-

body structures

20 and 40 is a p-type semiconductor material with the same doping concentration, the first source region 60 and the first drain region 70 of nMOS are n-type doped, and the second source region 80 and the second drain region 90 of pMOS are p-type doped.

Further, if the first and

second nanostructure

20 and 40 are both made of p-type semiconductor material with the same doping concentration, the first and

second gate electrodes

30 and 50 are made of the same conductive material with the work function near the conduction band bottom of the p-type semiconductor material, and the work functions of the first and

second gate electrodes

30 and 50 are selected to completely deplete the nanostructure, preferably, the work functions of the first and

second gate electrodes

30 and 50 range from 4.1 eV to 4.5eV, and the specific value is determined by the parameters of the thickness and the doping concentration of the nanostructure, which is not limited herein.

In this embodiment, the first nanoparticle structure includes at least one first nanoparticle, when the number of the first nanoparticles is greater than or equal to two, all the first nanoparticles are arranged in a stacking manner in a vertical direction or arranged in a same layer manner in a horizontal direction, the second nanoparticle structure includes at least one second nanoparticle, and when the number of the second nanoparticles is greater than or equal to two, all the second nanoparticles are arranged in a stacking manner in a vertical direction or arranged in a same layer manner in a horizontal direction.

In this embodiment, when the number of the first nanobodies and the second nanobodies is greater than or equal to two, there are two arrangement manners, one is that a plurality of first nanobodies or a plurality of second nanobodies are arranged in a stacking manner in a vertical direction, where the vertical direction is as shown in fig. 3, and the other is that a plurality of first nanobodies or a plurality of second nanobodies are arranged in the same layer in a horizontal direction. In addition, the first nano body and the second nano body may be in the same layer or in adjacent layers, when in the same layer, the semiconductor materials adopted by the first nano body and the second nano body are the same, for example, both are Si, and when in adjacent layers, the semiconductor materials adopted by the first nano body and the second nano body are different, for example, the material of the first nano body is Si, and the material of the second nano body is Ge or SiGe. For example, referring to fig. 3 and 4, fig. 3 is a structure in which the first nano-body and the second nano-body are located in the same layer, fig. 4 is a structure in which the first nano-body and the second nano-body are located in adjacent layers, wherein fig. 3(2) and fig. 4(1), (2) and (3) are schematic cross-sectional views of nano-body portions.

Further, the first nano-body and the second nano-body are nano-sheets or nano-wires.

In the present embodiment, the semiconductor substrate 10 may be a bulk silicon substrate or an SOI substrate. The semiconductor substrate 10 may be a semiconductor material of Si, SiGe, Ge, SiC, III-IV group, or the like.

Referring to fig. 5, fig. 5 is a schematic diagram of a ring-gate nano CMOS according to an embodiment of the present invention. As can be seen from the gate-all-around nano CMOS structure provided in this embodiment and FIG. 5, when a positive voltage V is applied to the power supply_DAnd when the input end is not connected with voltage, namely when the input end is suspended, the nMOS and the pMOS are in an off state, and the ring gate nano CMOS does not work. When the input end is connected with 0V, the pMOS is conducted, and the output end is at a high level. Then, as the input voltage gradually increases from 0V, the pMOS gradually turns off, and the nMOS gradually turns on, and when the pMOS is off and the nMOS is on, a low level is output.

The first nano-body structure of nMOS and the second nano-body structure of pMOS of this embodiment are prepared from semiconductor materials of the same conductivity type, and have the same or similar doping concentration, preferably the same doping concentration, that is, the first nano-body structure of nMOS and the second nano-body structure of pMOS are prepared on p-type semiconductor material with a certain doping concentration, or are prepared on n-type semiconductor material with a certain doping concentration, so that there is no need to prepare semiconductor materials of different conductivity types for the nano-sheet/wire of ring-gate nMOS and the nano-sheet/wire of ring-gate pMOS, respectively, so that the ring-gate nano-CMOS of this embodiment can omit the process of preparing semiconductor materials of different conductivity types, although the process of preparing n-type semiconductor material or p-type semiconductor material is omitted on the surface, but can reduce many process steps, which shortens the process cycle, it is very beneficial and advantageous to control the process error, reduce the chip process cost, and improve the performance and reliability of the device and circuit, and this problem is just one of the core problems that the industry has paid attention to and paid long attention to. Meanwhile, because the gate electrodes of the nMOS and the pMOS of the embodiment are made of the same conductive material or preferably the same conductive material, when the same conductive material is used as the gate electrode, the gate electrode of the nMOS and the gate electrode of the pMOS do not need to be separately prepared. In addition, the gate electrode region of the gate-all-around nano CMOS is a sensitive region, the gate electrode controls the performance of the CMOS, and the process of preparing the gate electrode can influence the performance of the CMOS, so that the gate electrode of the nMOS and the gate electrode of the pMOS are made of the same conductive material with the same work function and only need to be prepared once, and the performance and the reliability of the gate-all-around nano CMOS circuit can be improved.

In summary, in the present embodiment, two key process technologies of the gate-all-around nano CMOS are simplified through the above manner, the process steps for preparing the gate-all-around nano CMOS are reduced, the process procedure and the process difficulty are reduced, and thus the preparation cost can be reduced, and thus the yield, performance and reliability of the gate-all-around nano CMOS and the integrated circuit thereof can be improved. In addition, the gate-all-around nano CMOS structure provided by the embodiment can also increase the threshold voltage regulation dimension and improve the switching speed.

Example two

On the basis of the foregoing embodiments, the present embodiment further provides a method for manufacturing a gate-all-around nano CMOS structure, where the method for manufacturing the gate-all-around nano CMOS structure includes:

step 2.1, selecting a semiconductor substrate 10;

step 2.2, forming a first material lamination layer and a second material lamination layer on the semiconductor substrate 10;

step 2.3, removing the sacrificial layer of the first material lamination and the sacrificial layer of the second material lamination to correspondingly form a first nano-body structure 20 with a first source region 60 and a first drain region 70 at two ends and a second nano-body structure 40 with a second source region 80 and a second drain region 90 at two ends;

and 2.4, forming a gate dielectric layer and a first gate electrode 30 and a second gate electrode 50 with the same work function around the first nano body structure 20 and the second nano body structure 40 to form the nMOS and the pMOS, wherein the first nano body structure and the second nano body structure have the same conductivity type.

Further, in a specific embodiment, step 2.2 may specifically include:

step 2.21, forming a first material layer and a second material layer which are alternately stacked on the semiconductor substrate 10;

and 2.22, etching the first material layer and the second material layer which are arranged in a laminated manner to form a first material laminated layer and a second material laminated layer.

Specifically, a first material layer and a second material layer which are stacked are sequentially formed on the semiconductor substrate 10, and then the first material layer and the second material layer which are stacked are etched, thereby forming a first material stack for preparing the first nano body structure 20 and a second material stack for preparing the second nano body structure 40.

Further, step 2.21 may specifically include:

when the first material layer and the second material layer are grown on the semiconductor substrate 10, the first material layer and the second material layer which are alternately stacked and have the same conductive type are formed in combination with an in-situ doping method.

That is to say, in the present embodiment, the first material layer and the second material layer are required to be doped with elements having the same conductivity type, for example, both the first material layer and the second material layer are p-type doped or both are n-type doped, so that when the first material layer or the second material layer is grown, the elements having the same conductivity type can be doped in the first material layer and the second material layer by using an in-situ doping method, so that the doping concentrations of the first material layer and the second material layer can be more uniform.

Further, in a specific embodiment, step 2.3 may specifically include:

step 2.31, preparing a first source region 60 and a first drain region 70 at two ends of the first material lamination, and preparing a second source region 80 and a second drain region 90 at two ends of the second material lamination;

step 2.32, removing the sacrificial layer of the first material stack forms a first nanostructure 20 and removing the sacrificial layer of the second material stack forms a second nanostructure 40.

Specifically, a first source region 60 and a first drain region 70 are first fabricated at both ends of the first material stack, and a second source region 80 and a second drain region 90 are fabricated at both ends of the second material stack, thereby facilitating the subsequent step of removing the sacrificial layer; one of the first material layer and the second material layer forming the first material stack is a sacrificial layer, and one of the first material layer and the second material layer forming the second material stack is a sacrificial layer, where the sacrificial layer is a material layer to be removed, for example, etching away the first material layer of the first material stack and the first material layer of the second material stack may form the first nanostructure 20 and the second nanostructure 40 in which the nanosheet or the nanowire is located at the same layer, and for example, etching away the first material layer of the first material stack and the second material layer of the second material stack may form the first nanostructure 20 and the second nanostructure 40 in which the nanosheet or the nanowire is located at adjacent layers.

Further, in a specific embodiment, step 2.4 may specifically include:

step 2.41, dielectric materials are grown around the first nano structure 20 and the second nano structure 40 to form a gate dielectric layer;

and 2.42, growing the same gate electrode material on the surface of the gate dielectric layer to form a first gate electrode 30 and a second gate electrode 50 with the same work function.

As can be seen from the above, the nMOS and the pMOS of the present embodiment are prepared on the semiconductor material with the same conductivity type and preferably the same doping concentration, so that it is not necessary to prepare the semiconductor materials with different conductivity types, and meanwhile, since the gate electrodes of the nMOS and the pMOS of the present embodiment are made of the conductive material with the same work function, and particularly, the same conductive material is adopted, it is not necessary to separately prepare the gate electrode of the nMOS and the gate electrode of the pMOS, the ring-gate nano CMOS prepared by the preparation method of the present embodiment reduces the preparation process steps, reduces the process and process difficulty, thereby can reduce the preparation cost, and the related parasitic influence can be reduced, thereby being beneficial to improving the performance and reliability of the ring-gate nano CMOS and the integrated circuit thereof.

It should be noted that the sequence of the steps of the preparation method of this embodiment is not the only sequence for implementing the gate-all-around nano CMOS structure provided in the first embodiment, but is only for convenience of describing the preparation method of this embodiment, for example, during the preparation process, the first source region and the first drain region may be prepared first, and then the second source region and the second drain region may be prepared first, and then the first source region and the first drain region may be prepared first.

It should be understood that other specific process means adopted for fabricating the gate-all-around nano CMOS in this embodiment can be implemented by the prior art, and are not described herein again.

The process technology related by the invention is compatible with the existing CMOS process technology, so that the whole process is not given in the embodiment, and the sequence of partial process can be changed.

EXAMPLE III

Referring to fig. 6a to 6n, fig. 6a to 6n are schematic diagrams illustrating a process for manufacturing a stacked-layer gate-all-around nanowire/CMOS wafer according to an embodiment of the present invention, and based on the above, the present embodiment further provides a method for manufacturing a stacked-layer gate-all-around nanowire/CMOS wafer, where the nanowire/wafer (the second material layer) is Si, and the sacrificial layer (the first material layer) is SiGe, and the method includes:

step 3.1, see fig. 6a, provides a semiconductor substrate 10.

Specifically, the semiconductor substrate 10 is bulk Si.

And 3.2, epitaxially growing a laminated material.

The stacked material is used for preparing the nanowire/sheet of the stacked gate-all-around nano CMOS, the conductive type of the stacked material can be n type or p type, and the nMOS and the pMOS of the embodiment share the semiconductor material with the same conductive type according to the design requirement.

Specifically, referring to fig. 6b, SiGe layers 101 and Si layers 102 are alternately grown on the surface layer of the semiconductor substrate 10 to form a stacked material.

Further, the SiGe layer 101 and the Si layer 102 have a property of being selectively etchable with respect to each other. In this embodiment, SiGe is first epitaxially grown on the semiconductor substrate 10, and then Si/SiGe is alternately grown. The thickness and number of layers of the laminate in this embodiment are according to design requirements, and this embodiment is not particularly limited thereto.

The conductive type of the laminated material can be realized by in-situ doping during the epitaxial growth of the laminated layer, and can also be finished by processes such as ion implantation, diffusion and the like in the subsequent process.

And 3.3, forming a fin structure.

Referring to fig. 6c, the SiGe layer 101 and the Si layer 102 are etched at the same time to etch a first material stack 100 and a second material stack 110, where the first material stack 100 and the second material stack 110 are fin structures, and when the SiGe layer 101 and the Si layer 102 are etched, the first material stack 100 is etched below the interface of the semiconductor substrate 10 to form a shallow trench, where the first material stack 110 is used to form a nanowire/plate of nMOS, the second material stack 110 is used to form a nanowire/plate of pMOS, and the geometric dimension of the nanowire/plate is prepared according to the design requirement.

Step 3.4, please refer to fig. 6d, wherein fig. 6d (1) is a cross-sectional view of a front view and fig. 6d (2) is a side view, a dielectric is deposited between the fin structures to form a dielectric layer 120, and for the bulk Si substrate, the surface of the dielectric layer 120 is aligned with the original upper surface of the bulk Si material, and the purpose and function of the deposition of the dielectric layer 120 is to etch the epitaxial SiGe material to form the nanowires/sheets of Si material as described below.

And 3.5, forming pseudo gate dielectrics and pseudo gate electrodes.

Specifically, referring to fig. 6e, where fig. 6e (1) is a cross-sectional view of a front view and fig. 6e (2) is a side view, a dummy gate dielectric 130 is first formed on the first material stack 100 and the second material stack 110, and then a dummy gate electrode 140 is formed on the dummy gate dielectric 130, the dummy gate dielectric 130 and the dummy gate electrode 140 are overlapped, and the dummy gate electrode 140 is formed for the subsequent formation of source and drain electrodes and for determining the channel length.

Step 3.6, please refer to fig. 6f, wherein fig. 6f (1) is a front view, fig. 6f (2) is a side view, an isolation layer 150 is formed on the side surface of the pseudo gate electrode 140, and the isolation layer 150 is used to prevent the gate electrode of the device prepared as described below from forming a short circuit with the source and drain electrodes thereof.

Step 3.7, please refer to fig. 6g, where fig. 6g is a side view, and the fins except for the dummy gate electrode side isolation layer 150 may be etched, or only the sacrificial layer except for the dummy gate electrode side isolation layer 150 may be etched.

Step 3.8, please refer to fig. 6h, fig. 6h is a partial cross-sectional view of the side view, and the sacrificial layer part with the bare drain is etched away by using an anisotropic etching method as shown in fig. 6 h.

Step 3.9, please refer to fig. 6i, fig. 6i is a partial cross-sectional view of a side view, and the inner isolation layer 160 is formed at the etched-away sacrificial layer.

Step 3.10, please refer to fig. 6j, fig. 6j (2) is a cross-sectional view of a front view, fig. 6j (1) and fig. 6j (3) are side views, and a first source region 60 and a first drain region 70 of nMOS are formed for nMOS epitaxial n-type semiconductor material, and a second source region 80 and a second drain region 90 of pMOS are formed for pMOS epitaxial p-type semiconductor material, respectively, at two sides of the divided pseudo-gate isolation layers of nMOS and pMOS.

It should be appreciated that since all fins of the present embodiment are identical, the fins of both nMOS and pMOS can be divided unconstrained.

Step 3.11, referring to fig. 6k, fig. 6k (1) and fig. 6k (2) are side views, where dummy gate electrode 140 and underlying gate dielectric 130 are etched away, isolation layer 150 on the side surface of dummy gate electrode 140 is remained, and fins on the lower surface of gate dielectric 130 are exposed.

Step 3.12, see fig. 6l, fig. 6l (1), fig. 6l (2) are side views, and the SiGe layer is etched away by using the anisotropic etching characteristics of the SiGe layer and the Si layer, leaving the Si layer as the nano-wires/sheets of nMOS and pMOS, the Si layer being left as the first nano-body structure 20 of nMOS and the second nano-body structure 40 of pMOS.

And 3.13, depositing a gate dielectric layer and preparing a gate electrode.

Specifically, referring to fig. 6m, fig. 6m (1), fig. 6m (2) are cross-sectional side views, first co-depositing a gate dielectric layer 170 around the released bare-drain Si nanowires/sheets of nMOS and pMOS; thereafter, a gate metal of the same work function is co-deposited over the gate dielectric layer 170 around the Si nanowires/slabs of nMOS and pMOS, forming the first gate electrode 30 and the second gate electrode 50.

It should be noted that the specific value of the work function of the gate electrode in this embodiment needs to be determined by optimizing the thickness and doping concentration of the nanowire/sheet based on the electrical property requirement, and it needs to ensure that the nanowire/sheet is fully depleted under zero bias.

And 3.14, metallization.

Specifically, referring to fig. 6n, wherein fig. 6n (1) and 6n (3) are sectional views of side views, fig. 6n (2) is a partial sectional view of a front view, and finally, a metallization connection is implemented through a metal 180, and the purpose of the metallization is to connect the first gate electrode 30 of the stacked gate-all-around nanowire/sheet nMOS and the second gate electrode 50 of the pMOS together, and connect the first drain region 70 of the nMOS and the second drain region 90 of the pMOS together, so as to form a stacked layer gate-all-around nanowire/sheet CMOS structure.

It should be noted that the nanowire/sheet of this embodiment may be of an n-type or a p-type, and the conductive type of the stacked nanowire/sheet may be formed by in-situ doping during the epitaxial growth of the stacked material, or may be formed in a subsequent process, such as ion implantation, diffusion, and the like.

In addition, when the semiconductor substrate 10 of the present embodiment is an SOI (Silicon-On-Insulator, Silicon On an insulating substrate), the difference between the semiconductor substrate 10 and the bulk Si is only in steps 3.1 to 3.4, and the remaining steps are the same as those of the semiconductor substrate 10, so that the steps 3.1 to 3.4 are only described for the stacked same-layer ring-gate nanowire/sheet CMOS in which the semiconductor substrate 10 is an SOI, and referring to fig. 7a to 7d, when the semiconductor substrate 10 of the present embodiment is an SOI, the preparation method includes:

step 3.1, see fig. 7a, provides a semiconductor substrate 10.

Specifically, the semiconductor substrate 10 is SOI.

And 3.2, epitaxially growing a laminated material.

Specifically, referring to fig. 7b, a stacked material of SiGe layers 101 and Si layers 102 is alternately grown on the surface layer of the semiconductor substrate 10.

And 3.3, forming a fin structure.

Referring to fig. 7c, the SiGe layer 101 and the Si layer 102 are etched simultaneously to etch the first material stack 100 and the second material stack 110, where the first material stack 100 and the second material stack 110 are fin structures, and when the stack on the SOI is etched to form fins, the SiO of the SOI needs to be etched₂An upper surface, wherein a first material stack 100 is used to form the nanowires/platelets of nMOS and a second material stack 110 is used to form the nanowires/platelets of pMOS, the geometric dimensions of the nanowires/platelets being prepared as required by the design.

Step 3.4, please refer to fig. 7d, wherein fig. 7d (1) is a front view, fig. 7d (2) is a side view, a dielectric layer 120 is deposited between the fin structures, and for the SOI substrate, the surface of the dielectric layer 120 is aligned with the top Si surface of the SOI material, and the purpose and function of depositing the dielectric layer 120 is to form the nanowire/chip of Si material.

For the semiconductor substrate 10 being an SOI, the steps after forming the dielectric layer 120 on the SOI are the same as the preparation steps for the semiconductor substrate 10 being bulk Si in this embodiment, and are not described again here.

Example four

Referring to fig. 8a to 8d, fig. 8a to 8d are schematic diagrams illustrating a process of manufacturing another stacked-layer gate-all-around nanowire/CMOS wafer according to an embodiment of the present invention, and based on the above, the present embodiment further provides a method for manufacturing a stacked-layer gate-all-around nanowire/CMOS wafer, where the nanowire/wafer (the first material layer) is SiGe, and the sacrificial layer (the second material layer) is Si, and the method includes:

step 4.1, see fig. 8a, provides a semiconductor substrate 10.

Specifically, the semiconductor substrate 10 is bulk Si.

And 4.2, epitaxially growing a laminated material.

Specifically, referring to fig. 8b, a stacked material of SiGe layers 101 and Si layers 102 is alternately grown on the surface layer of the semiconductor substrate 10.

Further, the SiGe layer 101 and the Si layer 102 have a property of being selectively etchable with respect to each other.

And 4.3, forming a fin structure.

Referring to fig. 8c, the SiGe layer 101 and the Si layer 102 are etched at the same time to etch a first material stack 100 and a second material stack 110, where the first material stack 100 and the second material stack 110 are fin structures, and when the SiGe layer 101 and the Si layer 102 are etched, the upper interface of the bulk Si may be etched, or the lower interface of the bulk Si may be etched to form a shallow trench, where the first material stack 100 is used to form a nanowire/chip of nMOS, and the second material stack 110 is used to form a nanowire/chip of pMOS.

Step 4.4, please refer to fig. 8d, wherein fig. 8d (1) is a cross-sectional view in front view, and fig. 8d (2) is a side view, and a dielectric is deposited between the fin structures to form a dielectric layer 120, and for the bulk Si substrate, the surface of the dielectric layer 120 is aligned with the upper interface of the first layer SiGe, and the purpose and function of the deposition of the dielectric layer 120 is to form nanowires/sheets of SiGe material.

It should be noted that, for the same-layer nanowire/slice prepared from SiGe, after step 4.4, the methods of forming the dummy gate dielectric, the dummy gate electrode and the isolation layer, forming the inner isolation layer, forming the source/drain electrode, removing the dummy gate electrode, releasing the nanowire/slice, depositing the gate dielectric, and preparing the gate electrode are similar to those provided in the third embodiment, and the differences are only that the sacrificial layer in the third embodiment is a SiGe layer, the nanowire/slice is a Si layer, the sacrificial layer in the present embodiment is a Si layer, and the nanowire/slice is a SiGe layer, and therefore, details are not described here.

In addition, when the semiconductor substrate 10 of the present embodiment is an SOI, the difference between the semiconductor substrate 10 and the bulk Si is only in step 4.1 to step 4.4, and the remaining steps are the same as those when the semiconductor substrate 10 is the bulk Si, so that the present embodiment only describes step 4.1 to step 4.4 for the stacked-layer ring-gate nanowire/chip CMOS in which the semiconductor substrate 10 is an SOI, please refer to fig. 9a to 9c, and when the semiconductor substrate 10 of the present embodiment is an SOI, the preparation method includes:

step 4.1, see fig. 9a, a semiconductor substrate 10 is provided.

Specifically, the semiconductor substrate 10 is SOI.

And 4.2, epitaxially growing a laminated material.

Specifically, referring to fig. 9b, a stacked material of SiGe layers 101 and Si layers 102 is alternately grown on the surface layer of the semiconductor substrate 10.

And 4.3, forming a fin structure.

Referring to fig. 9c, fig. 9c (1) is a front view, fig. 9c (2) is a side view, and the SiGe layer 101 and the Si layer 102 are etched at the same time to etch the first material stack 100 and the second material stack 110, where the first material stack 100 and the second material stack 110 are fin structures, and when the stack on the SOI is etched to form fins, the SiO of the SOI needs to be etched₂An upper surface, wherein a first material stack 100 is used to form the nanowires/platelets of nMOS and a second material stack 110 is used to form the nanowires/platelets of pMOS, the geometric dimensions of the nanowires/platelets being prepared as required by the design.

For the semiconductor substrate 10 being SOI, the subsequent steps are the same as the preparation steps of the present embodiment in which the semiconductor substrate 10 is bulk Si, and are not described again here.

EXAMPLE five

Referring to fig. 10a to 10j, fig. 10a to 10j are schematic diagrams illustrating a process for manufacturing a stacked adjacent layer ring gate nanowire/CMOS, and based on the above, this embodiment further provides a method for manufacturing a stacked adjacent layer ring gate nanowire/CMOS, where the nanowire/sheet (second material layer) of nMOS is Si, and the nanowire/sheet (first material layer) of pMOS is SiGe, and the method includes:

step 5.1, see fig. 10a, provides a semiconductor substrate 10.

Specifically, the semiconductor substrate 10 is SOI.

And 5.2, epitaxially growing a laminated material.

Specifically, referring to fig. 10b, SiGe layers 101 and Si layers 102 are alternately grown on the surface layer of the semiconductor substrate 10.

Further, the SiGe layer 101 and the Si layer 102 have a property of being selectively etchable with respect to each other. In this embodiment, the first layer of epitaxial material is SiGe, and then Si/SiGe is grown alternately. The thickness and number of layers of the laminate in this embodiment are according to design requirements, and this embodiment is not particularly limited thereto.

And 5.3, forming a fin structure.

Referring to fig. 10c, in which fig. 10c (1) is a front view and fig. 10c (2) is a side view, the SiGe layer 101 and the Si layer 102 are simultaneously etched to etch the first material stack 100 and the second material stack 110, the first material stack 100 and the second material stack 110 are fin structures, and when the SiGe layer 101 and the Si layer 102 are etched, SiO of the SOI can be etched₂A surface, wherein a first material stack 100 is used to form the nanowires/flakes of nMOS and a second material stack 110 is used to form the nanowires/flakes of pMOS, the geometric dimensions of the nanowires/flakes being prepared as required by the design.

Step 5.4, please refer to fig. 10d, wherein fig. 10d (1) and fig. 10d (3) are side views and fig. 10d (2) is a front view, a dielectric layer 120 is formed by depositing a dielectric between the fin structures of the nMOS region, the surface of the dielectric deposited between the fins of the nMOS region is aligned with the lower surface of the first layer SiGe, and no dielectric is deposited between the fins of the pMOS region.

And 5.5, forming pseudo gate dielectrics and pseudo gate electrodes.

Specifically, referring to fig. 10e, wherein fig. 10e (1) and fig. 10e (2) are side views, a dummy gate dielectric is first formed on the first material stack 100 and the second material stack 110, and then a dummy gate electrode 140 is formed on the dummy gate dielectric, the dummy gate dielectric is overlapped with the dummy gate electrode 140, and the dummy gate electrode 140 is formed for the subsequent formation of source and drain electrodes and the determination of the channel length.

Step 5.6, please continue to refer to fig. 10e, an isolation layer 150 is formed on the side surface of the dummy gate electrode 140, and the isolation layer 150 is used to prevent the gate electrode of the device prepared as described below from forming short circuits with the source and drain electrodes thereof.

Step 5.7, please refer to fig. 10f, where fig. 10f (1) and fig. 10f (3) are side views, fig. 10f (2) is a partial cross-sectional view corresponding to fig. 10f (1), and fig. 10f (4) is a cross-sectional view corresponding to fig. 10f (3), the dummy gate electrode 140 and the fin outside the isolation layer 150 on the side thereof are etched away, the SiGe portion blocked by the isolation layer is etched away in the nMOS region by an anisotropic etching method, the Si portion blocked by the isolation layer is etched away in the pMOS region by an anisotropic etching method, and the inner isolation layer 160 is formed at the etched-away sacrificial layer.

Step 5.8, please refer to fig. 10g, wherein fig. 10f (1) and fig. 10f (3) are side views, and fig. 2 is a front view, wherein a first source region 60 and a first drain region 70 of nMOS are formed for nMOS epitaxial n-type semiconductor material and a second source region 80 and a second drain region 90 of pMOS are formed for pMOS epitaxial p-type semiconductor material, respectively, at two sides of the divided spacers of nMOS and pMOS.

Step 5.9, please refer to fig. 10h, where fig. 10h (1) is a partial cross-sectional view of a side view, fig. 10h (2) is a side view, the dummy gate electrode 140 and the underlying gate-last dielectric are etched away, the isolation layer 150 on the side of the dummy gate electrode 140 is remained, the fin exposed on the lower surface of the gate-last dielectric 130, the SiGe layer in the nMOS region is etched away by utilizing the anisotropic etching characteristics of Si and SiGe, the Si layer is left to serve as the nanowire/sheet of nMOS, the Si layer in the pMOS region is etched away, the SiGe layer is left to serve as the nanowire/sheet of pMOS, the Si layer is left to serve as the first nanostructure 20 of nMOS, and the SiGe layer is left to serve as the second nanostructure 40 of pMOS.

And 5.10, depositing a gate dielectric layer and preparing a gate electrode.

Specifically, referring to fig. 10i, where fig. 10i (1) is a partial cross-sectional view of a side view and fig. 10i (2) is a cross-sectional view of a side view, a gate dielectric layer 170 is first co-deposited around the released bare-drain Si nanowires/slabs of nMOS and pMOS SiGe nanowires/slabs; thereafter, a gate metal of the same work function is co-deposited over the gate dielectric layer 170 around the Si nanowires/slabs of nMOS and the SiGe nanowires/slabs of pMOS to form the first gate electrode 30 and the second gate electrode 50.

And 5.10, metallization.

Specifically, referring to fig. 10j, where fig. 10j (1) is a partial cross-sectional view of a side view, fig. 10j (2) is a partial cross-sectional view of a front view, and fig. 10j (3) is a cross-sectional view of a side view, finally, a metallization connection is implemented through a metal 180 for the purpose of connecting the first gate electrode 30 of the stacked gate-all-around nanowire/tile nMOS with the second gate electrode 50 of the pMOS, and connecting the first drain region 70 of the nMOS with the second drain region 90 of the pMOS, forming a stacked-level gate-all-around nanowire/tile CMOS structure.

It should be noted that the nanowire/sheet of this embodiment may be of an n-type or a p-type, and the conductive type of the stacked nanowire/sheet may be formed by in-situ doping during the epitaxial growth of the stacked material, or may be formed by ion implantation or diffusion in the subsequent process.

In addition, when the semiconductor substrate 10 of the present embodiment is bulk Si, the difference between the semiconductor substrate 10 and the SOI is only in step 5.1 to step 5.4, and the remaining steps are the same as those when the semiconductor substrate 10 is SOI, so that in this embodiment, only step 5.1 to step 5.4 are described for the stacked adjacent layer ring gate nanowire/sheet CMOS in which the semiconductor substrate 10 is bulk Si, referring to fig. 11a to 11d, when the semiconductor substrate 10 of the present embodiment is bulk Si, the preparation method includes:

step 5.1, see fig. 11a, provides a semiconductor substrate 10.

Specifically, the semiconductor substrate 10 is bulk Si.

And 5.2, epitaxially growing a laminated material.

Specifically, referring to fig. 11b, SiGe layers 101 and Si layers 102 are alternately grown on the surface layer of the semiconductor substrate 10.

And 5.3, forming a fin structure.

Referring to fig. 11c, the SiGe layer 101 and the Si layer 102 are etched at the same time to etch a first material stack 100 and a second material stack 110, where the first material stack 100 and the second material stack 110 are fin structures, and when the SiGe layer 101 and the Si layer 102 are etched, the surface of the bulk Si may be etched, or the surface of the bulk Si may be etched below the interface of the bulk Si, where the first material stack 100 is used to form the nano wire/sheet of nMOS, the second material stack 110 is used to form the nano wire/sheet of pMOS, and the geometric dimensions of the nano wire/sheet are prepared according to the design requirements.

Step 5.4, please refer to fig. 11d, wherein fig. 11d (1) and 11d (3) are cross-sectional side views, and fig. 11d (2) is a cross-sectional front view, and a dielectric layer 120 is formed by depositing a dielectric between the fin structures of the nMOS region and the pMOS region, wherein a surface of the dielectric deposited between the fins of the nMOS region is aligned with a lower surface of the first layer SiGe, and a surface of the dielectric deposited between the fins of the pMOS region is aligned with an upper surface of the first layer SiGe.

For the semiconductor substrate 10 being bulk Si, the steps after forming the dielectric layer 120 on the bulk Si are the same as the preparation steps for the semiconductor substrate 10 being SOI of this embodiment, and are not described again here.

In the description of the present invention, the terms "first" and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implying any number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.

In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic data point described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples described in this specification can be combined and combined by those skilled in the art.

The foregoing is a more detailed description of the present invention that is presented in conjunction with specific embodiments, and the practice of the invention is not to be considered limited to those descriptions. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.

Claims

1. A ring-gated nano-CMOS structure comprising an nMOS and a pMOS, wherein the nMOS comprises a first nano-body structure provided on a semiconductor substrate and a first gate electrode surrounding the first nano-body structure, and the pMOS comprises a second nano-body structure provided on the semiconductor substrate and a second gate electrode surrounding the second nano-body structure, wherein,

2. The gate-all-around nano-CMOS structure of claim 1, wherein the material of the first and second nano-body structures is an n-type semiconductor material with the same doping concentration, the first source and drain regions of nMOS are n-type doped, and the second source and drain regions of pMOS are p-type doped.

3. The gate-all-around nano-CMOS structure of claim 2, wherein the work functions of the first gate electrode and the second gate electrode are in the range of 4.6-5.1 eV.

4. The gate-all-around nano-CMOS structure of claim 1, wherein the material of the first and second nano-body structures is a p-type semiconductor material with the same doping concentration, the first source and drain regions of nMOS are n-type doped, and the second source and drain regions of pMOS are p-type doped.

5. The gate-all-around nano-CMOS structure of claim 4, wherein the work functions of said first gate electrode and said second gate electrode are in the range of 4.1-4.5 eV.

6. The gate-all-around nano-CMOS structure according to any one of claims 1 to 5, wherein the first nano-structure comprises at least one first nano-body, when the number of the first nano-bodies is greater than or equal to two, all the first nano-bodies are arranged in a stacked manner in a vertical direction or arranged in a same layer manner in a horizontal direction, the second nano-structure comprises at least one second nano-body, and when the number of the second nano-bodies is greater than or equal to two, all the second nano-bodies are arranged in a stacked manner in a vertical direction or arranged in a same layer manner in a horizontal direction.

7. The gate-all-around nano-CMOS structure of claim 6, wherein the first nano-body and the second nano-body are in the same layer or adjacent layers.

8. The gate-all-around nano-CMOS structure of claim 7, wherein the first and second nano-bodies are nano-sheets or nano-wires.

9. A method for fabricating a gate-all-around nano CMOS structure according to any one of claims 1 to 8, the method comprising:

selecting a semiconductor substrate;

10. The method of claim 9, wherein forming a first material stack and a second material stack of the same conductivity type on the semiconductor substrate comprises: