CN112710948A

CN112710948A - Clock frequency detection circuit, clock control circuit and clock frequency detection method

Info

Publication number: CN112710948A
Application number: CN201911025411.5A
Authority: CN
Inventors: 彭敏强
Original assignee: Sanechips Technology Co Ltd
Current assignee: Sanechips Technology Co Ltd
Priority date: 2019-10-25
Filing date: 2019-10-25
Publication date: 2021-04-27

Abstract

The invention provides a clock frequency detection circuit, a clock control circuit and a clock frequency detection method, wherein the clock control circuit comprises: the measurement module comprises a first clock counter, wherein the first clock counter is configured to acquire a count value of a first clock signal in a first period; the comparison module is configured to compare the calculated value with an expected value of the first clock signal in a first period to obtain a comparison result; and the control chain module is configured to acquire an expected value according to the serial chain test vector, send the expected value to the comparison module, acquire a comparison result according to the serial chain test vector and perform frequency detection on the clock to be tested according to the comparison result. The invention solves the problems of overhigh test cost and higher complexity of test design in the process of detecting the clock network frequency in the chip in the related technology, thereby achieving the effect of reducing the equipment and time cost in the process of detecting the clock network frequency in the chip.

Description

Clock frequency detection circuit, clock control circuit and clock frequency detection method

Technical Field

The invention relates to the field of microelectronics, in particular to a clock frequency detection circuit, a clock control circuit and a clock frequency detection method.

Background

At present, the digital chip Design scale is larger and more complex, and therefore, the requirements and challenges For Design For Test (DFT) in the chip Design process are higher and higher: currently, DFT needs to improve the test quality, reduce the test time as much as possible, reduce the test pin resource requirement, and reduce the complexity of the test circuit design and integration.

A plurality of clock generation or processing modules are arranged on a chip internal clock network, for example, a phase-locked loop, a frequency divider, a clock switching circuit, etc., and a conventional DFT Test method such as a Serial Chain (SCAN) method and a Memory Build In Self Test (MBIST) method cannot directly cover the Test of the clock generation or processing modules on the clock network. In the related art, the clock generation and processing module is usually tested by a direct test method, i.e., the output of the partial clock or the output after frequency division is connected to the chip pin for measurement. The testing method is subject to the performance of an Automatic Test Equipment (ATE) machine which needs to be adopted during testing, and specifically, the measuring precision is subject to the maximum sampling number of the ATE machine in unit time, and is inversely proportional to the frequency of a measured clock circuit, and the higher the frequency of the clock circuit is, the higher the requirement on the measuring precision is, and the higher the corresponding requirement on the performance of the ATE machine is; therefore, in order to ensure the measurement accuracy of the measurement of the high-frequency clock circuit, it is necessary to ensure that the ATE machine has good performance, thereby increasing the measurement cost.

Meanwhile, when a Chip is subjected to a wafer test (CP), a test pin is very sensitive to frequency and generally cannot be directly used as a test item of the CP, so that the test application is limited and the test cost is indirectly increased; the test method also needs additional test pin resources during CP test, the available pin resources for testing in many projects are limited, conflict of pin resource requirements is easy to cause, and the additional pin arrangement also causes higher requirements on the pin driving capability of the output clock, so that the test design complexity is increased.

In addition, there is an indirect clock control circuit design based on the digital circuit principle in the related art, wherein a common test method is to test an internal high-speed clock by using an interface clock, that is, to enable the interface clock and the internal high-speed clock to start counting at the same time, and to calculate the frequency of the internal high-speed clock by using a count value in a certain counting interval and a known interface clock frequency, so as to determine whether there is a deviation between the internal high-speed clock frequency and a design value. According to the test method, a test vector needs to be independently set in the test process to cover a clock circuit to be tested, and an additional test control pin is needed in the test process; therefore, the test time cost is obviously increased under the condition that the clock network in the chip is complex and the number of the points to be tested is large, and the complexity of the test design is greatly improved.

In view of the above problems in the related art that the cost of testing the frequency of the clock network in the chip during the detection process is too high and the complexity of the test design is large, no effective solution has been proposed in the related art.

Disclosure of Invention

The embodiment of the invention provides a clock frequency detection circuit, a clock control circuit and a clock frequency detection method, which at least solve the problems of overhigh test cost and higher test design complexity in the process of detecting the frequency of an on-chip clock network in the related technology.

According to an embodiment of the present invention, there is provided a clock frequency detection circuit including:

the measurement module comprises a first clock counter, wherein the first clock counter is configured to count a first clock signal in a first period so as to obtain a count value of the first clock signal in the first period; the first clock signal is a clock signal input by a clock to be tested;

a comparison module configured to compare the calculated value with an expected value of the first clock signal in the first period to obtain a comparison result;

and the control chain module is configured to acquire the expected value according to a serial chain test vector, send the expected value to the comparison module, acquire the comparison result according to the serial chain test vector and perform frequency detection on the clock to be detected according to the comparison result.

According to another embodiment of the present invention, there is also provided a clock control circuit, including the clock control circuit described in the above embodiment, in this embodiment, the clock control circuit further includes:

a first input module configured to input the first clock signal;

a control module configured to control the first clock signal, obtain the chain test vector, and send the chain test vector to the control chain module in the clock frequency detection circuit.

According to another embodiment of the present invention, there is also provided a chip including the clock control circuit described in the above embodiment.

According to another embodiment of the present invention, there is also provided a clock frequency detection method including:

acquiring an expected value of a first clock signal counted in a first period, wherein the first clock signal is a clock signal input by a clock to be tested;

acquiring a count value of the first clock signal counted in the first period;

and obtaining a comparison result of comparing the count value with the expected value according to the serial chain test vector so as to carry out frequency detection on the clock to be detected.

According to another embodiment of the present invention, there is also provided a clock frequency detection apparatus including:

the device comprises a first acquisition module, a second acquisition module and a third acquisition module, wherein the first acquisition module is used for acquiring an expected value of a first clock signal counted in a first period, and the first clock signal is a clock signal input by a clock to be detected;

the second acquisition module is used for acquiring a count value of the first clock signal counted in the first period;

and the comparison module is used for obtaining a comparison result of comparing the counting value with the expected value according to the serial chain test vector so as to carry out frequency detection on the clock to be detected.

According to another embodiment of the present invention, a computer-readable storage medium is also provided, in which a computer program is stored, wherein the computer program is configured to perform the steps of any of the above-described method embodiments when executed.

According to another embodiment of the present invention, there is also provided an electronic device, including a memory in which a computer program is stored and a processor configured to execute the computer program to perform the steps in any of the above method embodiments.

According to the invention, the control chain module is configured to obtain the expected value according to the serial chain test vector and send the expected value to the comparison module, and the control chain module obtains the expected value and the first clock counter in the measurement module according to the serial chain test vector and counts the first clock signal in a first period by the comparison module so as to obtain the comparison result between the count values of the first clock signal in the first period and carry out frequency detection on the clock to be detected according to the comparison result; therefore, the invention can solve the problems of overhigh test cost and higher complexity of test design in the process of detecting the clock network frequency in the chip in the related technology, thereby achieving the effects of reducing the equipment and time cost in the process of detecting the clock network frequency in the chip and reducing the complexity of the test design.

Drawings

The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the invention without limiting the invention. In the drawings:

FIG. 1 is a functional diagram of a clock frequency detection circuit according to an embodiment of the present invention;

FIG. 2 is a functional diagram of a clock frequency detection circuit according to an embodiment of the present invention;

FIG. 3 is a functional diagram of a clock frequency detection circuit according to an embodiment of the present invention (III);

FIG. 4 is a functional diagram of a clock frequency detection circuit according to an embodiment of the present Invention (IV);

FIG. 5 is a circuit diagram of a clock frequency detection circuit according to an embodiment of the present invention;

FIG. 6 is a functional diagram of a clock control circuit according to an embodiment of the present invention;

FIG. 7 is a functional diagram of a clock control circuit according to an embodiment of the present invention;

FIG. 8 is a circuit schematic of a clock control circuit provided in accordance with an embodiment of the present invention;

FIG. 9 is a flow chart of clock frequency detection performed by the clock control circuit according to an embodiment of the present invention;

FIG. 10 is a flow chart of a clock frequency detection method provided in accordance with an embodiment of the present invention;

fig. 11 is a block diagram of a clock frequency detection apparatus according to an embodiment of the present invention.

Detailed Description

The invention will be described in detail hereinafter with reference to the accompanying drawings in conjunction with embodiments. It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict.

It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order.

Example 1

Fig. 1 is a functional schematic diagram (one) of a clock frequency detection circuit according to an embodiment of the present invention, and as shown in fig. 1, the clock frequency detection circuit in the embodiment includes:

the measurement module 102 includes a first clock counter 1022 configured to count the first clock signal in a first period to obtain a count value of the first clock signal in the first period; the first clock signal is a clock signal input by a clock to be tested;

a comparison module 104 configured to compare the calculated value with an expected value of the first clock signal in the first period to obtain a comparison result;

the control chain module 106 is configured to obtain an expected value according to the serial chain test vector, send the expected value to the comparison module 104, obtain a comparison result according to the serial chain test vector, and perform frequency detection on the clock to be tested according to the comparison result.

It should be further noted that, in the measurement module, the first clock counter is configured to count the first clock signal in a first period, and may instruct the first clock counter to count the first clock signal in a preset first period, and may also instruct the first clock counter to use another device, for example, another counter, as a reference for counting, for example, the first clock counter counts according to the start of counting of the another counter, and stops counting according to the end of counting of the another counter.

In the control chain module 106, the serial chain test vector is a test vector issued by the control chain module, and since the serial chain test vector is an existing vector for performing control processing on the clock in the control chain module, it is not necessary to set a separate test adjacency in performing clock frequency detection in this embodiment.

According to the clock frequency detection circuit in the embodiment, the control chain module is configured to obtain the expected value according to a serial chain test vector, send the expected value to the comparison module, obtain the expected value according to the serial chain test vector, count the first clock signal in a first period by the comparison module for the expected value and a first clock counter in the measurement module, obtain a comparison result between count values of the first clock signal in the first period, and perform frequency detection on the clock to be detected according to the comparison result; therefore, the clock frequency detection circuit in the embodiment can solve the problems of overhigh test cost and higher complexity of test design in the process of detecting the clock network frequency in the chip in the related technology, so as to achieve the effects of reducing the equipment and time cost in the process of detecting the clock network frequency in the chip and reducing the complexity of the test design.

In an optional embodiment, the measurement module 102 further includes a second clock counter 1024, where the second clock counter 1024 is configured to count a second clock signal in a second period;

the second clock signal is a clock signal input by peripheral Automatic Test Equipment (ATE), and the second period is a preset inherent period of the second clock signal; the first period is synchronous with the second period.

It should be further noted that the first period is synchronized with the second period, and indicates that the first period counted by the first clock counter is referenced to the second period, and is synchronized with the second period, i.e., the actual period counted by the first clock counter is the second period. The first clock counter counts in a second period, and the specific period information of the second period can be sent to the control part of the first clock counter for control, or when the second clock counter counts in a natural period, that is, the second period, the first clock counter counts when the second clock counter starts counting, and stops counting when the second clock counter finishes counting, that is, the first clock counter counts with the second clock counter as a reference; the present invention does not limit the specific counting manner of the first clock counter. Fig. 2 is a functional schematic diagram (ii) of a clock frequency detection circuit according to an embodiment of the present invention, and the structure of the measurement module in the above-mentioned alternative embodiment is shown in fig. 2.

In an alternative embodiment, the expected value is obtained from the following:

the second period, the frequency information of the first clock signal, and the frequency information of the second clock signal.

It should be further noted that the frequency information of the first clock signal is a clock frequency of the first clock signal, and the frequency information of the second clock signal is a clock frequency of the second clock signal. Setting the second period to be Cnt _ R, the frequency information of the first clock signal to be Frq _ T, the frequency information of the second clock signal to be Cnt _ R, and the expected value of the first clock signal in the first period to be Int _ M, the expected value can be obtained by the following formula:

Int_M＝[Cnt_R*Frq_T/Frq_R]；

the above [ ] represents rounding up the calculation result for Cnt _ R Frq _ T/Frq _ R.

It should be further noted that the above formula for obtaining the expected value Int _ M is only an optional way, and during the process of actually determining the expected value, the expected value may also be determined in other ways according to the actual detection environment or requirements, which is not limited by the present invention.

In an alternative embodiment, the comparing module 104 includes:

an expected value storage unit 1042 configured to store an expected value;

the comparing unit 1044 is configured to obtain the count value and the expected value, and compare the count value with the expected value to obtain a comparison result.

It should be further noted that the expected value storage unit stores the expected value, i.e., the expected value can be fed into the expected value storage unit through the chain test vector. Fig. 3 is a functional schematic diagram (iii) of a clock frequency detection circuit according to an embodiment of the present invention, and the comparison module in the above-mentioned alternative embodiment is configured as shown in fig. 3.

In an optional embodiment, the comparing unit 1044 is further configured to:

removing the error in the count value according to the preset error bit;

and comparing the count value with the expected value to obtain a comparison result.

It should be further noted that, during the counting process of the first clock counter, since the first clock counter may be controlled by using an asynchronous clock based on the counting of other counters on other clock signals, there is a possibility that an error occurs in the first clock counter during the starting and ending of the counting. The setting of the comparison unit can effectively eliminate the possible error in the counting value, thereby improving the precision of the clock frequency detection. It should be noted that, in the process of comparing the count value after the error is eliminated with the expected value, the count value may be directly compared with the expected value of the corresponding code bit by using corresponding processing, and also the code bit that may have an error may be directly removed in the process of determining the expected value, which is not limited in the present invention.

In an alternative embodiment, the control chain module 106 includes an expectation value register 1062, a comparison result register 1064; the control chain module 1062 is also configured to,

indicating an expected value register to obtain an expected value under a serial data shifting mode according to the serial test vector, and sending the expected value to a comparison module; and/or the presence of a gas in the gas,

and indicating the comparison result register to obtain a comparison result in a serial data acquisition mode according to the serial test vector, and carrying out frequency detection on the clock to be tested according to the comparison result.

It should be further noted that fig. 4 is a functional schematic diagram (iv) of the clock frequency detection circuit provided in the embodiment of the present invention, and the structure of the control chain module in the above alternative embodiment is shown in fig. 4.

In an optional embodiment, the control chain module 106 is further configured to send the comparison result to an external automatic test equipment ATE to perform frequency detection on the clock to be tested.

To further explain the clock frequency detection circuit in the present embodiment, the circuit configuration and the operation of the clock frequency detection circuit will be explained below by way of specific embodiments.

Detailed description of the preferred embodiment

Fig. 5 is a schematic circuit diagram of a clock frequency detection circuit according to an embodiment of the present invention, and the input signal, the output signal, and the specific structure of the clock frequency detection circuit in the embodiment are described below with reference to fig. 5.

The input signal of the clock frequency detection circuit in this embodiment includes:

1) and (3) SI: input control signals of the scan chain;

2) PLL _ CLK: a high-speed clock signal, where the PLL _ CLK is output from a phase-locked loop inside a chip, where the PLL _ CLK is a first clock signal in the above embodiment, and in this embodiment, the PLL _ CLK is a clock signal to be frequency-detected;

3) ATE _ CLK: a low-speed clock signal, where the ATE _ CLK is directly input by an external ATE tester, where the ATE _ CLK is the second clock signal in the above embodiment, and the inherent cycle of the ATE _ CLK is the second cycle in the above embodiment;

4) OCC _ RST: an OCC reset signal;

the output signal of the clock frequency detection circuit in this embodiment is SO.

The clock frequency detection circuit in this embodiment specifically includes: a clock counter to be tested 001, a reference clock counter 002 and a TEST _ ON module 003. A clock counter 001 to be tested, which corresponds to the first clock counter in the above embodiments, where the clock counter 001 to be tested is used to access the PLL _ CLK; the reference clock counter 002, i.e. the second clock counter in the above embodiment, the reference clock counter 002 is used to access the ATE _ CLK. The TEST _ ON module 003 is configured to access the OCC _ RST and is controlled by the OCC _ RST; specifically, after OCC _ RST is reset and released, the TEST _ ON module 003 sends an enable signal counter _ en to the clock under TEST counter 001 and the reference clock counter 002 to instruct the clock under TEST counter 001 and the reference clock counter 002 to start counting operations with respect to the PLL _ CLK and the ATE _ CLK, respectively.

Further, the reference clock counter 002 stores the inherent period of ATE _ CLK, that is, the second period, and when the reference clock counter 002 counts ATE _ CLK to the inherent period, the reference clock counter 002 stops counting, and at this time, the TEST _ ON module 003 turns off the corresponding enable signal, so that the clock counter 001 to be tested also stops counting PLL _ CLK.

For different PLL _ CLK, the clock counter under test 001 theoretically has different counting results in the corresponding counting period, i.e., the inherent period of ATE _ CLK, and the result is set as the expected value of the clock counter under test 001 counting PLL _ CLK in the inherent period of ATE _ CLK. The expected value may be determined by: setting the inherent period of ATE _ CLK to Cnt _ R, the clock frequency of PLL _ CLK to Frq _ T, the clock frequency of ATE _ CLK to Cnt _ R, and the expected value to Int _ M, the expected value can be obtained by the following formula:

Int_M＝[Cnt_R*Frq_T/Frq_R]；

The clock frequency detection circuit in this embodiment further includes an expected value storage logic 004 and a counter comparison circuit 005, and the expected value obtained through the theoretical calculation can be stored in the expected value storage logic 004. The count value of PLL _ CLK acquired by the clock counter 001 to be tested and the expected value of the expected value storage logic 004 are simultaneously fed to the counter comparison circuit 005 for comparison processing. Here, the counter comparison circuit 005 may indicate that the comparison result between the count value of the PLL _ CLK and the expected value is "true" by "1", and indicate that the comparison result between the count value of the PLL _ CLK and the expected value is not "false" by "0"; therefore, the comparison result between the count value of the PLL _ CLK and the expected value can be determined according to the level of the output signal of the counter comparison circuit 005. In the case where the comparison result between the count value of PLL _ CLK and the expected value matches, that is, the frequency test result of the clock circuit corresponding to PLL _ CLK is correct, the clock circuit is normal, whereas in the case where the comparison result between the count value of PLL _ CLK and the expected value does not match, that is, the frequency test result of the clock circuit corresponding to PLL _ CLK is erroneous, the clock circuit malfunctions.

It should be further noted that the counter comparison circuit 005 can also implement a mask function, i.e. remove error bits that may exist in the comparison data. Since the clock counter to be measured 001 is asynchronously clocked by the reference clock counter 002, there is a possibility that the clock counter to be measured 001 may have an error in both the start and end of counting during the counting of the PLL _ CLK. The counter comparison circuit 005 can remove an error in the count value of the PLL _ CLK by the mask function and then compare the count value with an expected value, thereby improving the comparison accuracy.

The clock frequency detection circuit in this embodiment further includes a frequency measurement control chain 006 and a frequency measurement feedback register 007, and the frequency measurement control chain 006 and the frequency measurement feedback register 007 can form a complete shift register chain. According to the input SI, the frequency measurement control chain 006 may send the control register data of the OCC and the expected value corresponding to the PLL _ CLK to the expected value storage logic 004 in a scan shift mode, sample the output result of the counter comparison circuit 005 to the frequency measurement feedback register 007 in a scan capture mode, and send the output result as the output signal SO to the ATE machine for test comparison in the scan shift mode. Therefore, the SI constitutes a chain test vector in this embodiment, i.e., data shifting and collection are achieved.

Example 2

This embodiment provides a clock control circuit, which includes the clock frequency detection circuit described in embodiment 1, and fig. 6 is a functional schematic diagram (one) of the clock control circuit provided in the embodiment of the present invention, as shown in fig. 6, the clock control circuit in this embodiment includes:

a first input module 202 configured to input a first clock signal;

the control module 204 is configured to control the first clock signal, obtain a chain test vector, and send the chain test vector to a control chain module in the clock frequency detection circuit.

It should be further noted that the clock control circuit in this embodiment may be an OCC circuit, or may be other circuits for implementing the related clock control function, which is not limited in this disclosure.

It should be further described that, in the control module in this embodiment, the clock control circuit performs control processing on a corresponding module, and the control module can meet the clock control requirement of the clock control circuit in DFT. On this basis, the control module in this embodiment can also control the first clock signal and obtain the chain test vector to send to the clock frequency detection circuit, that is, the clock control module in this embodiment can also detect the clock frequency.

Through the clock control circuit in the embodiment, the clock frequency detection circuit in the embodiment can be arranged in the clock control circuit, the control module is used for controlling the first clock signal, the serial chain test vector is obtained, and the serial chain test vector is sent to the control chain module in the clock frequency detection circuit. Therefore, the clock control circuit in this embodiment can solve the problems of the related art that the test cost is too high and the complexity of the test design is large in the process of detecting the clock network frequency on the chip, so as to achieve the effects of reducing the equipment and time cost when detecting the clock network frequency on the chip and reducing the complexity of the test design.

The chain test vector is an existing vector of the control module in the process of controlling the clock control circuit to perform clock control, and the chain test vector is sent to the control chain module in the clock frequency detection circuit to execute corresponding operation, so that the clock frequency detection in the clock frequency detection circuit can be realized on the basis of the existing chain test vector. Therefore, the process of detecting the clock frequency in this embodiment is completely based on the control manner of the existing clock control circuit, and does not involve using an additional test pin or test adjacency for detection.

Generally speaking, the clock control circuit in this embodiment is designed to implement DFT, so that the clock control circuit needs to cover the whole clock network in the chip, and therefore, the clock control circuit in this embodiment can detect the quality of all clocks in the chip, thereby significantly improving the coverage of the clock quality test.

In addition, all devices related to the clock control circuit in the embodiment can be realized by adopting resources in a standard cell library in the circuit design, so that the clock control circuit in the embodiment does not bring extra design and integration cost in the realization process. On the other hand, the serial test vector in the clock control circuit in this embodiment is used for clock control, so that the control of the serial test vector on the clock frequency detection in this embodiment can be completed in the clock control process, that is, the clock frequency detection process can be completed while performing the scan test, thereby avoiding extra time overhead and significantly reducing time cost.

In an optional embodiment, the clock control circuit further includes:

a second input module 206 configured to input a second clock signal;

the control module 204 is further configured to control the second clock signal.

It should be further noted that fig. 7 is a functional schematic diagram (ii) of a clock control circuit provided according to an embodiment of the present invention, and the arrangement of the second input module is shown in fig. 7.

In an alternative embodiment, the control module 204 is configured to:

and controlling the first clock signal and/or the second clock signal to be switched off and switched on and outputting the corresponding output clock signal.

The clock frequency detection circuit included in the clock control circuit in the present embodiment includes:

the comparison module is configured to compare the calculated value with an expected value of the first clock signal in a first period to obtain a comparison result;

and the control chain module is configured to acquire an expected value according to the serial chain test vector, send the expected value to the comparison module, acquire a comparison result according to the serial chain test vector and perform frequency detection on the clock to be tested according to the comparison result.

In an optional embodiment, the measurement module further includes a second clock counter configured to count a second clock signal in a second period;

In an optional embodiment, the comparing module includes:

an expected value storage unit configured to store an expected value;

and the comparison unit is configured to acquire the count value and the expected value and compare the count value with the expected value to acquire a comparison result.

In an optional embodiment, the comparison circuit is further configured to:

removing the error in the count value according to the preset error bit;

In an optional embodiment, the control chain module includes an expected value register and a comparison result register; the control chain module is also configured to,

In an optional embodiment, the control chain module is further configured to send the comparison result to an external automatic test equipment ATE to perform frequency detection on the clock to be tested.

The remaining optional technical solutions and technical effects of the clock frequency detection circuit in this embodiment correspond to those of the clock frequency detection circuit in embodiment 1, and therefore are not described herein again.

To further explain the clock control circuit in the present embodiment, the configuration and operation of the clock control circuit in the present embodiment will be explained below by way of a specific embodiment.

Detailed description of the invention

Fig. 8 is a schematic circuit diagram of a clock control circuit according to an embodiment of the present invention, and the input, output, and internal configuration of the clock control circuit in the embodiment are described in detail below with reference to fig. 8.

In the clock control circuit in this embodiment, the input signal includes:

1) ATE _ CLK: the low-speed clock signal, i.e. the second clock signal in the above embodiment, is directly input by the external ATE tester;

2) PLL _ CLK: in the embodiment, the PLL _ CLK is a clock signal indicating a frequency to be detected in the clock control circuit;

3) OCC _ CTRLs: the OCC _ CTRLs can be of various types according to different control requirements or purposes, for example, a scan shift enable signal shift _ en, a data acquisition signal capture _ en, an OCC reset signal OCC _ RST and the like;

4) SCAN _ IN: the OCC internal clock controls the input signal of the chain.

In the clock control circuit in this embodiment, the output signal includes:

1) OCC _ CLK: clock signals are output from PLL _ CLK, SCANSHIFT, low-speed Capture mode selection ATE _ CLK and high-speed Capture mode selection PLL _ CLK under the function mode;

2) SCAN _ OUT: the OCC internal clock controls the output signal of the chain.

The internal structure of the clock control circuit in this embodiment specifically includes:

ATE clock gating 011, PLL clock gating 012, OCC clock selector 013, and OCC control module 014; the ATE clock gate 011 is used for accessing an ATE _ CLK sent by an external ATE tester, and the PLL clock gate 012 is used for accessing a clock signal to be tested PLL _ CLK output by a phase-locked loop inside a chip. The ATE clock gating 011 can be controlled by the OCC control module 014 to realize the clock turn-on of ATE _ CLK in shift mode and low-speed capture mode and the clock turn-off function in high-speed capture mode; correspondingly, the PLL clock gating 012 is also controlled by the OCC control module 014 to implement the functions of clock-off of PLL _ CLK for shift mode and low-speed capture mode and clock-on and output clock number control for high-speed capture mode.

The OCC clock selector 013 is controlled by the OCC control module 014 to control the selection of OCC _ CLK in the different DFT modes. The OCC control module 014 controls the ATE clock gate 011, the PLL clock gate 012, and the OCC clock selector 013 according to the OCC _ CTRLs signal, that is, the OCC control module 014 controls the OCC _ CTRLs inputted from the outside, and the OCC control module 014 also controls the OCC control chain 015.

The OCC control chain 015 accesses an externally input SCAN _ IN to control the OCC control chain 015 to perform corresponding operations IN different modes. OCC control chain 015 may include a plurality of shift registers, and according to the indication of SCAN _ IN, OCC control chain 015 may shift the control signal for the OCC into OCC control module 014 IN SCAN shift mode.

The clock control circuit in this embodiment further includes a clock frequency detection module, which is the clock frequency detection circuit in the first embodiment. In this embodiment, the structure and the operation mode of the clock frequency detection module correspond to those of the clock frequency detection circuit in the first embodiment, and therefore are not described herein again.

It should be further noted that the clock frequency detection module may be disposed inside the clock control circuit, or may be disposed outside the clock control circuit, that is, disposed independently from the clock control circuit.

In this embodiment, ATE clock gating 011 and PLL clock gating 012 can respectively input ATE _ CLK and PLL _ CLK into the reference clock counter and the clock counter to be tested of the clock frequency detection module; meanwhile, a shift register chain formed by a frequency measurement control chain and a frequency measurement shift register in the clock frequency detection module can further form a longer shift register chain in the OCC with the OCC control chain 015 in this embodiment; the OCC internal shift register chain can send the control register data of the OCC and the expected value of the PLL _ CLK clock counter into the shift register chain in a shifting mode.

A specific method for detecting the clock frequency of the clock control circuit is described below, fig. 9 is a flowchart for detecting the clock frequency of the clock control circuit according to an embodiment of the present invention, and as shown in fig. 9, the specific method for detecting the clock frequency of the clock control circuit may be referred to as the following method:

s1, theoretically calculating an expected value Int _ M, specifically, theoretically calculating an expected value Int _ M of a clock to be frequency-detected counting in a corresponding first period, for the clock to be detected PLL _ CLK, acquiring PLL _ CLK clock frequency information Frq _ T, ATE _ CLK clock frequency Frq _ R input by an external ATE machine, and a fixed period Cnt _ R corresponding to the ATE _ CLK, and calculating an expected value of the clock counter to be detected PLL _ CLK counting in a fixed period according to the above information, that is:

[ Cnt _ R × Frq _ T/Frq _ R ]; [] Represents rounding up;

it should be further explained that, if there are multiple clocks to be tested, the Int _ M calculation process as above needs to be repeated for each clock to be tested;

s2, adding ATPG constraint, specifically, adding related constraint in scan ATPG environment, where the ATPG constraint indicates to send the expected value obtained in S1 to the corresponding register, and setting the expected comparison result output value in the counter comparison circuit in the clock frequency detection module; the process of adding the ATPG constraint comprises the following steps: the guiding tool respectively sends the expected value Int _ M corresponding to the PLL _ CLK of each clock to be tested into the frequency measurement control chain of the clock frequency detection module in the clock control circuit where each clock to be tested is located in the scan shift process, and adds ATPG constraint to make the input values of the frequency measurement feedback registers 202 corresponding to all the clocks to be tested be "1", that is, the input state is "true";

s3, SCAN ATPG and test, specifically, vector generation by ATPG and simulation or ATE test are carried out, if the clock frequency of OCC on a clock network is abnormal (the expected value is inconsistent with the measured value), SCAN simulation or ATE test will have errors, therefore, chips with abnormal clocks can be screened out through SCAN vector synchronization, and the fail of the frequency measurement feedback register 202 in which OCC is specifically located can be analyzed and positioned through ATPG diagnose, so that which clock has a problem can be further judged.

Example 3

This embodiment provides a chip, which includes the clock control circuit described in embodiment 2, and in the chip in this embodiment, the technical scheme and technical effect corresponding to the clock control circuit correspond to the clock control circuit in embodiment 2, so details are not described here.

Example 4

The present embodiment provides a clock frequency detection method, and fig. 10 is a flowchart of the clock frequency detection method according to the embodiment of the present invention, as shown in fig. 10, the frequency detection method in the present embodiment includes:

s302, obtaining an expected value of a first clock signal for counting in a first period, wherein the first clock signal is a clock signal input by a clock to be tested;

s304, acquiring a count value of the first clock signal counted in a first period;

s306, obtaining a comparison result of comparing the count value with the expected value according to the serial chain test vector so as to carry out frequency detection on the clock to be detected.

By the clock frequency detection method in the embodiment, because the expected value and the count value of the first clock signal counted in the first period can be obtained, and the comparison result of comparing the count value and the expected value is obtained according to the serial chain test vector, the frequency of the clock to be detected is detected; therefore, the clock frequency detection method in the embodiment can solve the problems of overhigh test cost and higher complexity of test design in the process of detecting the clock network frequency in the chip in the related technology, so as to achieve the effects of reducing the equipment and time cost in the process of detecting the clock network frequency in the chip and reducing the complexity of the test design.

In an optional embodiment, in the step S304, obtaining a count value of the first clock signal counted in the first period includes:

configuring a second clock signal to count in a second period, wherein the second clock signal is a clock signal input by peripheral Automatic Test Equipment (ATE), and the second period is a preset inherent period of the second clock signal;

the first period and the second period are set to be synchronous so as to obtain a count value of the first clock signal counting in the first period.

It should be further noted that the first period is synchronized with the second period, and indicates that the first period counted by the first clock counter is referenced to the second period, and is synchronized with the second period, i.e., the actual period counted by the first clock counter is the second period. The first clock counter counts in a second period, and the specific period information of the second period can be sent to the control part of the first clock counter for control, or when the second clock counter counts in a natural period, that is, the second period, the first clock counter counts when the second clock counter starts counting, and stops counting when the second clock counter finishes counting, that is, the first clock counter counts with the second clock counter as a reference; the present invention does not limit the specific counting manner of the first clock counter.

In an optional embodiment, the obtaining an expected value of the first clock signal counted in the first period in step S302 includes:

the expected value is obtained from: the second period, the frequency information of the first clock signal, and the frequency information of the second clock signal.

In an optional embodiment, in the step S306, obtaining a comparison result of comparing the count value with the expected value according to the chaining test vector includes:

removing the error in the count value according to the preset error bit;

and obtaining a comparison result of the count value and the expected value after the error is removed according to the serial chain test vector.

In an optional embodiment, in the step S306, obtaining a comparison result of comparing the count value with the expected value according to the serial test vector to perform frequency detection on the clock to be tested, includes:

under the condition that the count value is consistent with the expected value, judging that the frequency of the clock to be tested is normal; alternatively, the first and second electrodes may be,

and judging that the frequency of the clock to be tested is abnormal under the condition that the counting value does not accord with the expected value.

Through the above description of the embodiments, those skilled in the art can clearly understand that the method according to the above embodiments can be implemented by software plus a necessary general hardware platform, and certainly can also be implemented by hardware, but the former is a better implementation mode in many cases. Based on such understanding, the technical solutions of the present invention may be embodied in the form of a software product, which is stored in a storage medium (e.g., ROM/RAM, magnetic disk, optical disk) and includes instructions for enabling a terminal device (e.g., a mobile phone, a computer, a server, or a network device) to execute the method according to the embodiments of the present invention.

Example 5

The present embodiment provides a clock frequency detection apparatus, which is used to implement the foregoing embodiments and preferred embodiments, and the description of the apparatus is omitted here. As used below, the term "module" may be a combination of software and/or hardware that implements a predetermined function. Although the means described in the embodiments below are preferably implemented in software, an implementation in hardware, or a combination of software and hardware is also possible and contemplated.

Fig. 11 is a block diagram of a clock frequency detection apparatus according to an embodiment of the present invention, and as shown in fig. 11, the apparatus includes:

a first obtaining module 402, configured to obtain an expected value of a first clock signal counted in a first period, where the first clock signal is a clock signal input by a clock to be tested;

a second obtaining module 404, configured to obtain a count value of the first clock signal counted in the first period;

the comparing module 406 is configured to obtain a comparison result of comparing the count value with the expected value according to the serial link test vector, so as to perform frequency detection on the clock to be tested.

By the clock frequency detection device in the embodiment, because the expected value and the count value of the first clock signal counted in the first period can be obtained, and the comparison result of comparing the count value and the expected value is obtained according to the serial chain test vector, the frequency of the clock to be detected is detected; therefore, the clock frequency detection device in this embodiment can solve the problems of the related art that the test cost is too high and the complexity of the test design is large in the process of detecting the clock network frequency on the chip, so as to achieve the effects of reducing the equipment and time cost when detecting the clock network frequency on the chip and reducing the complexity of the test design.

The remaining optional technical solutions and technical effects of the clock frequency detection apparatus in this embodiment correspond to those of the clock frequency detection method in embodiment 3, and therefore are not described herein again.

In an optional embodiment, the obtaining a count value of the first clock signal counted in the first period includes:

In an optional embodiment, the obtaining an expected value of the first clock signal counted in the first period includes:

In an optional embodiment, the obtaining a comparison result of comparing the count value with the expected value according to the chaining test vector includes:

removing the error in the count value according to the preset error bit;

In an optional embodiment, the obtaining a comparison result of comparing the count value with the expected value according to the serial test vector to perform frequency detection on the clock to be tested includes:

It should be noted that, the above modules may be implemented by software or hardware, and for the latter, the following may be implemented, but not limited to: the modules are all positioned in the same processor; alternatively, the modules are respectively located in different processors in any combination.

Example 6

Embodiments of the present invention also provide a computer-readable storage medium, in which a computer program is stored, wherein the computer program is configured to perform the steps of any of the above-mentioned method embodiments when executed.

Alternatively, in the present embodiment, the above-mentioned computer-readable storage medium may be configured to store a computer program for executing the steps of:

s1, obtaining an expected value of a first clock signal for counting in a first period, wherein the first clock signal is a clock signal input by a clock to be tested;

s2, acquiring a count value of the first clock signal counted in the first period;

and S3, obtaining a comparison result of comparing the count value with the expected value according to the serial chain test vector, so as to carry out frequency detection on the clock to be detected.

Optionally, the specific examples in this embodiment may refer to the examples described in the above embodiments and optional implementation manners, and this embodiment is not described herein again.

Optionally, in this embodiment, the storage medium may include, but is not limited to: various media capable of storing computer programs, such as a usb disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a removable hard disk, a magnetic disk, or an optical disk.

Example 7

Embodiments of the present invention also provide an electronic device comprising a memory having a computer program stored therein and a processor arranged to run the computer program to perform the steps of any of the above method embodiments.

Optionally, the electronic apparatus may further include a transmission device and an input/output device, wherein the transmission device is connected to the processor, and the input/output device is connected to the processor.

Optionally, in this embodiment, the processor may be configured to execute the following steps by a computer program:

It will be apparent to those skilled in the art that the modules or steps of the present invention described above may be implemented by a general purpose computing device, they may be centralized on a single computing device or distributed across a network of multiple computing devices, and alternatively, they may be implemented by program code executable by a computing device, such that they may be stored in a storage device and executed by a computing device, and in some cases, the steps shown or described may be performed in an order different than that described herein, or they may be separately fabricated into individual integrated circuit modules, or multiple ones of them may be fabricated into a single integrated circuit module. Thus, the present invention is not limited to any specific combination of hardware and software.

The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A clock frequency detection circuit, comprising:

2. The circuit of claim 1, wherein the measurement module further comprises a second clock counter configured to count a second clock signal for a second period;

the second clock signal is a clock signal input by external Automatic Test Equipment (ATE), and the second period is a preset inherent period of the second clock signal; the first period is synchronous with the second period.

3. The circuit of claim 2, wherein the expected value is obtained from:

the second period, frequency information of the first clock signal, and frequency information of the second clock signal.

4. The circuit of claim 1, wherein the comparison module comprises:

an expected value storage unit configured to store the expected value;

and the comparison unit is configured to acquire the count value and the expected value and compare the count value with the expected value to acquire the comparison result.

5. The circuit of claim 4, wherein the comparison unit is further configured to:

removing the error in the count value according to a preset error bit;

and comparing the count value with the expected value after the error is removed to obtain the comparison result.

6. The circuit of any of claims 1 to 5, wherein the control chain module comprises an expected value register, a comparison result register; the control chain module is further configured to,

according to the serial chain test vector, indicating the expected value register to obtain the expected value in a serial chain data shifting mode, and sending the expected value to the comparison module; and/or the presence of a gas in the gas,

and indicating the comparison result register to obtain the comparison result in a serial chain data acquisition mode according to the serial test vector, and carrying out frequency detection on the clock to be tested according to the comparison result.

7. The circuit of claim 6, wherein the control chain module is further configured to send the comparison result to peripheral Automated Test Equipment (ATE) for frequency detection of the clock under test.

8. A clock control circuit comprising the clock control circuit of any one of claims 2 to 7; the clock control circuit further includes:

a first input module configured to input the first clock signal;

9. The circuit of claim 8, wherein the clock control circuit further comprises:

a second input module configured to input the second clock signal;

the control module is further configured to control the second clock signal.

10. The circuit of claim 9, wherein the control module is configured to:

and controlling the first clock signal and/or the second clock signal to be switched off and switched on and outputting a corresponding output clock signal.

11. A chip comprising a clock control circuit as claimed in any one of claims 8 to 10.

12. A method of clock frequency detection, the method comprising:

acquiring a count value of the first clock signal counted in the first period;

13. The method of claim 12, wherein obtaining the count value of the first clock signal counted during the first period comprises:

and setting the first period and the second period to be synchronous so as to obtain a count value of the first clock signal counted in the first period.

14. The method of claim 13, wherein obtaining an expected value for the first clock signal to count over the first period comprises:

obtaining the expected value according to the following objects: the second period, frequency information of the first clock signal, and frequency information of the second clock signal.

15. The method of any of claims 12 to 14, wherein obtaining the comparison of the count value to the expected value based on a string test vector comprises:

removing the error in the count value according to a preset error bit;

16. The method according to any one of claims 12 to 14, wherein the obtaining a comparison result of the count value and the expected value according to a chain test vector for performing frequency detection on the clock under test comprises:

and under the condition that the count value does not accord with the expected value, judging that the frequency of the clock to be tested is abnormal.

17. A clock frequency detection apparatus, the apparatus comprising:

18. A computer-readable storage medium, in which a computer program is stored, wherein the computer program is configured to carry out the method of any one of claims 12 to 16 when executed.

19. An electronic device comprising a memory and a processor, wherein the memory has stored therein a computer program, and wherein the processor is arranged to execute the computer program to perform the method of any of claims 12 to 16.