CN112701112A - Buck circuit silicon carbide power module - Google Patents
Buck circuit silicon carbide power module Download PDFInfo
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- CN112701112A CN112701112A CN202011589380.9A CN202011589380A CN112701112A CN 112701112 A CN112701112 A CN 112701112A CN 202011589380 A CN202011589380 A CN 202011589380A CN 112701112 A CN112701112 A CN 112701112A
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- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 title claims abstract description 69
- 229910010271 silicon carbide Inorganic materials 0.000 title claims abstract description 69
- 239000000758 substrate Substances 0.000 claims abstract description 25
- 239000002184 metal Substances 0.000 claims abstract description 4
- 229910052751 metal Inorganic materials 0.000 claims abstract description 4
- 238000003466 welding Methods 0.000 claims description 2
- 230000003071 parasitic effect Effects 0.000 abstract description 15
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract description 8
- 229910052802 copper Inorganic materials 0.000 abstract description 8
- 239000010949 copper Substances 0.000 abstract description 8
- 239000000919 ceramic Substances 0.000 abstract description 4
- 238000010586 diagram Methods 0.000 description 7
- 239000000463 material Substances 0.000 description 6
- 238000000034 method Methods 0.000 description 6
- 239000004065 semiconductor Substances 0.000 description 6
- 238000006243 chemical reaction Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000017525 heat dissipation Effects 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000007935 neutral effect Effects 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
- H01L25/071—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next and on each other, i.e. mixed assemblies
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5386—Geometry or layout of the interconnection structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
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- Microelectronics & Electronic Packaging (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
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Abstract
The invention discloses a buck circuit silicon carbide power module, and belongs to the technical field of power electronics. The power module includes: the bottom layer is directly coated with a copper ceramic DBC substrate; the silicon carbide power chip, the driving resistor, the power terminal and the driving terminal are attached to the bottom DBC substrate, and the silicon carbide power chip and the driving resistor form two buck half-bridge circuits; the silicon carbide power chips are connected through metal bonding wires; the bottom layer is directly welded on the bottom plate through the copper-clad ceramic DBC substrate. The power module provided by the invention optimizes the commutation loop through reasonable DBC copper layer layout, realizes the balance of parallel chip loops, greatly reduces the parasitic inductance of the loops, reduces the volume of the module and improves the power density of the module.
Description
Technical Field
The invention belongs to the technical field of power electronics, and particularly relates to a buck circuit silicon carbide power module.
Background
buck half-bridge circuits are widely used in a variety of electronic devices. However, the power devices used by the conventional commercial buck half-bridge module still mainly comprise silicon-based devices, and the circuit has low current-carrying capacity and high loss and is not suitable for being used in high-power-level circuits.
Silicon carbide devices have higher current carrying capability, higher switching speed, lower switching losses, and are capable of operating at higher temperatures than silicon-based devices. However, the parasitic inductance of the current conversion loop of the existing commercial silicon carbide module is generally large, and the switching voltage and current stress borne by the silicon carbide device can be increased. In addition, the current carrying capacity between single silicon carbide chips is limited, and the current carrying capacity of a module is often improved by connecting a plurality of power chips in parallel in a high-power occasion, however, the current imbalance among the chips connected in parallel is caused by different parasitic inductance introduced into a driving circuit.
Based on the above circumstances, there is an urgent need for a buck circuit silicon carbide power module which can realize low parasitic inductance, current equalization of parallel power chips and high current-carrying capacity.
Disclosure of Invention
Aiming at the defects of the prior art, the invention aims to provide a buck circuit silicon carbide power module, which aims to solve the problems of overhigh parasitic inductance, non-uniform current of a switching tube and low power density of the conventional buck power module.
In order to achieve the above object, the present invention provides a buck circuit silicon carbide power module, including: the silicon carbide power chip and the driving resistor form two buck half-bridge circuits which comprise a first buck half-bridge circuit and a second buck half-bridge circuit; the silicon carbide power chips are connected through metal bonding wires; the bottom layer is directly welded on the bottom plate through the copper-clad ceramic DBC substrate.
Further, the DBC substrate includes:
a thermally conductive layer to conduct heat from the silicon carbide power chip out of the power module;
the insulating layer is positioned between the heat conducting layer and the circuit layer, and the circuit layer is connected with the corresponding port of the silicon carbide power chip in a welding mode.
Further, the DBC substrate circuit layer includes a first chip region, a second chip region, a third chip region, a fourth chip region, a first negative electrode connection region, a second negative electrode connection region, a first control region, a second control region, a third control region, and a fourth control region; the first chip area, the second chip area and the first negative electrode connecting area are sequentially arranged to form a rectangular area, the first chip area is in a shape of 'pi', the second chip area is in a shape of 'mountain', the first chip area and the second chip area are arranged in a staggered mode from top to bottom, and the first negative electrode connecting area is formed by two polygonal areas and filled in a groove in the middle of the second chip area; the first control area is located above the first chip area, and the second control area is located below the second chip area. The third chip area is in a shape of pi, the fourth chip area is in a shape of Chinese character 'shan', the third chip area and the fourth chip area are arranged up and down and are placed together in a staggered mode, and the second negative electrode connecting area is composed of two polygonal areas and is filled in a groove in the middle of the fourth chip area; the third control area is located above the third chip area, and the fourth control area is located below the fourth chip area. The length of the loop is reduced through reasonable layout design among different connection areas, so that parasitic inductance of a current conversion loop is reduced, the reliability of the module is improved, the buck circuit can work under higher voltage level and higher switching frequency, and the power density of the module is effectively improved.
Furthermore, the first chip area and the second chip area are adjacently and closely placed up and down, and the first negative electrode connecting area is arranged at the groove in the middle of the first chip area and the second chip area, so that the space is fully utilized on the premise of ensuring insulation safety, and the increase of the module volume is avoided.
Furthermore, the first control area and the second control area are arranged on two sides of the first chip area and the second chip area in parallel and are arranged in parallel with the silicon carbide power chips in parallel, so that the driving circuit paths of the chips in parallel are consistent, and the balance of the switch driving performance is realized.
Furthermore, the placing direction of the parallel silicon carbide power chips is vertical to the connecting direction of bonding wires of the parallel silicon carbide power chips, so that the lengths of main power loops of the parallel chips are basically consistent, and good dynamic current sharing and stable current sharing performances are achieved.
Further, the first buck half-bridge circuit and the second buck half-bridge circuit are symmetrically distributed about a neutral line of the power module.
Through the technical scheme, compared with the prior art, the buck circuit silicon carbide power module provided by the invention has the advantages that the silicon carbide semiconductor chip is welded on the DBC substrate through the chip interconnection technology, and compared with the conventional power module, the module can work at higher frequency and higher temperature by using the silicon carbide semiconductor device, so that the working performance of the module can be effectively improved. Meanwhile, the parallel power chips inside the module are symmetrically distributed, and the direction of the bonding wire is vertical to the placing direction of the parallel chips, so that the length of the parallel loop is consistent. Furthermore, aiming at the characteristic that the silicon carbide chip is sensitive to parasitic inductance, the invention provides a novel layout of a DBC circuit layer connecting area, and the circuit layout is optimized by arranging the combined placement positions of different connecting areas, so that the low parasitic parameters of the module and the current sharing of the parallel chips are realized.
Drawings
Fig. 1 is a schematic structural diagram of a power module according to an embodiment of the present invention;
FIG. 2 is a topology diagram of a first buck half-bridge circuit configuration according to an embodiment of the present invention;
fig. 3 is a schematic diagram of a DBC substrate structure provided in an embodiment of the present invention;
fig. 4 is a schematic diagram of the distribution of the connection regions of the circuit layers of the DBC plate according to an embodiment of the present invention.
Detailed Description
The following detailed description of the embodiments of the present invention will be provided with reference to the drawings and examples, so that how to apply the technical means to solve the technical problems and achieve the technical effects can be fully understood and implemented. It should be noted that, as long as there is no conflict, the embodiments and the features of the embodiments of the present invention may be combined with each other, and the technical solutions formed are within the scope of the present invention.
In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the embodiments of the invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without some of these specific details or with other methods described herein.
The invention provides a buck circuit silicon carbide power module, which comprises: the silicon carbide power chip and the driving resistor form two buck half-bridge circuits which comprise a first buck half-bridge circuit and a second buck half-bridge circuit; the silicon carbide power chips are connected through metal bonding wires; the bottom layer is directly welded on the bottom plate through the copper-clad ceramic DBC substrate.
Examples
Fig. 1 shows a schematic structural diagram of a buck circuit silicon carbide power module provided in this example, which includes DBC substrates 101 and 102, a silicon carbide power chip 201a, a silicon carbide power chip 201b, a silicon carbide power chip 202a, a silicon carbide power chip 202b, positive power terminals 301 and 302, negative power terminals 401 and 402, output power terminals 501 and 502, a driving terminal 601a, a driving terminal 601b, a driving terminal 602a, a driving terminal 602b, a driving resistor 7, a bottom board 8, and a package case 9. The silicon carbide power chip 201a and the silicon carbide power chip 201b form a first buck half-bridge circuit and are welded on the DBC substrate 101, and the silicon carbide power chip 202a and the silicon carbide power chip 202b form a second buck half-bridge circuit and are welded on the DBC substrate 102.
Fig. 2 shows a schematic circuit diagram of the first buck half-bridge circuit of the present example. The first buck half-bridge circuit in this example includes a silicon carbide power chip 201a, a silicon carbide power chip 201 b. The silicon carbide power chip 201a forms an upper bridge arm of the first buck half-bridge circuit, and the silicon carbide power chip 201b forms a lower bridge arm of the first buck half-bridge circuit. The second buck half-bridge circuit has the same structure as the first buck half-bridge circuit, and is not described herein. It should be noted that, the two buck half-bridge circuits mentioned in this embodiment may use one half-bridge circuit alone, or may use two half-bridge circuits simultaneously, and the present invention is not limited to this application.
Preferably, the silicon carbide power chips 201a, 202a, 201b and 202b used in this embodiment are formed by connecting 6 silicon carbide MOSFET power chips in parallel, so that the current carrying capacity of the module can be improved. Meanwhile, the silicon carbide power chips 201a and 201b are symmetrically distributed about the horizontal axis of the module, so that the length balance of the parallel power loop can be realized, the loop connection distance is reduced, and the loop parasitic inductance is reduced. The silicon carbide power chip 202a and the silicon carbide power chip 202b form a second buck half-bridge circuit, which is consistent with the first buck half-bridge circuit loop layout and is not described herein again.
It should be further noted that, in the present embodiment, each power semiconductor chip included in the buck circuit may be implemented by using a different chip, and the present invention is not limited thereto. For example, in one embodiment of the present invention, a silicon carbide MOSFET chip with a freewheeling diode may be employed.
Further, it should be noted that, in different embodiments of the present invention, each power semiconductor chip included in the buck circuit may be implemented by using a different number of chips in parallel, and the present invention is not limited thereto. For example, in one embodiment of the present invention, 6 silicon carbide power chips may be employed in parallel.
In the present embodiment, 4 copper pillar terminals are used for each of the positive power terminals 301 and 302 and the negative power terminals 401 and 402, and 6 copper pillar terminals are used for each of the output power terminals 501 and 502. And the multiple terminals are symmetrically distributed, so that the electrified current of each copper column can be reduced, and the stability is improved. Meanwhile, the layout positions of the positive power terminal and the negative power terminal are optimized, and the positive power terminal and the negative power terminal are placed in parallel and relatively close to each other as far as possible on the premise of ensuring insulation, so that the length of a loop is reduced, and the parasitic inductance of the loop is reduced.
It is noted that in different embodiments of the present invention, the power terminals may be implemented using different numbers of differently shaped terminals, and the present invention is not limited thereto. For example, in one embodiment of the present invention, the positive power terminal employs 4 copper pillar terminals and the output power terminal employs 6 copper pillar terminals.
In this embodiment, 4 driving terminals are distributed at four corners of the module. The driving terminals 601a are connected to the gates of the respective parallel power chips of the silicon carbide power chip 201a through different driving resistors 7. The driving resistor and the parallel power chip of 201a are oppositely arranged in parallel. When the module works, a driving signal is transmitted to the grid electrode of the silicon carbide power chip 201a through the driving resistor, and the power chip is controlled to be turned off. Because the distances from the parallel power chips of the silicon carbide power chip 201a to the driving terminal 601a are different, the parasitic inductance of the driving loop is different, and the switching speeds of the multiple parallel power chips of 201a are consistent by changing the resistance value of the driving resistor 7, so that the current sharing among the multiple parallel chips is realized. The current sharing principle of the silicon carbide power chip 201b, the silicon carbide power chip 202a and the silicon carbide power chip 202b is the same as that of the power chip 201a, and the description thereof is omitted.
Fig. 3 shows a schematic structural view of the DBC substrates 101 and 102 of the present embodiment. The DBC substrate 101 includes a circuit layer 1a, an insulating layer 1b, and a heat dissipation layer 1 c. The power chip, the power terminal and the driving terminal are welded on the circuit layer. The circuit layer 1a is made of an oxygen-free copper material, and the surface of the circuit layer is subjected to nickel plating treatment, so that the oxidation resistance of the surface is enhanced, and the wire bonding is facilitated. The insulating layer 1b is made of AlN material. The heat generated in the working process of the power chip is conducted to the heat dissipation layer through the circuit layer and the insulating layer to dissipate the heat. The DBC substrates 102 and 101 have the same structure and are not described in detail herein.
Fig. 4 shows a schematic diagram of the connection region distribution of the circuit layers of the DBC substrates 101 and 102 of the present embodiment. The chip comprises a first chip area 101a, a second chip area 101b, a third chip area 102a, a fourth chip area 102b, a first negative electrode connection area 101c, a second negative electrode connection area 102c, a first control area 101d, a second control area 101e, a third control area 102d and a fourth control area 102 e. The drain and positive power terminal 301 of the sic power chip 201a is soldered on the first chip region 101a, the drain and output power terminal 501 of the sic power chip 201b is soldered on the second chip region 101b, and the negative power terminal 401 is soldered on the first negative connection region 101 c. The driving terminal 601a is soldered to the first control area 101d, and the driving terminal 601b is soldered to the second control area 101 e. The power chips are interconnected through bonding wires. The DBC substrate 101 and the DBC substrate 102 are axisymmetrically distributed about a module vertical center line. The connections of the power chip, the connection terminals, and the DBC substrate 102 circuit layer connection area are similar to those of the DBC substrate 101 circuit layer connection area, and are not described herein again.
In the implementation process of the module, the power chip, the power terminal and the driving terminal are firstly welded on the DBC substrate, then the power chip is connected in a lead bonding mode, then the DBC substrate is welded on the bottom plate, finally the module shell is sleeved on the bottom plate, and plastic package is carried out through the plastic sealing glue, so that the buck circuit silicon carbide power module shown in the figure 1 is constructed, and the advantages of simplified process, compact structure and light weight are achieved.
As can be seen from the above description, in the buck circuit silicon carbide power module provided in this embodiment, the power chip having a specific power conversion function is soldered on the circuit layer of the DBC substrate by a specific technology, and using the silicon carbide device, the module can operate at a higher switching frequency, so as to reduce the volume of the passive device of the module, reduce the loss in the module, and thus implement a high power density.
Further, by optimizing the layout arrangement of the circuit connection area of the circuit layer, the buck circuit commutation loop is symmetrical. And on the basis of ensuring the insulating condition of the module, the length of the commutation loop is reduced, and the problem of larger parasitic inductance introduced by a longer commutation loop can be avoided, so that the reliability of the module is ensured and the loss is reduced. Meanwhile, through the reasonable layout of the power chips in the circuit and the optimization of the driving resistance value, the influence of the parasitic inductance of a current conversion loop can be reduced, the current sharing among a plurality of parallel power chips is realized, and the operation reliability of the module is improved.
Further, the buck circuit silicon carbide power module provided by the example comprises two buck half-bridge circuits. They may be used either individually or simultaneously.
As can be seen from the above description, the embodiment provides a buck circuit silicon carbide power module, in which a silicon carbide semiconductor chip is soldered on a DBC substrate through a chip interconnection technology, and compared with an existing power module, by using a silicon carbide semiconductor device, the module can operate at a higher frequency and a higher temperature, and the working performance of the module can be effectively improved. Meanwhile, the parallel power chips inside the module are symmetrically distributed, and the direction of the bonding wire is vertical to the placing direction of the parallel chips, so that the length of the parallel loop is consistent. Furthermore, aiming at the characteristic that the silicon carbide chip is sensitive to parasitic inductance, the invention provides a novel layout of a DBC circuit layer connecting area, and the circuit layout is optimized by arranging the combined placement positions of different connecting areas, so that the low parasitic parameters of the module and the current sharing of the parallel chips are realized.
It is to be understood that the disclosed embodiments of the invention are not limited to the particular structures, process steps, or materials disclosed herein but are extended to equivalents thereof as would be understood by those ordinarily skilled in the relevant arts. It is also to be understood that the terminology used herein is for the purpose of describing particular embodiments only, and is not intended to be limiting.
Reference in the specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. Thus, the appearances of the phrase "one embodiment" or "an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment.
For convenience, a plurality of items, structural units, compositional units, and/or materials may be presented in a common list. However, these lists should be construed as though each element of the list is individually identified as a separate unique member. Thus, no element of a list should be construed as a de facto equivalent of any other element of the same list solely based on their presentation in a common list without indications to the contrary. In addition, various embodiments and examples of the present invention may also be referred to herein, along with alternatives for the various elements. It should be understood that these embodiments, examples and alternatives are not to be construed as equivalents to each other but are to be considered as independent representatives of the invention.
Furthermore, the described features, structures, or characteristics may be combined in any other suitable manner in one or more embodiments. In the above description, certain specific details are provided, such as lengths, heights, etc., to provide a thorough understanding of embodiments of the invention. One skilled in the relevant art will recognize, however, that the invention may be practiced without one or more of the specific details, or with other methods, components, materials, and so forth. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of the invention.
While the above examples are illustrative of the principles of the present invention in one or more applications, it will be apparent to those of ordinary skill in the art that various changes in form, usage and details of implementation can be made without departing from the principles and concepts of the invention. Accordingly, the invention is defined by the appended claims.
It will be understood by those skilled in the art that the foregoing is only a preferred embodiment of the present invention, and is not intended to limit the invention, and that any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (8)
1. A buck circuit silicon carbide power module, the power module comprising: the silicon carbide power chip and the driving resistor form two buck half-bridge circuits which comprise a first buck half-bridge circuit and a second buck half-bridge circuit; the silicon carbide power chips are connected through metal bonding wires.
2. The power module of claim 1, wherein the DBC substrate comprises:
a thermally conductive layer to conduct heat from the silicon carbide power chip out of the power module;
the insulating layer is positioned between the heat conducting layer and the circuit layer, and the circuit layer is connected with the corresponding port of the silicon carbide power chip in a welding mode.
3. The power module of claim 2, wherein the circuit layer comprises a first chip region, a second chip region, a third chip region, a fourth chip region, a first negative connection region, a second negative connection region, a first control region, a second control region, a third control region, a fourth control region; the first chip area, the second chip area and the first negative electrode connecting area are sequentially arranged to form a rectangular area, the first chip area is in a shape of 'pi', the second chip area is in a shape of 'mountain', the first chip area and the second chip area are arranged in a staggered mode from top to bottom, and the first negative electrode connecting area is formed by two polygonal areas and filled in a groove in the middle of the second chip area; the first control area is located above the first chip area, and the second control area is located below the second chip area.
4. The power module as claimed in claim 3, wherein the third chip region is "pi" shaped, the fourth chip region is "shan" shaped, and the third chip region and the fourth chip region are arranged and staggered up and down, and the second negative connection region is composed of two polygonal regions filled in the middle groove of the fourth chip region; the third control area is located above the third chip area, and the fourth control area is located below the fourth chip area.
5. The power module of claim 3, wherein the first chip region and the second chip region are closely positioned one above the other, and the first negative connection region is disposed between the first chip region and the second chip region.
6. The power module of claim 3, wherein the first control region and the second control region are disposed in parallel on opposite sides of the first chip region and the second chip region and in parallel with the parallel silicon carbide power chips.
7. The power module of claim 1 wherein the parallel silicon carbide power chips are placed in a direction perpendicular to their bond wire connections.
8. The power module of claim 1 wherein the first buck half-bridge circuit and the second buck half-bridge circuit are symmetrically distributed about a power module centerline.
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