CN112701034B - Method for manufacturing grid electrode - Google Patents
Method for manufacturing grid electrode Download PDFInfo
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- CN112701034B CN112701034B CN202011561763.5A CN202011561763A CN112701034B CN 112701034 B CN112701034 B CN 112701034B CN 202011561763 A CN202011561763 A CN 202011561763A CN 112701034 B CN112701034 B CN 112701034B
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- 238000000034 method Methods 0.000 title claims abstract description 52
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 22
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 88
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 58
- 229920005591 polysilicon Polymers 0.000 claims abstract description 58
- 239000004065 semiconductor Substances 0.000 claims abstract description 22
- 238000005530 etching Methods 0.000 claims abstract description 18
- 239000000758 substrate Substances 0.000 claims description 29
- 239000002184 metal Substances 0.000 claims description 10
- 229910052751 metal Inorganic materials 0.000 claims description 10
- 238000001259 photo etching Methods 0.000 claims description 7
- 150000004767 nitrides Chemical class 0.000 claims description 6
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 5
- 230000005669 field effect Effects 0.000 claims description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 3
- 238000002955 isolation Methods 0.000 claims description 3
- 238000010030 laminating Methods 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- 238000001312 dry etching Methods 0.000 abstract description 6
- 230000007547 defect Effects 0.000 abstract description 5
- 230000000694 effects Effects 0.000 abstract description 5
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 3
- 230000003247 decreasing effect Effects 0.000 description 3
- 230000007423 decrease Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000008719 thickening Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- PEUPIGGLJVUNEU-UHFFFAOYSA-N nickel silicon Chemical compound [Si].[Ni] PEUPIGGLJVUNEU-UHFFFAOYSA-N 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28079—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a single metal, e.g. Ta, W, Mo, Al
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/823456—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different shapes, lengths or dimensions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The invention relates to a manufacturing method of grid, which relates to a manufacturing technology of a semiconductor integrated circuit, and utilizes the ISO region loading effect to reduce the thickness of photoresist, so that the reduction rate of the photoresist in the ISO region is correspondingly slower to achieve the effect of reducing the thickness difference of the photoresist in different regions; and because the photoresist is thinned, the dry etching program strength of removing the photoresist on the top layer of the polysilicon gate by the EB1 can be correspondingly reduced, so that less photoresist can be consumed in the ISO region EB1, the defect window of the subsequent EB2 can be increased, the problem of insufficient OX residual and SIGE FILM DAMAGE process windows in the dry etching process can be solved, and the problem of defects after the dry etching process of the HK28 photoresist back etching process can be solved.
Description
Technical Field
The present invention relates to semiconductor integrated circuit manufacturing technology, and more particularly, to a method for manufacturing a gate.
Background
HKMG processes such as 28nm require the simultaneous formation of a high dielectric constant (HK) gate dielectric layer and a Metal Gate (MG), and post-metal gate processes are commonly used in existing HKMG processes. In the post-metal gate process, a Dummy gate structure, i.e., a polysilicon gate (Poly) of the Dummy gate structure, i.e., a Dummy polysilicon gate (Dummy Poly), is generally used to form a gate dielectric layer, a channel region, and a source drain region of the device, and then the metal gate is replaced, i.e., the polysilicon gate of the Dummy gate structure is removed (Dummy Poly remove, DPR), and then the removed region of the polysilicon gate is filled with metal to form the metal gate. A Hard Mask (HM) including an oxide layer is formed on top of the polysilicon gate before the polysilicon gate is removed, so that the oxide layer of the Hard Mask layer needs to be removed before the polysilicon gate is removed. In addition, the densities and sizes of the polysilicon gates on the semiconductor substrate are often different, and in particular, referring to fig. 1a, fig. 1a is a schematic view of a device structure in one of the conventional gate manufacturing processes, and as shown in fig. 1a, the semiconductor substrate 100 includes an open area 110, an isolated pattern area (ISO) 120, and a dense pattern area (density) 130, where the device density is gradually increased. And the dummy polysilicon gate structure includes a gate dielectric layer 210, a polysilicon gate 220, and a hard mask layer 230 formed of a first nitride layer 231 and a second oxide layer 232. And the polysilicon gate includes a large-sized polysilicon gate and a small-sized polysilicon gate.
The existing process of removing the oxide layer of the hard mask layer includes: step one, forming a photoresist 310; step two, opening photoresist on the bulk polysilicon gate through a photoetching process, as shown in a device structure schematic diagram of one of the existing gate manufacturing processes in FIG. 1 b; step three, the photoresist on the rest polysilicon gates is opened through Etching Back (EB) of a Photoresist (PR), namely EB1, mainly for overcoming the photoresist load (loading) on the bulk polysilicon gates, and all the polysilicon gates are opened at the moment, as shown in a device structure schematic diagram of one of the existing gate manufacturing processes in FIG. 1 c; step four, a second etching back process, EB2, is performed to remove the second oxide layer 232 of the hard mask layer, as shown in fig. 1d, which is a schematic device structure of one of the existing gate manufacturing processes. In the 28nm HKMG process, in order to avoid damage (damage) to other areas such as an active area and the like in the process of removing the oxide layer of the hard mask layer of the polysilicon gate, the other areas are protected by a photoresist, and after EB1, the residual quantity of the photoresist on the small polysilicon gate is particularly noted, and is too high, so that the photoresist on the polysilicon gate is not completely opened, and the hard mask layer cannot be completely removed; however, too low photoresist tends to cause silicon germanium (SGe) on the surfaces of Active Areas (AA) on both sides of the polysilicon gate and even no photoresist protection on AA, which eventually results in nickel silicide (Nisi) or SIGE DAMAGE, resulting in thinner photoresist thickness in the ISO region and thus insufficient OX remainder and SIGE FILM DAMAGE process windows during the dry etching process. This is mainly due to the difference in the heights of the photoresist in the different regions, as shown in fig. 1a, the photoresist 310 is higher by a distance of 110nm than the dummy gate structure H1 in the dense pattern region (density) 130, and is higher by a distance of 160nm than the substrate H1 in the open region 110. And the top height of the photoresist decreases sequentially from the dense pattern area (density) 130, the isolated pattern area (ISO) 120 to the open area 110.
In this regard, the main solution in the prior art is to increase the photoresist thickness as much as possible to reduce the loading effect of the photoresist filling and to compensate the problem of insufficient OX result and SIGE FILM DAMAGE process window during the dry etching process, but the actual product shows that it is difficult to reduce the problem by thickening the photoresist due to the oversized ISO area.
Disclosure of Invention
The invention provides a manufacturing method of a grid electrode, which comprises the following steps: s1: providing a semiconductor substrate, forming a gate dielectric layer and a polysilicon gate on the surface of the semiconductor substrate in sequence, forming a field oxide layer in the semiconductor substrate, isolating an active region by the field oxide layer, wherein the open region, the isolated pattern region and the dense pattern region are respectively positioned in different active regions; s2: forming a hard mask layer on the surface of the polysilicon gate, wherein the hard mask layer is formed by laminating a first nitride layer and a second oxide layer; s3: performing photoetching to form a plurality of pseudo gate structures, wherein each pseudo gate structure is formed by stacking the etched gate dielectric layer, the polysilicon gate and the hard mask layer; s4: forming side walls on the side surfaces of the pseudo gate structures; s5: forming a source region and a drain region of the device in the active regions at two sides of the pseudo gate structure, wherein a component enhancement process is included in the process of forming the source region and the drain region of the device, and the component enhancement process forms a germanium-silicon layer in the source region or the drain region of the p-type field effect transistor; s6: forming photoresist, wherein the photoresist is 15-25 nm higher than the pseudo gate structure in the dense pattern area, and is 90-110 nm higher than the substrate in the open area; s7: etching back the photoresist for the first time, and opening the photoresist on all polysilicon gates; s8: etching back the photoresist for the second time to remove the second oxide layer of the hard mask layer; s9: and removing the polysilicon gate, and forming a metal gate in the removed region of the polysilicon gate.
Further, the top height of the photoresist is sequentially reduced from the dense pattern region, the isolated pattern region to the open region in S6.
Further, in S6, the photoresist is 20nm higher than the dummy gate structure in the dense pattern region and 100nm higher than the semiconductor substrate in the open region.
Further, the photoresist is etched away from 45nm to 65nm in the back etching of the first photoresist in S7.
Further, the first photoresist etch back etches away 55nm of photoresist.
Further, S61 is included between S6 and S7: and opening the photoresist on the large polysilicon gate through a photoetching process.
Further, the semiconductor substrate is a silicon substrate.
Further, the gate dielectric layer includes a high dielectric constant layer.
Further, the field oxide layer is shallow trench field oxide.
Further, the shallow trench field oxide is formed by adopting a shallow trench isolation process
Drawings
Fig. 1 a-1 d are schematic views of a device structure in one of the prior art gate fabrication processes.
Fig. 2 a-2 c are schematic views of a device structure during one of the manufacturing processes of the gate electrode according to an embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made more apparent and fully hereinafter with reference to the accompanying drawings, in which some, but not all embodiments of the invention are shown. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
It should be understood that the present invention may be embodied in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size of layers and regions, as well as the relative sizes, may be exaggerated for the same elements throughout. It will be understood that when an element or layer is referred to as being "on" …, "" adjacent to "…," "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected to or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on" …, "" directly adjacent to "…," "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
Spatially relative terms, such as "under …," "under …," "below," "under …," "over …," "above," and the like, may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "below …" and "under …" may include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatially relative descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
In an embodiment of the present invention, a method for manufacturing a gate is provided, including: s1: providing a semiconductor substrate, forming a gate dielectric layer and a polysilicon gate on the surface of the semiconductor substrate in sequence, forming a field oxide layer in the semiconductor substrate, isolating an active region by the field oxide layer, wherein the open region, the isolated pattern region and the dense pattern region are respectively positioned in different active regions; s2: forming a hard mask layer on the surface of the polysilicon gate, wherein the hard mask layer is formed by laminating a first nitride layer and a second oxide layer; s3: performing photoetching to form a plurality of pseudo gate structures, wherein each pseudo gate structure is formed by stacking the etched gate dielectric layer, the polysilicon gate and the hard mask layer; s4: forming side walls on the side surfaces of the pseudo gate structures; s5: forming a source region and a drain region of the device in the active regions at two sides of the pseudo gate structure, wherein a component enhancement process is included in the process of forming the source region and the drain region of the device, and the component enhancement process forms a germanium-silicon layer in the source region or the drain region of the p-type field effect transistor; s6: forming photoresist, wherein the photoresist is 15-25 nm higher than the pseudo gate structure in the dense pattern area, and is 90-110 nm higher than the substrate in the open area; s7: etching back the photoresist for the first time, and opening the photoresist on all polysilicon gates; s8: etching back the photoresist for the second time to remove the second oxide layer of the hard mask layer; s9: and removing the polysilicon gate, and forming a metal gate in the removed region of the polysilicon gate.
Referring to fig. 2 a-2 c, fig. 2 a-2 c are schematic views of a device structure during one of the manufacturing processes of the gate according to an embodiment of the invention. The manufacturing method of the grid electrode of the embodiment of the invention comprises the following steps:
S1: as shown in fig. 2a, a semiconductor substrate 1000 is provided, a gate dielectric layer 2100 and a polysilicon gate 2200 are sequentially formed on the surface of the semiconductor substrate 1000, a field oxide layer 1010 is formed in the semiconductor substrate 1000, active regions are isolated by the field oxide layer 1010, and an open region 1100, an isolated pattern region (ISO) 1200 and a dense pattern region (density) 1300 are respectively located in different active regions.
The semiconductor substrate 1000 is a silicon substrate.
The gate dielectric layer 2100 includes a high dielectric constant layer.
And the device density of the open area 1100, the isolated pattern area (ISO) 1200, and the dense pattern area (density) 1300 gradually increases. And the polysilicon gates include large-sized polysilicon gates and small-sized polysilicon gates, such as the polysilicon gates in the isolated pattern area (ISO) 1200 being large-sized polysilicon gates and the polysilicon gates in the dense pattern area (density) 1300 being small-sized polysilicon gates.
The field oxide 1010 is shallow trench field oxide formed by shallow trench isolation process.
S2: as shown in fig. 2a, a hard mask layer 2300 is formed on the surface of the polysilicon gate 2200, and the hard mask layer 2300 is formed by stacking a first nitride layer 2310 and a second oxide layer 2320.
S3: as shown in fig. 2a, a plurality of dummy gate structures are formed by performing photolithography and etching, and each of the dummy gate structures is formed by stacking the etched gate dielectric layer 2100, the polysilicon gate 2200, and the hard mask layer 2300.
S4: as shown in fig. 2a, a sidewall 2400 is formed on the side of each of the dummy gate structures.
The material of the sidewall 2400 includes a nitride layer.
S5: and forming source regions and drain regions of the device in the active regions at two sides of the pseudo gate structure, wherein a component enhancement process is included in the process of forming the source regions and the drain regions of the device, and the component enhancement process forms a germanium-silicon layer (SiGe) in the source region or the drain region of the p-type field effect transistor.
S6: as shown in fig. 2a, a photoresist 3100 is formed, the photoresist 3100 being between 15nm and 25nm above the dummy gate structure in the dense pattern region (density) 1300 and between 90nm and 110nm above the substrate in the open region 1100.
More specifically, the top height of the photoresist decreases sequentially from the dense pattern area (density) 1300, the isolated pattern area (ISO) 1200 to the open area 1100.
That is, the present invention employs a method of reducing the thickness of photoresist relative to the prior art. The photoresist 310 is raised above the dummy gate structure 110nm in the dense pattern region (density) 130 and 160nm above the substrate in the open region 110 as shown in prior art fig. 1 a. Therefore, the thickness of the photoresist formed in the present invention S6 is greatly reduced relative to the prior art.
More specifically, in one embodiment, the photoresist 3100 is 20nm above the dummy gate structure in the dense pattern region (density) 1300 and 100nm above the semiconductor substrate in the open region 1100.
S7: as shown in fig. 2b, a first Etch Back (EB) of the Photoresist (PR), EB1, is performed to open the photoresist on all polysilicon gates.
Because the thickness of the photoresist formed in S6 is thinner, the strength of the etching back process of the first photoresist of the present application can be correspondingly reduced compared with the strength of the etching back process of the first photoresist of the prior art, for example, by reducing the etching time or power of the etching back process of the first photoresist.
Because the photoresist is thinned, the dry etching program strength of removing the photoresist on the top layer of the polysilicon gate by the EB1 can be correspondingly reduced, so that less photoresist can be consumed in the ISO region EB1, and the defect window of the subsequent EB2 can be increased.
In the prior art shown in fig. 1c, the first photoresist etch back EB1 etches away 145nm of photoresist. As shown in fig. 2b of the present application, the etching back EB1 of the first photoresist etches away the photoresist of 45nm to 65nm, more specifically, the etching back EB1 of the first photoresist etches away the photoresist of 55 nm.
S8: as shown in fig. 2c, an Etch Back (EB) of the second Photoresist (PR), EB2, is performed to remove the second oxide layer 2320 of the hard mask layer.
S9: and removing the polysilicon gate, and forming a metal gate in the removed region of the polysilicon gate.
In an embodiment of the present invention, S61 may further be included between S6 and S7: and opening the photoresist on the large polysilicon gate through a photoetching process.
As described above, the present inventors have reversely thought that the conventional manner of the prior art, which uses the ISO region loading effect, adopts increasing the thickness of the photoresist, but the method has a lower thickening ratio to the ISO region, and then reversely thought that the present application adopts decreasing the thickness of the photoresist, so that the decreasing rate of the photoresist in the ISO region is correspondingly slower to achieve the effect of decreasing the difference of the thicknesses of the photoresist in different regions; and because the photoresist is thinned, the dry etching program strength of removing the photoresist on the top layer of the polysilicon gate by the EB1 can be correspondingly reduced, so that less photoresist can be consumed in the ISO region EB1, the defect window of the subsequent EB2 can be increased, the problem of insufficient OX residual and SIGE FILM DAMAGE process windows in the dry etching process can be solved, and the problem of defects after the dry etching process of the HK28 photoresist back etching (PREB) process can be solved.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the invention.
Claims (9)
1. A method of manufacturing a gate electrode, comprising:
S1: providing a semiconductor substrate, forming a gate dielectric layer and a polysilicon gate on the surface of the semiconductor substrate in sequence, forming a field oxide layer in the semiconductor substrate, isolating an active region by the field oxide layer, wherein the open region, the isolated pattern region and the dense pattern region are respectively positioned in different active regions;
s2: forming a hard mask layer on the surface of the polysilicon gate, wherein the hard mask layer is formed by laminating a first nitride layer and a second oxide layer;
s3: performing photoetching to form a plurality of pseudo gate structures, wherein each pseudo gate structure is formed by stacking the etched gate dielectric layer, the polysilicon gate and the hard mask layer;
S4: forming side walls on the side surfaces of the pseudo gate structures;
s5: forming a source region and a drain region of the device in the active regions at two sides of the pseudo gate structure, wherein a component enhancement process is included in the process of forming the source region and the drain region of the device, and the component enhancement process forms a germanium-silicon layer in the source region or the drain region of the p-type field effect transistor;
S6: forming photoresist, wherein the photoresist is 15-25 nm higher than the pseudo gate structure in the dense pattern area, and is 90-110 nm higher than the substrate in the open area; sequentially reducing the heights of the top parts of the photoresist from the dense pattern area and the isolated pattern area to the open area;
s7: etching back the photoresist for the first time, and opening the photoresist on all polysilicon gates;
s8: etching back the photoresist for the second time to remove the second oxide layer of the hard mask layer; and
S9: and removing the polysilicon gate, and forming a metal gate in the removed region of the polysilicon gate.
2. The method of fabricating a gate electrode according to claim 1, wherein the photoresist is higher than the dummy gate structure by 20nm in the densely patterned region and higher than the semiconductor substrate by 100nm in the empty region in S6.
3. The method of manufacturing a gate electrode according to claim 1, wherein the first photoresist in S7
The photoresist is etched from 45nm to 65 nm.
4. A method of fabricating a gate electrode according to claim 3, wherein the first photoresist etch back etches away 55nm of photoresist.
5. The method of manufacturing a gate electrode according to claim 1, further comprising S61 between S6 and S7: and opening the photoresist on the large polysilicon gate through a photoetching process.
6. The method of manufacturing a gate electrode according to claim 1, wherein the semiconductor substrate is a silicon substrate.
7. The method of claim 1, wherein the gate dielectric layer comprises a high dielectric constant layer.
8. The method of claim 1, wherein the field oxide layer is shallow trench field oxide.
9. The method of claim 8, wherein the shallow trench field oxide is formed using a shallow trench isolation process.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011561763.5A CN112701034B (en) | 2020-12-25 | 2020-12-25 | Method for manufacturing grid electrode |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011561763.5A CN112701034B (en) | 2020-12-25 | 2020-12-25 | Method for manufacturing grid electrode |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN112701034A CN112701034A (en) | 2021-04-23 |
| CN112701034B true CN112701034B (en) | 2024-04-26 |
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