CN112687700A - Three-dimensional memory and preparation method thereof - Google Patents
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- 238000002360 preparation method Methods 0.000 title abstract description 5
- 239000010410 layer Substances 0.000 claims abstract description 369
- 238000000034 method Methods 0.000 claims abstract description 105
- 239000000758 substrate Substances 0.000 claims abstract description 85
- 239000012535 impurity Substances 0.000 claims abstract description 53
- 239000002346 layers by function Substances 0.000 claims abstract description 19
- 230000004888 barrier function Effects 0.000 claims description 98
- 230000005641 tunneling Effects 0.000 claims description 40
- 238000004519 manufacturing process Methods 0.000 claims description 22
- 230000000903 blocking effect Effects 0.000 claims description 18
- 238000000151 deposition Methods 0.000 claims description 17
- 239000002019 doping agent Substances 0.000 claims description 15
- 230000008021 deposition Effects 0.000 claims description 14
- 230000002829 reductive effect Effects 0.000 claims description 14
- 239000000126 substance Substances 0.000 claims description 14
- 238000005530 etching Methods 0.000 claims description 13
- 239000011241 protective layer Substances 0.000 claims description 13
- 238000001039 wet etching Methods 0.000 claims description 12
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 10
- 239000012808 vapor phase Substances 0.000 claims description 9
- 230000007423 decrease Effects 0.000 claims description 5
- 239000007788 liquid Substances 0.000 claims description 5
- 238000009826 distribution Methods 0.000 claims description 4
- 238000003860 storage Methods 0.000 abstract description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 24
- 229920005591 polysilicon Polymers 0.000 description 22
- 238000005229 chemical vapour deposition Methods 0.000 description 9
- 239000000463 material Substances 0.000 description 9
- 238000005137 deposition process Methods 0.000 description 7
- 229910021417 amorphous silicon Inorganic materials 0.000 description 6
- 239000004065 semiconductor Substances 0.000 description 5
- 238000000231 atomic layer deposition Methods 0.000 description 4
- 230000000149 penetrating effect Effects 0.000 description 4
- 238000005240 physical vapour deposition Methods 0.000 description 4
- 230000001681 protective effect Effects 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 150000001875 compounds Chemical class 0.000 description 3
- 239000003989 dielectric material Substances 0.000 description 3
- 150000004767 nitrides Chemical class 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 239000005922 Phosphane Substances 0.000 description 2
- XYFCBTPGUUZFHI-UHFFFAOYSA-N Phosphine Chemical compound P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 238000005429 filling process Methods 0.000 description 2
- 230000014509 gene expression Effects 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 238000004943 liquid phase epitaxy Methods 0.000 description 2
- 229910000064 phosphane Inorganic materials 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 238000000427 thin-film deposition Methods 0.000 description 2
- 238000000927 vapour-phase epitaxy Methods 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- ZOCHARZZJNPSEU-UHFFFAOYSA-N diboron Chemical compound B#B ZOCHARZZJNPSEU-UHFFFAOYSA-N 0.000 description 1
- 239000012467 final product Substances 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 230000005484 gravity Effects 0.000 description 1
- 230000002401 inhibitory effect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000000670 limiting effect Effects 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000001451 molecular beam epitaxy Methods 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
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Abstract
The application provides a three-dimensional memory and a preparation method thereof. The method for preparing the three-dimensional memory comprises the following steps: forming a stacked structure on a substrate, and forming a channel hole in the stacked structure; forming a functional layer and a channel layer in the channel hole in sequence; and doping impurities in the channel layer such that a doping concentration of the impurities gradually increases in the channel layer from a bottom portion near the substrate to a top portion opposite to the bottom portion. According to the preparation method, the consistency of the programming/erasing speed of the storage unit of the three-dimensional memory can be improved, the three-dimensional storage unit has narrower threshold voltage, and the performance of the three-dimensional memory can be effectively improved.
Description
Technical Field
The present disclosure relates to the field of semiconductor design and manufacturing, and more particularly, to a structure of a three-dimensional memory and a method for fabricating the same.
Background
In the existing three-dimensional memory manufacturing method, taking a three-dimensional NAND memory as an example, the following steps are generally adopted for manufacturing a functional layer and a channel layer as shown in fig. 7 to 11:
as shown in fig. 7, a functional layer of a channel structure, specifically, a channel hole 3 penetrating to the substrate 1 may be formed in the stacked structure 2, the channel hole 3 forms a groove having a certain depth in the substrate 1, and an epitaxial layer 4 is formed in the groove. A laminated structure of a first oxide layer/a nitride layer/a second oxide layer/a primary amorphous silicon deposition layer ONOP can be formed on the surface of the epitaxial layer 4, which is far away from the substrate 1, and the inner side wall of the channel hole 3 through methods such as deposition, wherein the amorphous silicon deposition layer can be used as a protective sacrificial layer 6, the ONO laminated structure forms a functional layer 5, and the functional layer 5 sequentially comprises a blocking layer, a charge trapping layer and a tunneling layer from the inner side wall of the channel hole 3 to the radial direction of the axis of the functional layer.
As shown in fig. 8, the SONO is deep-hole etched in the channel hole 3 at its bottom (the portion near the substrate 1), thereby destroying the protective sacrificial layer 6 and the functional layer 5 at the bottom of the channel hole 3 to expose the epitaxial layer 4. During this process, some of the amorphous silicon in the protective sacrificial layer 6 may be etched away in order to protect the functional layer 5.
As shown in fig. 9, another etching process (e.g., a wet etching process) is performed to remove the remaining portion of the protective sacrificial layer 6.
As shown in fig. 10, a polysilicon channel layer is grown to connect the epitaxial layer 4. Specifically, the polysilicon channel layer 7 may be formed directly on the surface of the tunneling layer using, for example, a deposition process; it is also possible to form the amorphous silicon layer in the channel hole 3 first and then form the polysilicon channel layer 7 in a subsequent process step by, for example, crystallizing the amorphous silicon layer.
As shown in fig. 11, the trench filling layer 8 is filled in the remaining space of the trench hole 3.
Due to the limitation of the dual-stack or multi-stack manufacturing process, the Critical Dimension (CD) of the upper and lower channels of the conventional three-dimensional memory is not uniform (the critical dimension of the upper channel is larger than that of the lower channel), and as the number of stacked memory cells increases, the thickness of each layer in the ONOP (oxide-nitride-oxide-polysilicon) structure of the functional layer and the channel layer formed on the inner sidewall of the channel hole at the upper portion (far from the substrate) of the channel hole and the thickness of each layer at the lower portion (near the substrate) of the channel hole tend to have a certain difference. These process problems will seriously affect the uniformity of the program/erase speed of the memory cells in the finally formed three-dimensional memory, and make the threshold voltage range (Vt) of the memory cells too wide, resulting in unstable performance of the three-dimensional memory.
Disclosure of Invention
The present application provides a three-dimensional memory and a method of fabricating the same that can at least partially solve the above-mentioned problems in the prior art.
One aspect of the present application provides a method of fabricating a three-dimensional memory, the method including: forming a laminated structure on a substrate, and forming a channel hole in the laminated structure; forming a functional layer and a channel layer in the channel hole in sequence; and doping impurities in the channel layer such that a doping concentration of the impurities gradually increases in the channel layer from a bottom portion near the substrate to a top portion opposite to the bottom portion.
In one embodiment, gradually increasing the doping concentration of the impurity in the channel layer from a bottom portion near the substrate to a top portion opposite to the bottom portion includes: the doping concentration of the impurity is formed 10 between the bottom and the top15To 1018cm-3Doping concentration gradient of (2).
In one embodiment, the method further comprises: forming an epitaxial layer on the bottom surface of the channel hole close to the substrate; and the step of forming a functional layer in the trench hole includes: forming a barrier layer on an upper surface of the epitaxial layer remote from the substrate and an inner sidewall of the channel hole, the barrier layer including a bottom portion proximate to the substrate and a top portion opposite the bottom portion, and processing the barrier layer such that a thickness of the barrier layer gradually decreases from the bottom portion thereof to the top portion thereof.
In one embodiment, treating the barrier layer to taper the thickness of the barrier layer from the bottom thereof to the top thereof comprises: and thinning the barrier layer by adopting a wet etching process so that the thickness of the barrier layer is gradually reduced from the bottom to the top of the barrier layer.
In one embodiment, the thinning the barrier layer using a wet etching process includes: and thinning the barrier layer by using etching liquid containing hydrofluoric acid.
In one embodiment, the functional layer further includes a charge trap layer and a tunneling layer sequentially disposed on a surface of the blocking layer, wherein forming the channel layer on a surface of the tunneling layer includes: forming a protective layer on the surface of the tunneling layer; removing portions of the protective layer, the tunneling layer, the charge trapping layer, and the blocking layer at the bottom surface of the channel hole, respectively, to expose the epitaxial layer; removing the residual protective layer to expose the surface of the tunneling layer, and forming a groove on the upper surface of the epitaxial layer; and forming the channel layer on the surface of the tunneling layer and the surface of the groove.
In one embodiment, doping the channel layer with impurities includes: and doping impurities in the channel layer by adopting a chemical vapor phase doping process.
In one embodiment, doping impurities in the channel layer using a chemical vapor phase doping process includes: adjusting the distribution and doping content of the impurities in different portions of the channel layer by controlling at least one of a process time, a temperature, a deposition pressure, a dopant concentration, and a dopant flow rate in the chemical vapor doping process.
In one embodiment, doping impurities in the channel layer using a chemical vapor phase doping process includes: the dopant concentration of the impurity is gradually increased in the channel layer from a bottom portion near the substrate to a top portion opposite to the bottom portion by controlling at least one of the deposition pressure and the dopant concentration in the chemical vapor phase doping process.
In one embodiment, the doping the impurity into the multi-channel layer further comprises: and thinning the channel layer.
Another aspect of the present application provides a three-dimensional memory, including: a substrate; a stacked structure disposed on the substrate, the stacked structure including gate layers and insulating layers alternately stacked; and a channel structure penetrating through the laminated structure, wherein a blocking layer, a charge trapping layer, a tunneling layer and a polysilicon channel layer are arranged in the channel structure, and the channel layer has impurities with doping concentration gradually increasing from the bottom close to the substrate to the top opposite to the bottom.
In one embodiment, the thickness of the barrier layer gradually decreases from its bottom near the substrate to its top opposite the bottom.
In one embodiment, the impurity is in the channelThe doping concentration gradient of the bottom and the top of the layer has a value in the range of 1015To 1018cm-3。
Yet another aspect of the present application provides a method of fabricating a three-dimensional memory, the method including: forming a stacked structure on a substrate, forming a channel hole in the stacked structure; forming an epitaxial layer on the bottom surface of the channel hole close to the substrate; forming a barrier layer on an upper surface of the epitaxial layer away from the substrate and an inner sidewall of the channel hole, the barrier layer including a bottom portion near the substrate and a top portion opposite to the bottom portion thereof; treating said barrier layer to taper the thickness of said barrier layer from said bottom portion thereof to said top portion thereof; and sequentially depositing a charge trapping layer, a tunneling layer and a channel layer on the surface of the barrier layer.
In one embodiment, treating the barrier layer to taper the thickness of the barrier layer from the bottom thereof to the top thereof comprises: and thinning the barrier layer by adopting a wet etching process so that the thickness of the barrier layer is gradually reduced from the bottom to the top of the barrier layer.
In one embodiment, the thinning the barrier layer using a wet etching process includes: and thinning the barrier layer by using etching liquid containing hydrofluoric acid.
In one embodiment, forming a channel layer on a surface of the tunneling layer includes: forming a protective layer on the surface of the tunneling layer; removing portions of the protective layer, the tunneling layer, the charge trapping layer, and the blocking layer at the bottom surface of the channel hole, respectively, to expose the epitaxial layer; removing the residual protective layer to expose the surface of the tunneling layer, and forming a groove on the upper surface of the epitaxial layer; and forming the channel layer on the surface of the tunneling layer and the surface of the groove.
Another aspect of the present application provides a three-dimensional memory, including: a substrate; a stacked structure disposed on the substrate, the stacked structure including gate layers and insulating layers alternately stacked; and a channel structure penetrating through the laminated structure, wherein a blocking layer, a charge trapping layer, a tunneling layer and a channel layer are sequentially arranged in the channel structure, and the thickness of the blocking layer is gradually reduced from the bottom of the blocking layer close to the substrate to the top opposite to the bottom.
According to the method for manufacturing the three-dimensional memory and the three-dimensional memory of the embodiments, by controlling the impurity doping concentration in the polysilicon channel layer and cooperating with forming the barrier layer in the three-dimensional memory, the thickness of which gradually increases along the direction from the opening (far from the substrate) to the bottom (close to the substrate) of the channel hole, the programming/erasing speed of the three-dimensional memory can be improved as a whole, the memory cell of the three-dimensional memory has a narrower threshold voltage range, and the performance of the three-dimensional memory is improved.
Drawings
Other features, objects, and advantages of the present application will become more apparent upon reading of the following detailed description of non-limiting embodiments thereof, with reference to the accompanying drawings. Wherein:
FIG. 1 is a flow chart of a method of fabricating a three-dimensional memory according to one embodiment of the present application;
fig. 2-6 are process schematic diagrams of a method of making according to an embodiment of the present application; and
fig. 7 to 11 are schematic process diagrams of a conventional method for manufacturing a three-dimensional memory.
Detailed Description
For a better understanding of the present application, various aspects of the present application will be described in more detail with reference to the accompanying drawings. It should be understood that the detailed description is merely illustrative of exemplary embodiments of the present application and does not limit the scope of the present application in any way. Like reference numerals refer to like elements throughout the specification. The expression "and/or" includes any and all combinations of one or more of the associated listed items.
It should be noted that in the present description, the expressions first, second, third, etc. are used only to distinguish one feature from another, and do not indicate any limitation on the features, and do not particularly indicate any precedence order. Thus, a first side discussed in this application may also be referred to as a second side, and a first window may also be referred to as a second window, or vice versa, without departing from the teachings of this application.
In the drawings, the thickness, size and shape of the components have been slightly adjusted for convenience of explanation. The figures are purely diagrammatic and not drawn to scale. As used herein, the terms "approximately", "about" and the like are used as table-approximating terms and not as table-degree terms, and are intended to account for inherent deviations in measured or calculated values that would be recognized by one of ordinary skill in the art. Further, in this document, when it is described that one portion is located "on" another portion, it means located above or below the other portion, and does not absolutely mean located above with reference to the direction of gravity.
It will be further understood that terms such as "comprising," "including," "having," "including," and/or "containing," when used in this specification, are open-ended and not closed-ended, and specify the presence of stated features, elements, and/or components, but do not preclude the presence or addition of one or more other features, elements, components, and/or groups thereof. Furthermore, when a statement such as "at least one of" appears after a list of listed features, it modifies that entire list of features rather than just individual elements in the list. Furthermore, when describing embodiments of the present application, the use of "may" mean "one or more embodiments of the present application. Also, the term "exemplary" is intended to refer to an example or illustration.
Unless otherwise defined, all terms (including engineering and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict. In addition, unless explicitly defined or contradicted by context, the specific steps included in the methods described herein are not necessarily limited to the order described, but can be performed in any order or in parallel. The present application will be described in detail below with reference to the embodiments with reference to the attached drawings.
Further, in this application, when "connected" or "coupled" is used, it may mean either direct contact or indirect contact between the respective components, unless there is an explicit other limitation or can be inferred from the context.
Fig. 1 is a flowchart of a method 1000 for fabricating a three-dimensional memory according to a first embodiment of the present application. As shown in fig. 1, the present application provides a method 1000 for manufacturing a three-dimensional memory, including:
s1, forming a stacked structure on the substrate, and forming a channel hole in the stacked structure.
S2, forming a functional layer and a channel layer in the channel hole in sequence.
And S3, doping impurities in the channel layer such that the doping concentration of the impurities gradually increases in the polysilicon channel layer from a bottom portion near the substrate to a top portion opposite to the bottom portion.
The specific processes of the steps of the above-described manufacturing method 1000 will be described in detail with reference to fig. 2 to 6.
Fig. 2 is a schematic cross-sectional view of a structure formed after an epitaxial layer is formed in a trench hole according to a fabrication method of an embodiment of the present application.
The step S1 of forming a stacked structure on the substrate, and forming a channel hole in the stacked structure, may for example include: preparing a substrate 100; forming a stacked structure 200 on a substrate 100; and forming a channel hole 300 in the stacked structure 200, the channel hole 300 penetrating the stacked structure 200 in a stacked thickness direction and extending into the substrate 100.
The substrate 100 may be a semiconductor substrate, and the material thereof may be selected from single crystal silicon (Si), single crystal germanium (Ge), or silicon germanium (GeSi), silicon carbide (SiC); silicon-on-insulator (SOI), germanium-on-insulator (GOI) may also be selected; alternatively, other materials may be selected, such as group III-V compounds such as gallium arsenide.
The stacked structure 200 is used to form a memory cell string therein in a direction perpendicular to the substrate 100. As shown in fig. 2, in one embodiment of the present application, the stacked structure 200 may be formed on one side of the substrate 100 by one or more thin film deposition processes, which may include, but are not limited to, CVD, PVD, ALD, or any combination thereof, which is not limited in this application. The stacked structure 200 may include a plurality of stacked layers alternately stacked by insulating layers 210 and sacrificial layers 220, wherein the sacrificial layers 220 are to be replaced with gate layers in a subsequent step. The sacrificial layer 220 may be a nitride layer, such as silicon nitride. The insulating layer 210 may be an oxide layer, for example, silicon oxide.
Further, the stacked structure 200 may further include a plurality of sub-stacked structures, that is, the stacked structure 200 may be formed by a Single sub-stacked (Single) structure (as shown in fig. 2) or by a plurality of sub-stacked (Multiple) structures stacked in sequence. The greater the number of sacrificial layers or gate layers in the stacked structure 200, the more memory cells included in the formed memory cell string, and the higher the integration of the device.
Referring again to fig. 2, the channel hole 300 is a via hole that penetrates the stacked structure 200 and extends into the substrate 100. The channel hole 300 may be formed using, for example, an etching process, such that the channel hole 300 penetrates through the stacked-layer structure 200 and extends into the substrate 100. In other embodiments, the etching process may be stopped before the trench hole 300 reaches the substrate 100, and a subsequent punching process may be performed to further extend the trench hole 300 into the substrate 100.
In one embodiment of the present application, the method 1000 of fabricating a three-dimensional memory further includes forming an epitaxial layer 310 on a bottom surface of the channel hole 300 near the substrate 100, the epitaxial layer 310 may be formed by a Selective Epitaxial Growth (SEG) process, such as Vapor Phase Epitaxy (VPE), Liquid Phase Epitaxy (LPE), molecular beam epitaxy (MPE), or any combination thereof. Epitaxial layer 310 may be at least one of epitaxial silicon, silicon germanium, a III-V compound material, a II-VI compound material, an organic semiconductor material, and other suitable semiconductor materials.
Fig. 2 only illustrates the arrangement process of the channel hole 300 by taking the stack structure 200 including a single sub-stack structure as an example, and it will be understood by those skilled in the art that the stack structure 200 may also be formed by sequentially stacking a plurality of sub-stack structures each provided with a channel hole.
Fig. 3 is a schematic cross-sectional view of a structure formed after forming a barrier layer in a trench hole according to a fabrication method of an embodiment of the present application. Fig. 4 is a schematic cross-sectional view of a structure formed after thinning a barrier layer in a trench hole according to a fabrication method of an embodiment of the present application.
As shown in fig. 3 and 4, in one embodiment of the present application, the method 1000 of fabricating a three-dimensional memory further includes: a barrier layer 330 is formed on the upper surface 311 of the epitaxial layer 310 remote from the substrate 100 and the inner sidewalls of the channel hole 300, and the barrier layer 330 is thinned. Barrier layer 330 has a bottom 331 near substrate 100 and a top 332 remote from the substrate, and thinning barrier layer 330 includes tapering the thickness of barrier layer 330 from its bottom 331 to its top 332 (as shown in fig. 4).
Specifically, barrier layer 330 can be deposited on upper surface 311 of epitaxial layer 310 and the inner sidewalls of channel hole 300 using, for example, one or more thin film deposition processes (e.g., ALD, CVD, PVD, or combinations thereof). The blocking layer 330 may be used to block the flow of electron charges (electrons or holes) stored in the charge trapping layer 340 (shown in fig. 5) toward the stack 200. In some embodiments, it may be made of silicon oxide (SiO)2) Barrier layer 330 is prepared. In some embodiments, the dielectric material may also be made of a high dielectric constant dielectric material (e.g., alumina Al)2O3) Barrier layer 330 is prepared. It will be understood by those skilled in the art that the materials for the barrier layer, the methods of preparation and the parameters of the specific implementation may be varied to achieve the results and advantages described in this specification without departing from the claimed subject matter.
Further, the barrier layer 330 may be thinned by, for example, a wet etching process such that the thickness of the barrier layer 330 tapers from its bottom 331 to its top 332. Specifically, as the number of layers of the memory cells stacked in the three-dimensional memory increases, the barrier layer 330 at the top opening of the channel hole 300 is etched first during the wet etching operation, and the barrier layer 330 at the bottom of the channel hole 300 is etched after a certain time. Therefore, the wet etching process etches more of the barrier layer 330 at the top opening of the channel hole 300, and then gradually reduces the etching amount along the direction from the opening of the channel hole 300 to the bottom thereof, so that the thickness of the barrier layer 330 becomes gradually larger toward the substrate.
The Critical Dimensions (CD) of the upper and lower channel holes in the conventional three-dimensional memory are usually not uniform, and in general, the critical dimension of the upper channel hole is larger than that of the lower channel hole, which makes the effective electric field intensity of the upper structure of the memory cell in the three-dimensional memory smaller than that of the lower structure thereof at the same threshold voltage during the program/erase process, and as the number of stacked memory cells increases, the thickness of each layer in the ONOP (oxide-nitride-oxide-polysilicon) structure of the functional layer and the channel layer formed on the inner sidewall of the channel hole at the upper part (far from the substrate) of the channel hole and the thickness at the lower part (near the substrate) of the channel hole tend to have a certain difference, and finally these process problems will result in the non-uniform program/erase speed of the memory cell in the three-dimensional memory, and the threshold voltage range (Vt) of the memory cell is excessively wide, resulting in unstable performance of the three-dimensional memory. In one embodiment of the present application, a ratio of a thickness of the barrier layer 330 at a lower portion (close to the substrate) of the channel hole 300 to a thickness thereof at an upper portion (far from the substrate) of the channel hole 300 may be set as a thickness ratio of the barrier layer 330, and the thickness ratio of the barrier layer 330 formed on the upper surface 311 of the epitaxial layer 310 and the inner sidewalls of the channel hole 300 by the above deposition process may be between 90% and 95%. By thinning the barrier layer 330 such that the thickness of the barrier layer 330 tapers from its bottom 331 to its top 332, the final thickness ratio of the barrier layer 330 can be between 100% and 110%.
In the programming/erasing process of the three-dimensional memory, the programming/erasing speed of the three-dimensional memory is generally related to the thickness of each layer in an ONOP (oxide-nitride-oxide-polysilicon) structure in a channel hole, wherein the programming/erasing speed of the three-dimensional memory is slower when the thickness of each layer is larger, and the programming/erasing speed of the three-dimensional memory is faster when the thickness of each layer is smaller. In addition, the critical dimension of the upper channel hole is larger than that of the lower channel hole under normal conditions. Therefore, when the thickness of the barrier layer is gradually reduced from the bottom to the top of the barrier layer through the process of thinning the barrier layer, the thickness of the barrier layer of the upper structure of the memory cell in the three-dimensional memory is reduced, and the programming/erasing speed of the upper structure (the opening close to the channel hole) can be improved; on the contrary, the thickness of the barrier layer of the lower structure of the memory cell in the dimension memory is relatively thicker, so that the programming/erasing speed of the lower structure (the opening close to the channel hole) can be reduced, the performance of the upper structure of the three-dimensional memory is consistent with that of the lower structure, the programming/erasing speed of the three-dimensional memory is integrally improved, and the memory cell has a narrower threshold voltage range on the basis, and the performance stability of the three-dimensional memory is improved.
In one embodiment of the present application, a barrier layer 330 having a uniform thickness may be formed on the upper surface 311 of the epitaxial layer 310 and the inner sidewalls of the channel hole 300 by the above-described deposition process. The barrier layer 330 may then be thinned by, for example, a wet etch process such that the thickness of the barrier layer 330 tapers from its bottom 331 to its top 332. Specifically, more of the barrier layer 330 may be etched at the top opening of the channel hole 300, and then the etching amount may be gradually reduced along the direction from the opening of the channel hole 300 to the bottom thereof, so that the thickness of the barrier layer 330 becomes gradually greater toward the substrate (as shown in fig. 4).
In another embodiment of the present application, the barrier layer 330 having a non-uniform thickness may be formed on the upper surface 311 of the epitaxial layer 310 and the inner sidewalls of the channel hole 300 by the above-described deposition process. For example, barrier layer 330 has a thickness at its top 332 that is greater than its bottom 331 (as shown in FIG. 3). The barrier layer 330 may then be thinned by, for example, a wet etch process such that the thickness of the barrier layer 330 tapers from its bottom 331 to its top 332. Specifically, more etching may be performed when the barrier layer 330 is located at the top opening of the channel hole 300, and then, the etching amount is gradually reduced along the direction from the opening of the channel hole 300 to the bottom thereof, so that the thickness of the barrier layer 330 is gradually increased toward the substrate (as shown in fig. 4).
Further, when barrier layer 330 formed on top surface 311 of epitaxial layer 310 and the inner sidewalls of channel hole 300 by the deposition process described above has a top portion 332 with a thickness less than that of a bottom portion 331 thereof but still does not meet the requirements for electrical uniformity in the finally formed three-dimensional memory, barrier layer 330 may also be thinned by, for example, a wet etching process such that the thickness of barrier layer 330 is further tapered from bottom portion 331 thereof to top portion 332 thereof. Specifically, the barrier layer 330 may be etched a small amount at the top opening (far from the substrate) of the channel hole 300, and then, the etching amount is gradually decreased continuously along the direction from the opening of the channel hole 300 to the bottom (near the substrate) thereof, so that the thickness of the barrier layer 330 becomes further gradually larger toward the substrate (as shown in fig. 4).
Further, according to some embodiments of the present application, an etching liquid including hydrofluoric acid may also be used to perform the wet etching process.
According to the method, the barrier layer with the thickness gradually increasing along the direction from the opening to the bottom of the channel hole is formed in the channel hole, so that the programming/erasing speed of a lower structure (close to the bottom of the channel hole) of a storage string in the three-dimensional memory can be reduced, and the programming/erasing speed of an upper structure (close to the opening of the channel hole) is improved, so that the performance of the upper structure is consistent with that of the lower structure, the programming/erasing speed of the three-dimensional memory is integrally improved, a storage unit has a narrow threshold voltage range on the basis, and the performance stability of the three-dimensional memory is improved.
Fig. 5 is a schematic cross-sectional view of a structure formed after forming a functional layer in a trench hole according to a fabrication method of an embodiment of the present application.
As shown in fig. 5, in one embodiment of the present application, a method 1000 of fabricating a three-dimensional memory further includes: forming a charge trapping layer 340 on the surface of the thinned barrier layer 330; and forming a tunneling layer 350 on the surface of the charge trapping layer 340.
The charge trapping layer 340 is used to store electron charges. The charge storage or removal of the charge trapping layer 340 can affect the conduction or switching state of the semiconductor channel structure in the three-dimensional memory. In some embodiments, a nitride layer may be deposited on the surface of the thinned barrier layer 330 by, for example, a deposition process to form the charge trapping layer 340. In some embodiments, the charge trapping layer 340 may also be comprised of a multilayer structure. This is not a limitation of the present application.
The tunneling layer 350 can be used for data retention by inhibiting the trapping or de-trapping of electron charges. In some embodiments, the tunneling layer 350 may be formed by an oxide layer, such as by a deposition process. In some embodiments, the tunneling layer 350 may also be comprised of a multilayer structure. This is not a limitation of the present application.
Fig. 6 is a schematic cross-sectional view of a structure formed after forming a channel layer 320 in a channel hole according to a fabrication method of an embodiment of the present application.
As shown in fig. 6, in one embodiment of the present application, a method 1000 of fabricating a three-dimensional memory further includes forming a channel layer 320 in the channel hole 300. The channel layer 320 is to provide a channel layer for a selection transistor and a memory transistor of a memory cell string in a three-dimensional memory. According to one embodiment of the present application, the material of the channel layer 320 includes an impurity-doped channel material, such as P-type doped polysilicon. The impurity in the channel layer 320 is doped in the same type as the selection transistor and the memory transistor, for example, for the P-type selection transistor and the memory transistor, the channel layer 320 may be P-type doped polysilicon. Similarly, for N-type select and memory transistors, the channel layer 320 may be N-type doped polysilicon.
In one embodiment of the present application, the channel Layer 320 may be deposited directly in the channel hole 300 by using a method such as Atomic Layer Deposition (ALD), Physical Vapor Deposition (PVD), or Chemical Vapor Deposition (CVD).
In another embodiment of the present application, an amorphous silicon layer (not shown) may be formed in the channel hole 300 by, for example, a Chemical Vapor Deposition (CVD) method, and then crystallized to form the channel layer 320 in a subsequent process step.
In one embodiment of the present application, the method 1000 of fabricating a three-dimensional memory further comprises: the channel layer 320 is doped with impurities, and the doping concentration of the impurities gradually increases in the channel layer 320 from a bottom portion 321 near the substrate to a top portion 322 opposite the bottom portion 321. The doping concentration of the impurity forms a value range of 10 between the bottom 321 and the top 32215To 1018cm-3Doping concentration gradient of (2).
In one embodiment of the present application, impurity doping may be performed in the channel layer 320 using a process such as chemical vapor phase doping. Chemical vapor doping refers to a process of doping an impurity element into a thin film through a vapor phase while depositing a Chemical Vapor Deposition (CVD) thin film. In other words, while the channel layer 320 is formed by using the chemical vapor deposition process, N-type doping or P-type doping may be formed in the channel layer 320 by introducing an appropriate amount of dopant (impurity source), such as phosphane (PH3) or borane (B2H 6).
Further, it is also possible to effectively adjust different distributions of impurities in the channel layer 320 and different doping contents by controlling the process time, temperature, and deposition pressure in the chemical vapor doping process, and the type, concentration, and flow rate of the dopant. In addition, by controlling at least one of a deposition pressure and a dopant concentration in the chemical vapor doping process, a dopant concentration of an impurity may be gradually increased in the channel layer 320 from a bottom portion 321 near the substrate 100 to a top portion 322 opposite to the bottom portion 321. For example, the dopant may not easily and effectively enter the bottom 321 of the channel layer 320 by controlling the deposition pressure (increasing the deposition pressure) within a specific value range to achieve a doping concentration of the impurity at the bottom 321 that is less than the doping concentration at the top 322. In addition, the impurities may also form a doping concentration gradient between the bottom portion 321 and the top portion 322 by singly controlling the deposition pressure of the dopants. For example, controlling the dopant concentration gradient of the impurity between the bottom 321 and the top 322 of the channel layer 320 to 10 may be achieved by controlling the deposition pressure within a specific fixed value range15To 1018cm-3Between the ranges. It will be understood by those skilled in the art thatThe method of doping impurities or the parameters of the specific implementation process can be changed to obtain the results and advantages described in the specification without departing from the technical scheme claimed in the application.
In one embodiment of the present application, the method 1000 of fabricating a three-dimensional memory further comprises: the channel layer 320 is thinned before the step of doping the channel layer 320 with impurities.
In the process of forming the polysilicon channel 320, due to the existing process limitation, the thicknesses of the channel layer 320 at different positions of the channel hole 300 may have a certain difference, and when the similarity of the thicknesses of the polysilicon channel 320 is too low (the thickness difference is too large), the electrical properties of the finally formed three-dimensional memory, such as channel current, electric field intensity distribution, and threshold voltage, may be seriously affected, resulting in the overall performance degradation of the three-dimensional memory device.
In one embodiment of the present application, the channel layer 320 may be etched back (Etch back) to reduce the thickness difference of the parts of the channel layer 320 while being thinned. Further, the number of lattice damage or deposition defects in the channel layer 320 may also be reduced while the channel layer 320 is thinned by the etch-back process.
The polysilicon channel layer of the three-dimensional memory is a key channel for carrier movement, and the current conduction capability of the polysilicon channel layer has important influence on the erasing and writing performance and the reading performance of the three-dimensional memory. Due to the limitation of the dual-stack or multi-stack manufacturing process, the Critical Dimension (CD) of the upper and lower channels in the conventional three-dimensional memory is generally not uniform (the critical dimension of the upper channel is larger than that of the lower channel), and as the number of stacked memory cells increases, the thickness of each layer in the ONOP (oxide-nitride-oxide-polysilicon) structure of the functional layer and the channel layer formed on the inner sidewall of the channel hole is often different between the thickness of the upper portion (far from the substrate) of the channel hole and the thickness of the lower portion (near the substrate) of the channel hole. These process problems will seriously affect the uniformity of the program/erase speed of the memory cells in the finally formed three-dimensional memory, and make the threshold voltage (Vt) range of the memory cells too wide, resulting in unstable performance of the three-dimensional memory.
The method can effectively balance the problems of inconsistent critical dimension and uneven thickness of each layer in the ONOP caused by the process problems by doping impurities in the polysilicon channel layer and enabling the doping concentration of the impurities to be increased in the polysilicon channel layer from the bottom close to the substrate to the top opposite to the bottom by a certain doping concentration gradient. The problems in the prior art can be at least partially improved by controlling the impurity doping concentration in the polysilicon channel layer, the consistency of programming/erasing of the memory cell is improved, and the threshold voltage range of the memory cell is reduced.
Further, referring again to fig. 6, the step of forming the polysilicon channel layer in the channel hole may include: the channel layer 320 is formed on the surface of the tunneling layer 350. Specifically, a protection layer (not shown) may be formed on the surface of the tunneling layer 350; then, removing the portions of the protective layer, the blocking layer 330, the charge trapping layer 340 and the tunneling layer 350 at the bottom surface of the channel hole 300, respectively, to expose the epitaxial layer 310; removing the remaining protection layer to expose the surface of the tunneling layer 350 and forming a groove on the upper surface 311 of the epitaxial layer 310; and forming a channel layer 320 on the surface of the tunneling layer 350 and the surface of the recess.
In the channel hole 300, the channel layer 320, the tunneling layer 350, the charge trapping layer 340, and the blocking layer 330 are arranged in order radially from the axis of the channel hole 300 toward the inner sidewall. Alternatively, the remaining space of the trench hole 300 may also partially or completely fill a trench fill layer (not shown), which may include a dielectric material, such as silicon oxide or the like. Further, in the filling process, a plurality of insulating gaps can be formed in the channel filling layer by controlling the channel filling process so as to relieve the structural stress.
In addition, in a subsequent process of the method for manufacturing the three-dimensional memory, the method further comprises a step of removing the sacrificial layer in the alternating stacked insulating layers and sacrificial layers to replace the metal layer for forming the gate electrode layer. The embodiments and process flows in this application only show the stacked layer structure before gate layer formation. The final product of the three-dimensional memory should be provided with a stacked structure of alternating insulating and gate layers.
Referring again to fig. 6, another aspect of the present application also provides a three-dimensional memory structure. Specifically, the three-dimensional memory structure includes a substrate 100, a stack structure 200, and a channel structure. The stacked structure 200 is disposed on the substrate 100, and includes an insulating layer 210 and a gate layer (not shown) which are alternately stacked. The channel structure penetrates the stacked-layer structure 200, and includes a blocking layer 330, a charge storage layer 340, a tunneling layer 350, and a channel layer 320.
In one embodiment, barrier layer 330 tapers in thickness from its bottom 331 to its top 332.
In one embodiment, the channel layer 320 has impurities with a doping concentration gradually increasing from a bottom 321 thereof to a top 322 thereof.
In one embodiment, the dopant concentration gradient of the impurity at the bottom 321 and the top 322 ranges from 1015To 1018cm-3。
In one embodiment, the three-dimensional memory further includes an epitaxial layer 310 disposed in the substrate 100 in connection with the channel layer 320.
In one embodiment, the stack 200 includes at least one sub-stack.
Since the contents and structures referred to in the above description of the method 1000 may be fully or partially applicable to the three-dimensional memory described herein, the contents related or similar thereto will not be described in detail.
According to the three-dimensional memory structure provided by the application, the polycrystalline silicon channel layer is doped with impurities, and the doping concentration of the impurities is increased in the polycrystalline silicon channel layer from the bottom close to the substrate to the top opposite to the bottom by a fixed doping concentration gradient, so that the problems of inconsistent key sizes and uneven thicknesses of all layers in the ONOP due to process problems can be effectively balanced. By controlling the impurity doping concentration in the polysilicon channel layer and forming the barrier layer with the thickness gradually increasing along the direction from the opening (far away from the substrate) to the bottom (close to the substrate) of the channel hole in the three-dimensional memory, the programming/erasing speed of the three-dimensional memory can be improved on the whole, and on the basis, the memory cell has a narrower threshold voltage range, and the performance stability of the three-dimensional memory is improved.
The above description is only an embodiment of the present application and an illustration of the technical principles applied. It will be appreciated by a person skilled in the art that the scope of protection covered by the present application is not limited to the embodiments with a specific combination of the features described above, but also covers other embodiments with any combination of the features described above or their equivalents without departing from the technical idea. For example, the above features may be replaced with (but not limited to) features having similar functions disclosed in the present application.
Claims (18)
1. A method of fabricating a three-dimensional memory, the method comprising:
forming a laminated structure on a substrate, and forming a channel hole in the laminated structure;
forming a functional layer and a channel layer in the channel hole in sequence; and
doping impurities in the channel layer such that a doping concentration of the impurities gradually increases in the channel layer from a bottom portion near the substrate to a top portion opposite to the bottom portion.
2. The method of claim 1, wherein gradually increasing a doping concentration of the impurity in the channel layer from a bottom portion near the substrate to a top portion opposite the bottom portion comprises:
the doping concentration of the impurity is formed 10 between the bottom and the top15cm-3To 1018cm-3Doping concentration gradient of (2).
3. The method of claim 1, further comprising: forming an epitaxial layer on the bottom surface of the channel hole close to the substrate; and
the step of forming a functional layer in the trench hole includes:
forming a barrier layer on an upper surface of the epitaxial layer remote from the substrate and an inner sidewall of the channel hole, the barrier layer including a bottom portion proximate to the substrate and a top portion opposite the bottom portion, an
Treating said barrier layer such that the thickness of said barrier layer gradually decreases from said bottom portion thereof to said top portion thereof.
4. The method of claim 3, wherein treating the barrier layer to gradually decrease in thickness from the bottom thereof to the top thereof comprises:
and thinning the barrier layer by adopting a wet etching process so that the thickness of the barrier layer is gradually reduced from the bottom to the top of the barrier layer.
5. The method of claim 4, wherein thinning the barrier layer using a wet etch process comprises:
and thinning the barrier layer by using etching liquid containing hydrofluoric acid.
6. The method of claim 3, the functional layer further comprising a charge-trapping layer and a tunneling layer disposed sequentially on a surface of the barrier layer, wherein forming a channel layer within the channel hole comprises:
forming a protective layer on the surface of the tunneling layer;
removing portions of the protective layer, the tunneling layer, the charge trapping layer, and the blocking layer at the bottom surface of the channel hole, respectively, to expose the epitaxial layer;
removing the residual protective layer to expose the surface of the tunneling layer, and forming a groove on the upper surface of the epitaxial layer; and
and forming the channel layer on the surface of the tunneling layer and the surface of the groove.
7. The method of any of claims 1-6, wherein doping the channel layer with impurities comprises:
and doping impurities in the channel layer by adopting a chemical vapor phase doping process.
8. The method of claim 7, wherein doping the channel layer with impurities using a chemical vapor phase doping process comprises:
adjusting the distribution and doping content of the impurities in different portions of the channel layer by controlling at least one of a process time, a temperature, a deposition pressure, a dopant concentration, and a dopant flow rate in the chemical vapor doping process.
9. The method of claim 7, wherein doping the channel layer with impurities using a chemical vapor phase doping process comprises:
the doping concentration of the impurity is gradually increased in the channel layer from a bottom portion near the substrate to a top portion opposite to the bottom portion by controlling at least one of a deposition pressure and a dopant concentration in the chemical vapor doping process.
10. The method of claim 1, further comprising, prior to the step of doping the channel layer with impurities:
and thinning the channel layer.
11. A three-dimensional memory, comprising:
a substrate;
a stacked structure disposed on the substrate, the stacked structure including gate layers and insulating layers alternately stacked; and
a channel structure extending through the stack structure,
the channel structure is sequentially provided with a blocking layer, a charge capturing layer, a tunneling layer and a channel layer, and the channel layer is provided with impurities of which the doping concentration is gradually increased from the bottom close to the substrate to the top opposite to the bottom.
12. The memory of claim 11, wherein the thickness of the barrier layer gradually decreases from a bottom portion thereof adjacent to the substrate to a top portion thereof opposite to the bottom portion.
13. The memory of claim 11 or 12, wherein a doping concentration gradient of the impurity at the bottom and the top of the channel layer has a value in a range of 1015To 1018cm-3。
14. A method of fabricating a three-dimensional memory, the method comprising:
forming a laminated structure on a substrate, and forming a channel hole in the laminated structure;
forming an epitaxial layer on the bottom surface of the channel hole close to the substrate;
forming a barrier layer on an upper surface of the epitaxial layer far away from the substrate and an inner side wall of the channel hole, wherein the barrier layer comprises a bottom part close to the substrate and a top part opposite to the bottom part;
treating said barrier layer to taper the thickness of said barrier layer from said bottom portion thereof to said top portion thereof; and
and sequentially depositing a charge trapping layer, a tunneling layer and a channel layer on the surface of the barrier layer.
15. The method of claim 14, wherein treating the barrier layer to taper the thickness of the barrier layer from the bottom thereof to the top thereof comprises:
and thinning the barrier layer by adopting a wet etching process so that the thickness of the barrier layer is gradually reduced from the bottom to the top of the barrier layer.
16. The method of claim 15, wherein thinning the barrier layer using a wet etch process comprises:
and thinning the barrier layer by using etching liquid containing hydrofluoric acid.
17. The method of claim 14, wherein forming the channel layer on the surface of the tunneling layer comprises:
forming a protective layer on the surface of the tunneling layer;
removing portions of the protective layer, the tunneling layer, the charge trapping layer, and the blocking layer at the bottom surface of the channel hole, respectively, to expose the epitaxial layer;
removing the residual protective layer to expose the surface of the tunneling layer, and forming a groove on the upper surface of the epitaxial layer; and
and forming the channel layer on the surface of the tunneling layer and the surface of the groove.
18. A three-dimensional memory, comprising:
a substrate;
a stacked structure disposed on the substrate, the stacked structure including gate layers and insulating layers alternately stacked; and
a channel structure extending through the stack structure,
the channel structure is sequentially provided with a blocking layer, a charge capturing layer, a tunneling layer and a channel layer, and the thickness of the blocking layer is gradually reduced from the bottom of the blocking layer close to the substrate to the top opposite to the bottom.
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