CN112687617B - Preparation method of insulator needle and insulator needle - Google Patents
Preparation method of insulator needle and insulator needle Download PDFInfo
- Publication number
- CN112687617B CN112687617B CN202011551776.4A CN202011551776A CN112687617B CN 112687617 B CN112687617 B CN 112687617B CN 202011551776 A CN202011551776 A CN 202011551776A CN 112687617 B CN112687617 B CN 112687617B
- Authority
- CN
- China
- Prior art keywords
- substrate
- lower substrate
- upper substrate
- electroplating
- holes
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Abstract
The invention is suitable for the technical field of semiconductors, and provides a preparation method of an insulator needle and the insulator needle, wherein the method comprises the following steps: respectively preparing a plurality of through holes arranged in an array mode on an upper substrate and a lower substrate, and sputtering seed layers on the surfaces of the upper substrate and the lower substrate and in the through holes; electroplating metal with a preset height in the through holes and the upper and lower surfaces of the upper substrate and the lower substrate of the sputtering seed layer in a layer-by-layer electroplating mode; etching off the seed layers of the non-electroplated areas on the electroplated upper substrate and the electroplated lower substrate; preparing protective layers on the metal surfaces of the etched upper substrate and the etched lower substrate; and correspondingly bonding the first enclosing wall of the upper substrate for preparing the protective layer and the third enclosing wall of the lower substrate for preparing the protective layer to form the air coaxial insulator needle. The integrated design of the pin pitch of the insulator pin can improve the requirement of high-density interconnection of the metal tube shell, and the mounting surface is formed on the surface of the insulator pin, so that the radio frequency end is grounded and isolated nearby, the loss is small, and the high-frequency characteristic is good.
Description
Technical Field
The invention belongs to the technical field of semiconductors, and particularly relates to an insulator needle and a preparation method thereof.
Background
The glass insulator needle is a conventional part for airtight interconnection of metal tube shells, the radio frequency interface is usually in a single-needle structure with a single lead supported by glass frit, the distance from a central conductor to an outer ring support metal ring in the structure is 0.8mm, and the difficulty of continuous compression is high. And when many needles were arranged, the interval of needle, the distribution position adjustment degree of needle were big. With the increase of the integration level of radio frequency circuits and the increase of operating frequencies, the conventional insulator pin is more and more difficult to meet the requirements of high-density and low-loss through-wall interconnection of miniaturized metal tube shells.
Disclosure of Invention
In view of this, the embodiment of the invention provides an insulator needle and a preparation method thereof, and aims to solve the problem that the insulator needle in the prior art cannot meet the requirements of high-density and low-loss through-wall interconnection of a miniaturized metal tube shell.
In order to achieve the above object, a first aspect of embodiments of the present invention provides a method for manufacturing an insulator pin, including:
respectively preparing a plurality of through holes arranged in an array mode on an upper substrate and a lower substrate, and sputtering seed layers on the surfaces of the upper substrate and the lower substrate and in the through holes;
electroplating metals with preset heights on the upper surface and the lower surface in through holes of an upper substrate and a lower substrate of a sputtering seed layer in a layer-by-layer electroplating mode to ensure that electroplating metals are filled in the through holes of the upper substrate and the lower substrate, the preset through holes on the upper surface of the upper substrate are mutually connected by adopting the electroplating metals, the outer ring through holes on the lower surface of the upper substrate are connected by adopting the electroplating metals to form a first enclosing wall, the inner through holes are independent, the outer ring through holes on the upper surface of the lower substrate are connected by adopting the electroplating metals to form a second enclosing wall, the inner through holes are independent, the outer ring through holes on the lower surface of the lower substrate are connected by adopting the electroplating metals to form a third enclosing wall, and the through holes on the two inner sides are connected with the third enclosing wall by adopting the electroplating metals;
etching off the seed layers of the non-electroplated areas on the electroplated upper substrate and the electroplated lower substrate;
preparing protective layers on the metal surfaces of the etched upper substrate and the etched lower substrate;
and correspondingly bonding the first enclosing wall of the upper substrate for preparing the protective layer and the third enclosing wall of the lower substrate for preparing the protective layer to form the air coaxial insulator needle.
As another embodiment of the present application, the preparing a plurality of via holes arranged in an array manner on an upper substrate and a lower substrate respectively includes:
preparing a plurality of through holes arranged in an array mode on the upper substrate and the lower substrate respectively by adopting picosecond cold laser, wherein the ratio of the diameter of each through hole to the thickness of the upper substrate or the lower substrate is 1/4-1/3; the upper substrate and the lower substrate are glass substrates or quartz substrates.
As another embodiment of the present application, the cross section of the via hole is circular;
the diameter of the via hole is 70-125 μm.
As another embodiment of the present application, the metal material used for the seed layer is titanium or copper.
As another embodiment of the present application, the electroplating a metal with a preset height on the upper and lower surfaces in the via holes of the upper and lower substrates of the sputtered seed layer by a layer-by-layer electroplating method includes:
respectively spin-coating photoresist on the upper substrate and the lower substrate of the sputtering seed layer, carrying out photoetching development, then carrying out electroplating, filling electroplating metal in the through holes, and respectively enabling the electroplating metal on the upper surface and the lower surface of the upper substrate and the lower substrate to reach a first preset height;
grinding and polishing the electroplated metal surfaces of the upper substrate and the lower substrate;
respectively spin-coating photoresist on the upper substrate and the lower substrate which are subjected to polishing treatment again, carrying out photoetching development, and then electroplating again to enable the electroplated metal on the upper surface and the lower surface of the upper substrate and the lower substrate to reach a second preset height;
and electroplating the upper substrate and the lower substrate according to a second electroplating mode to enable the electroplated metal on the upper surface and the lower surface of the upper substrate and the lower substrate to reach the final preset height.
As another embodiment herein, the electroplated metal is copper;
the first preset height is 50 to 100 μm;
the second preset height is 150 to 300 μm;
the final preset height is 1mm to 2 mm.
As another embodiment of the present application, the etching of the seed layer in the non-electroplated areas on the electroplated upper substrate and the electroplated lower substrate includes:
and (3) stripping the seed layers in the non-electroplated areas on the upper substrate and the lower substrate after the plating by adopting the picosecond laser with the 3D space adjustable to leak the base materials of the upper substrate and the lower substrate.
As another embodiment of the present application, the material of the protective layer is gold.
As another embodiment of the present application, the metal used for bonding is gold.
A second aspect of an embodiment of the present invention provides an insulator needle, including an insulator needle manufactured by the method for manufacturing an insulator needle according to any one of the embodiments.
Compared with the prior art, the embodiment of the invention has the following beneficial effects: compared with the prior art, the invention prepares the via hole on the substrate, then electroplates metal in the via hole to form three conductors of G (ground) S (signal) G (ground) which are arranged in parallel to form the coplanar waveguide, and the integrated design of the pin pitch of the insulator pin can improve the requirement of high-density interconnection of metal tube shells, and the mounting surfaces are formed on the upper surface of the upper substrate and the lower surface of the lower substrate, thereby being convenient for mounting the blocking capacitor, and the radio frequency end is grounded and isolated nearby, the loss is small, and the high-frequency characteristic is good.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required to be used in the embodiments or the prior art description will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings may be obtained according to these drawings without inventive labor.
Fig. 1 is a schematic flow chart of an implementation of a method for manufacturing an insulator pin according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of via fabrication on a single substrate provided by an embodiment of the present invention;
FIG. 3 is a schematic view of the surfaces of the upper and lower substrates and the sputtered seed layer within the via provided by an embodiment of the present invention;
FIG. 4 is an exemplary diagram of a substrate after a first electroplating according to an embodiment of the present invention;
FIG. 5 is a schematic top view of an upper substrate provided in accordance with an embodiment of the present invention;
FIG. 6 is a schematic view of the bottom surface of the upper substrate provided by the embodiment of the present invention;
FIG. 7 is a schematic top view of a lower substrate according to an embodiment of the present invention;
FIG. 8 is a schematic view of the bottom surface of the lower substrate according to the embodiment of the present invention;
FIG. 9 is a schematic view of the substrate after a second electroplating according to an embodiment of the present invention;
FIG. 10 is a schematic representation after etching provided by embodiments of the present invention;
FIG. 11 is a schematic view of a bonded air coaxial insulator pin provided by an embodiment of the present invention;
fig. 12 is a schematic view of an embodiment of the present invention providing for the soldering of an insulator pin to a metal can;
fig. 13 is a schematic diagram of an insulator needle surface gluing element and bonding interconnection provided by an embodiment of the invention.
Detailed Description
In the following description, for purposes of explanation and not limitation, specific details are set forth such as particular system structures, techniques, etc. in order to provide a thorough understanding of the embodiments of the invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present invention with unnecessary detail.
In order to explain the technical means of the present invention, the following description will be given by way of specific examples.
Fig. 1 is a schematic flow chart illustrating an implementation of a method for manufacturing an insulator pin according to an embodiment of the present invention, which is described in detail below.
Optionally, the upper substrate and the lower substrate are glass substrates or quartz substrates, and are used as supporting materials for the end faces of the insulator pins.
As shown in fig. 2, a schematic diagram of preparing a via hole 2 on a single substrate 1 may be an upper substrate or a lower substrate, and when designing a via hole on a substrate, in order to reduce radio frequency loss and improve isolation, a ratio of a diameter of the via hole to a thickness of the upper substrate or the lower substrate may be 1/4 to 1/3.
Optionally, the shape of the cross section of the via hole is not limited, and may be circular or rectangular in this embodiment. For example, the cross-section of the via is circular to facilitate bonding interconnection at the side or end faces. The via may have a diameter of 70 μm to 125 μm. Alternatively, the diameter of the via may be 125 μm. The signal pins of the GSG interconnected with the via holes are rectangular in cross section, the coupling characteristics can be improved by the rectangles, the side length of each rectangle ranges from 0.12 mm to 0.25mm to 0.4mm, and the distance between the rectangles ranges from 0.05mm to 2 mm.
Optionally, in this step, picosecond cold laser may be used to prepare a plurality of via holes arranged in an array manner on the upper substrate and the lower substrate, respectively, and picosecond cold laser is used to open the holes, so that the hole walls are smooth and the verticality is higher, and the aperture difference between the upper and lower surfaces of the via holes is less than 5%, thereby reducing the transmission loss.
The needle spacing of the insulator needle adopts an integrated design, and different port impedances are matched with different needle spacings, so that the performance of the insulator needle can be improved.
As shown in fig. 3, the surface of the upper substrate and the lower substrate and the schematic diagram of the seed layer 3 sputtered in the via hole, the seed layer 3 is a thin film metal seed layer, and the adopted metal material is titanium or copper.
And step 102, electroplating metal with a preset height in the through holes and the upper and lower surfaces of the upper substrate and the lower substrate of the sputtering seed layer in a layer-by-layer electroplating mode.
The through holes of the upper substrate and the lower substrate are filled with electroplated metal, the through holes are preset on the upper surface of the upper substrate and are connected with each other through the electroplated metal, the outer ring through holes on the lower surface of the upper substrate are connected into a first enclosing wall through the electroplated metal, the inner through holes are independent, the outer ring through holes formed on the upper surface of the lower substrate are connected into a second enclosing wall through the electroplated metal, the inner through holes are independent, the outer ring through holes formed on the lower surface of the lower substrate are connected into a third enclosing wall through the electroplated metal, and the through holes on the two sides of the inner part are connected with the third enclosing wall through the electroplated metal.
Optionally, in the step, a layer-by-layer electroplating mode is adopted to electroplate metal with a preset height, namely, the extending part of the outer part of the insulator needle is prepared on the substrate by adopting a layer-by-layer electroplating method, the height can be accurately controlled through electroplating and CMP, the design requirements can be matched, and the use is flexible. The end face graph is defined by a photoresist material, rectangles with different sizes are selected according to requirements and strength, the side wall is smooth after electroplating and can be directly bonded, and interconnection is facilitated.
Optionally, this step may include:
respectively spin-coating photoresist on the upper substrate and the lower substrate of the sputtering seed layer, carrying out photoetching development, then carrying out electroplating, filling electroplating metal in the through holes, and respectively enabling the electroplating metal on the upper surface and the lower surface of the upper substrate and the lower substrate to reach a first preset height; as shown in fig. 4, each via hole is filled with the plated metal, and the plated metal on the upper and lower surfaces can reach 50 μm to 100 μm.
As shown in fig. 5, the right side of the plurality of vias arranged in an array are connected by plating, and the left side of the vias at the center of the left side of the plurality of vias are connected by plating to form the pattern shown in fig. 5. Fig. 6 shows a schematic view of the lower surface of the upper substrate, in which the via holes on the outer ring of the lower surface are connected by electroplating metal to form a first wall, and the via holes inside the first wall are independent. Note that the photolithography development pattern may be represented by the patterns shown in fig. 5 and 6, in which the black body portion is a bare portion and the other portions are photoresist portions.
Fig. 8 is a schematic top view of a lower substrate, wherein an outer via is formed on the top surface and connected to form a second wall by electroplating metal, and an inner via is independent. Fig. 7 is a schematic view of the lower surface of the lower substrate, wherein outer ring via holes formed on the lower surface of the lower substrate are connected to form a third enclosing wall by using electroplated metal, and via holes on two inner sides are connected to the third enclosing wall by using electroplated metal. Note that, the lithography development pattern may also be represented by the patterns shown in fig. 7 and 8, in which the black body portion is a bare portion and the other portions are photoresist portions.
As shown in fig. 6-8, the inner via holes are a G (ground) hole, an S (signal) hole and a G (ground) hole in sequence from left to right, and three formed conductors are arranged in parallel to form a coplanar waveguide. Two ground conductors at the interconnection end are interconnected with the third surrounding wall at the outer side, an installation surface is formed on the outer surface of the glass substrate, and a blocking capacitor, such as a capacitor welded in the figure 13, is mounted on the outer surface of the glass substrate, so that the radio frequency end can be conveniently grounded and isolated nearby, the length of an interconnection bonding wire is shortened, the loss is reduced, and the high-frequency characteristic is good.
And grinding and polishing the electroplated metal surfaces of the upper substrate and the lower substrate for subsequent operation.
Respectively spin-coating photoresist on the upper substrate and the lower substrate which are subjected to polishing treatment again, carrying out photoetching development, and then electroplating again to enable the electroplated metal on the upper surface and the lower surface of the upper substrate and the lower substrate to reach a second preset height; as shown in fig. 9, the signal hole portion in the middle of the front surface is heightened by electroplating, and the metal post on the back surface is heightened by electroplating. Alternatively, the second predetermined height may be 150 μm to 300 μm.
And electroplating the upper substrate and the lower substrate according to a second electroplating mode to enable the electroplated metal on the upper surface and the lower surface of the upper substrate and the lower substrate to reach the final preset height. All the photoresist is then removed. Optionally, the final preset height may be set according to the assembly or use requirements, for example, the final preset height may be 1mm to 2 mm. The cavity height can realize micron-scale matching design as required.
By adopting the electroplating mode, the metal can be electroplated each time, so that the whole height deviation is +/-2 mu m, and the pattern precision is +/-1 mu m, thereby reducing the total height deviation and improving the pattern precision.
Alternatively, the plating metal may be copper.
And 103, etching the seed layer of the electroplated upper substrate and the electroplated lower substrate in the non-electroplated area.
Optionally, the seed layers in the non-electroplated areas on the upper substrate and the lower substrate after picosecond laser stripping electroplating can be modulated by adopting the laser with the 3D space, and the base materials of the upper substrate and the lower substrate are leaked. The picosecond laser which can be modulated in the 3D space is adopted for etching in the step, and the etching position can be accurately positioned, so that the etching precision is improved, and other metals on the side wall are prevented from being etched.
Fig. 10 is a schematic diagram after etching.
And 104, preparing protective layers on the metal surfaces of the etched upper substrate and the etched lower substrate.
Optionally, the surfaces of the upper and lower substrates after etching are chemically plated with gold to improve the environmental tolerance of several shifts.
And 105, correspondingly bonding the first wall of the upper substrate for preparing the protective layer and the third wall of the lower substrate for preparing the protective layer to form the air coaxial insulator needle.
Optionally, the two substrates with symmetric enclosing walls are welded in a gold-gold bonding manner to form a cavity. Alternatively, the air cavity formed may be a micro vacuum cavity.
Fig. 11 is a schematic diagram of the bonded air coaxial insulator pin, in which the dotted line includes an upper substrate and a lower substrate, the upper substrate is a cross-sectional view along the straight line in fig. 5, and the lower substrate is a cross-sectional view along the straight line in fig. 8. The metal column is divided into a plurality of mutually independent areas to form a plurality of independent sub-cavities which are mutually and completely isolated by electromagnetic shielding. The metal column is used as an inner conductor and is respectively used as a direct current needle or a radio frequency needle. A plurality of radio frequency needles and direct current needles which are mutually isolated are manufactured in an insulator needle, so that the integration level can be improved.
Optionally, after this step, the method may further include: adopting a grinding wheel or laser scribing, and dividing into independent units; welding the split insulator pins to the corresponding positions of the tube shells as shown in figure 12; gluing elements on the surface, bonding and interconnecting, welding the capacitor to the surface of the insulator pin as shown in fig. 13, connecting the capacitor to the radio frequency pin corresponding to the intermediate signal via hole through a bonding wire, and connecting the capacitor with the shell chip.
It can be seen from fig. 11 to 13 that the pin pitch of the insulator pin is integrally designed, and different pitches of the pins match different port impedances, so that the performance of the insulator pin can be improved, two output end faces can be isolated from the ground, and the high-frequency matching characteristic is good.
The insulator pin is connected with the tube shell by welding, and the surface of the metal conductor through hole of the internal glass substrate is sealed by thick copper (more than 10 mu m) in an electroplating way. The substrate serving as the pin surface carrier of the insulator is damaged due to the structure of the via hole, and the metal filled in the via hole is thermally mismatched with the substrate, so that dense connection cannot be realized, and therefore, when the surface conductor layer is prepared, the thickness of the electroplated copper layer is larger than 10 mu m, so that airtightness is realized; and when the insulator needle is assembled, the outer metal ring and the tube shell are connected through the solder in a hard mode by adopting the solder, and finally air tightness is achieved.
According to the preparation method of the insulator needle, the semiconductor chip process is adopted, the high-strength glass substrate or quartz substrate is adopted as a carrier, the high-precision processing technologies such as laser drilling, sputtering, electroplating, photoetching, chemical mechanical polishing, gold-gold bonding and the like are comprehensively applied, and the two substrates are bonded to form the air coaxial insulator needle by combining the electric, thermal and stress simulation design, so that the matching degree with the design is high. In the embodiment, three conductors of G (ground) S (signal) G (ground) are arranged in parallel to form a coplanar waveguide, so that the traditional coaxial structure is replaced to improve the radio frequency characteristic. Meanwhile, high-density interconnection of single insulator needle integrated multi-channel radio frequency and direct current transmission is achieved, and the metal tube shell has great advantages on millimeter wave and THz miniaturized metal tube shells. The output end face of the insulator pin is integrally designed, and the side face and the end face can be bonded, so that the interconnection is convenient. The insulator needle is interconnected with the tube shell through welding, and the surface of the insulator needle is thick copper at the through hole of the metal conductor of the glass substrate, so that electroplating airtightness is realized.
It should be understood that, the sequence numbers of the steps in the foregoing embodiments do not imply an execution sequence, and the execution sequence of each process should be determined by functions and internal logic of the process, and should not limit the implementation process of the embodiments of the present invention in any way.
In correspondence to the method for manufacturing an insulator needle described in the above embodiment, an insulator needle provided in an embodiment of the present invention includes, as shown in fig. 11, an insulator needle manufactured by the method for manufacturing an insulator needle described in any one of the above embodiments, and has a friendship effect of the method for manufacturing an insulator needle provided in any one of the above embodiments.
The above-mentioned embodiments are only used for illustrating the technical solutions of the present invention, and not for limiting the same; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not depart from the spirit and scope of the embodiments of the present invention, and they should be construed as being included therein.
Claims (10)
1. A method for preparing an insulator pin, comprising:
respectively preparing a plurality of through holes arranged in an array mode on an upper substrate and a lower substrate, and sputtering seed layers on the surfaces of the upper substrate and the lower substrate and in the through holes;
electroplating metals with preset heights on the upper surface and the lower surface in through holes of an upper substrate and a lower substrate of a sputtering seed layer in a layer-by-layer electroplating mode to ensure that electroplating metals are filled in the through holes of the upper substrate and the lower substrate, the preset through holes on the upper surface of the upper substrate are mutually connected by adopting the electroplating metals, the outer ring through holes on the lower surface of the upper substrate are connected by adopting the electroplating metals to form a first enclosing wall, the inner through holes are independent, the outer ring through holes on the upper surface of the lower substrate are connected by adopting the electroplating metals to form a second enclosing wall, the inner through holes are independent, the outer ring through holes on the lower surface of the lower substrate are connected by adopting the electroplating metals to form a third enclosing wall, and the through holes on the two inner sides are connected with the third enclosing wall by adopting the electroplating metals;
etching off the seed layers of the non-electroplated areas on the electroplated upper substrate and the electroplated lower substrate;
preparing protective layers on the metal surfaces of the etched upper substrate and the etched lower substrate;
and correspondingly bonding the first enclosing wall of the upper substrate for preparing the protective layer and the third enclosing wall of the lower substrate for preparing the protective layer to form the air coaxial insulator needle.
2. The method of claim 1, wherein the forming the plurality of vias arranged in an array on the upper substrate and the lower substrate, respectively, comprises:
preparing a plurality of through holes arranged in an array mode on the upper substrate and the lower substrate respectively by adopting picosecond cold laser, wherein the ratio of the diameter of each through hole to the thickness of the upper substrate or the lower substrate is 1/4-1/3; the upper substrate and the lower substrate are glass substrates or quartz substrates.
3. The method of manufacturing an insulator needle according to claim 1,
the cross section of the through hole is circular;
the diameter of the via hole is 70-125 μm.
4. The method for manufacturing an insulator needle according to claim 1, wherein a metal material used for the seed layer is titanium or copper.
5. The method for manufacturing an insulator pin according to any one of claims 1 to 4, wherein the step of electroplating a predetermined height of metal on the upper and lower surfaces in the via holes of the upper and lower substrates of the sputtered seed layer by a layer-by-layer electroplating method comprises:
respectively spin-coating photoresist on the upper substrate and the lower substrate of the sputtering seed layer, carrying out photoetching development, then electroplating, filling electroplating metal in the through holes, and enabling the electroplating metal on the upper surface and the lower surface of the upper substrate and the lower substrate to respectively reach a first preset height;
grinding and polishing the electroplated metal surfaces of the upper substrate and the lower substrate;
respectively spin-coating photoresist on the upper substrate and the lower substrate which are subjected to polishing treatment again, carrying out photoetching development, and then electroplating again to enable the electroplated metal on the upper surface and the lower surface of the upper substrate and the lower substrate to reach a second preset height;
and electroplating the upper substrate and the lower substrate according to a second electroplating mode to enable the electroplated metal on the upper surface and the lower surface of the upper substrate and the lower substrate to reach the final preset height.
6. The method of manufacturing an insulator needle according to claim 5, wherein the plating metal is copper;
the first preset height is 50 to 100 μm;
the second preset height is 150 to 300 μm;
the final preset height is 1mm to 2 mm.
7. The method of claim 1, wherein etching away the seed layer in the non-plated areas on the plated upper and lower substrates comprises:
and stripping the seed layers of the electroplated upper substrate and the electroplated lower substrate in the non-electroplated area by adopting picosecond laser with 3D space modulation, and leaking the base materials of the upper substrate and the lower substrate.
8. The method of manufacturing an insulator needle according to claim 1, wherein a material of the protective layer is gold.
9. The method of manufacturing an insulator needle according to claim 1, wherein the metal used for bonding is gold.
10. An insulator needle comprising the insulator needle produced by the method for producing an insulator needle according to any one of claims 1 to 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011551776.4A CN112687617B (en) | 2020-12-24 | 2020-12-24 | Preparation method of insulator needle and insulator needle |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011551776.4A CN112687617B (en) | 2020-12-24 | 2020-12-24 | Preparation method of insulator needle and insulator needle |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN112687617A CN112687617A (en) | 2021-04-20 |
| CN112687617B true CN112687617B (en) | 2022-07-22 |
Family
ID=75452786
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202011551776.4A Active CN112687617B (en) | 2020-12-24 | 2020-12-24 | Preparation method of insulator needle and insulator needle |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112687617B (en) |
Citations (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6311850A (en) * | 1986-07-03 | 1988-01-19 | Sanki Denshi Kogyo Kk | Method and apparatus for detecting pin hole or the like of insulator |
| US6255218B1 (en) * | 1995-03-30 | 2001-07-03 | Nec Corporation | Semiconductor device and fabrication method thereof |
| JP2006274369A (en) * | 2005-03-29 | 2006-10-12 | Ebara Corp | Method and apparatus for forming substrate wiring, and plating suppressing substance transfer stamp |
| US7583169B1 (en) * | 2007-03-22 | 2009-09-01 | The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration | MEMS switches having non-metallic crossbeams |
| JP2011096752A (en) * | 2009-10-28 | 2011-05-12 | Kyocera Corp | Connection structure between semiconductor device and circuit board |
| CN102132398A (en) * | 2008-03-21 | 2011-07-20 | 哈佛学院院长等 | Self-aligned barrier layers for interconnects |
| CN103824816A (en) * | 2014-02-24 | 2014-05-28 | 中国兵器工业集团第二一四研究所苏州研发中心 | T/R assembly integrated air tightness packaging structure resistant to overload |
| CN105304977A (en) * | 2015-11-13 | 2016-02-03 | 中国电子科技集团公司第五十五研究所 | Millimeter wave ceramic insulator and design method therefor |
| CN205140941U (en) * | 2015-11-10 | 2016-04-06 | 河北中瓷电子科技有限公司 | Ceramic insulator for electronic packaging |
| CN106785435A (en) * | 2017-02-08 | 2017-05-31 | 成都雷电微力科技有限公司 | A kind of T/R module vertical interconnecting structure part |
| CN108370095A (en) * | 2015-08-06 | 2018-08-03 | 薄膜电子有限公司 | Wireless communication device and production and preparation method thereof with integrated ferrite shielding and antenna |
| CN108389847A (en) * | 2018-05-09 | 2018-08-10 | 宁波大学 | A kind of three-dimensional capacitor and preparation method thereof based on coaxial through-silicon via array |
| CN109390648A (en) * | 2018-09-10 | 2019-02-26 | 中国电子科技集团公司第二十九研究所 | A kind of encapsulating structure and method of Multi-channel microwave-light transition components |
| CN110010502A (en) * | 2018-10-10 | 2019-07-12 | 浙江集迈科微电子有限公司 | A kind of system in package technique of radio frequency chip |
| CN110739538A (en) * | 2019-09-28 | 2020-01-31 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | Radio frequency interconnection method of TR (transmitter-receiver) component and antenna array |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105552091A (en) * | 2016-03-09 | 2016-05-04 | 京东方科技集团股份有限公司 | Array substrate, preparing method thereof and display panel |
-
2020
- 2020-12-24 CN CN202011551776.4A patent/CN112687617B/en active Active
Patent Citations (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6311850A (en) * | 1986-07-03 | 1988-01-19 | Sanki Denshi Kogyo Kk | Method and apparatus for detecting pin hole or the like of insulator |
| US6255218B1 (en) * | 1995-03-30 | 2001-07-03 | Nec Corporation | Semiconductor device and fabrication method thereof |
| JP2006274369A (en) * | 2005-03-29 | 2006-10-12 | Ebara Corp | Method and apparatus for forming substrate wiring, and plating suppressing substance transfer stamp |
| US7583169B1 (en) * | 2007-03-22 | 2009-09-01 | The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration | MEMS switches having non-metallic crossbeams |
| CN102132398A (en) * | 2008-03-21 | 2011-07-20 | 哈佛学院院长等 | Self-aligned barrier layers for interconnects |
| JP2011096752A (en) * | 2009-10-28 | 2011-05-12 | Kyocera Corp | Connection structure between semiconductor device and circuit board |
| CN103824816A (en) * | 2014-02-24 | 2014-05-28 | 中国兵器工业集团第二一四研究所苏州研发中心 | T/R assembly integrated air tightness packaging structure resistant to overload |
| CN108370095A (en) * | 2015-08-06 | 2018-08-03 | 薄膜电子有限公司 | Wireless communication device and production and preparation method thereof with integrated ferrite shielding and antenna |
| CN205140941U (en) * | 2015-11-10 | 2016-04-06 | 河北中瓷电子科技有限公司 | Ceramic insulator for electronic packaging |
| CN105304977A (en) * | 2015-11-13 | 2016-02-03 | 中国电子科技集团公司第五十五研究所 | Millimeter wave ceramic insulator and design method therefor |
| CN106785435A (en) * | 2017-02-08 | 2017-05-31 | 成都雷电微力科技有限公司 | A kind of T/R module vertical interconnecting structure part |
| CN108389847A (en) * | 2018-05-09 | 2018-08-10 | 宁波大学 | A kind of three-dimensional capacitor and preparation method thereof based on coaxial through-silicon via array |
| CN109390648A (en) * | 2018-09-10 | 2019-02-26 | 中国电子科技集团公司第二十九研究所 | A kind of encapsulating structure and method of Multi-channel microwave-light transition components |
| CN110010502A (en) * | 2018-10-10 | 2019-07-12 | 浙江集迈科微电子有限公司 | A kind of system in package technique of radio frequency chip |
| CN110739538A (en) * | 2019-09-28 | 2020-01-31 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | Radio frequency interconnection method of TR (transmitter-receiver) component and antenna array |
Also Published As
| Publication number | Publication date |
|---|---|
| CN112687617A (en) | 2021-04-20 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US20190013561A1 (en) | Coaxial Waveguide Microstructures Having an Active Device and Methods of Formation Thereof | |
| US10511077B2 (en) | Method for manufacturing mode converter | |
| JP2009038806A (en) | Small-sized rf and microwave components, and method for manufacturing same | |
| WO2003049514A2 (en) | Miniature rf and microwave components and methods for fabricating such components | |
| US20220408526A1 (en) | Rf circuit and enclosure having a micromachined interior using semiconductor fabrication | |
| CN112687617B (en) | Preparation method of insulator needle and insulator needle | |
| US6667549B2 (en) | Micro circuits with a sculpted ground plane | |
| US9755333B2 (en) | Radio frequency connector receptical | |
| US20220289559A1 (en) | Microelectronics h-frame device | |
| CN111029313A (en) | Airtight packaging device and airtight packaging method | |
| CN210575940U (en) | Novel radio frequency transmission structure | |
| CN114609498A (en) | W-band radio frequency tube shell structure and preparation method | |
| CN111900522B (en) | Silicon-based air-filled micro-coaxial structure and silicon-based air-filled micro-coaxial transmission line | |
| CN111900521B (en) | Silicon-based micro coaxial structure | |
| CN210956641U (en) | Airtight packaging device | |
| CN111883898B (en) | Method for manufacturing micro delay line chip of micro coaxial structure | |
| CN111900520B (en) | Silicon-based micro-coaxial delay line chip | |
| CN111463528B (en) | Microstrip line filter, preparation method thereof and MEMS (micro-electromechanical system) sensor | |
| CN112687638B (en) | Vertical interconnected metal ceramic packaging shell, device and preparation method | |
| CN114583424B (en) | Suspended strip line filter and preparation method thereof | |
| CN110400787B (en) | Silicon-based vertical interconnection structure and preparation method | |
| JP2024510385A (en) | Radio frequency crossing with high isolation in microelectronic H-frame devices | |
| CN116404389A (en) | Micro coaxial broadband coupler applied to microwave assembly | |
| CN116365203A (en) | Silicon-based MEMS rectangular waveguide circulator and preparation method thereof | |
| CN111029312A (en) | Airtight packaging device and airtight packaging method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |