CN112684318A - Bootstrap type half-bridge driver common-mode voltage change rate tolerance testing device and method - Google Patents
Bootstrap type half-bridge driver common-mode voltage change rate tolerance testing device and method Download PDFInfo
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Abstract
The invention provides a bootstrap type half-bridge driver common-mode voltage change rate tolerance testing device, which comprises: a half-bridge driving circuit to be tested; the voltage boosting unit is connected between the power supply and the half-bridge driving circuit, generates an impact current for testing the common-mode voltage conversion rate of the half-bridge driving circuit through the voltage boosting unit, and ensures that the common-mode voltage conversion rate of the half-bridge driving circuit is within a safe tolerance range; the input end of the sampling unit is connected with the boosting unit, the working current of the boosting unit is obtained, the working current is sampled, and the sampling current is generated; and the comparison unit is connected between the sampling unit and the boosting unit, generates a driving signal for driving the boosting unit to work when the comparison unit judges that the sampling current falls within the safe working current range of the boosting unit, and is also used for adjusting the safe working current range of the boosting unit. The invention also provides a bootstrap type half-bridge driver common-mode voltage change rate tolerance test method.
Description
Technical Field
The invention relates to the technical field of electronics, in particular to a bootstrap type half-bridge driver common-mode voltage change rate tolerance testing device and method.
Background
As shown in fig. 1, the bootstrap half-bridge driver IC (Integrated circuit) will operate under the condition of high dv/dt (common mode voltage conversion ratio) because it needs to be connected to the middle point of the bridge arm of the half-bridge, and therefore, the endurance capability of the bootstrap half-bridge driver IC to dv/dt is a very important index. The most common method currently used in the industry to test this endurance is by testing the circuit as shown in figure 1.
The test circuit in fig. 1 includes an inductor L, a diode D1, an NMOS transistor Q1, a Low-voltage Gate Driver (LSGD Low Side Gate Driver), a resistor Rg2, and a half-bridge Driver IC of bootstrap type to be tested (hereinafter referred to as a half-bridge Driver IC). The half-bridge drive IC comprises an HB pin, an HO pin, an HS pin, an LO pin, a GND pin, an HI pin and an LI pin. The HI and LI pins are used to input complementary PWM signals. The HB pin is connected with a first end of the capacitor Cb, the HO pin is connected with a first end of the capacitor Cg1, and the LO pin and the GND pin are connected through a capacitor Cg 2. The power supply PVDD is connected with a first end of an inductor L and a cathode of a diode D1, a second end of the inductor L, an anode of a diode D1, a drain electrode of an NMOS tube Q1, an HS pin, a second end of a capacitor Cb and a second end of a capacitor Cg 1. The input end of the LSGD is used for inputting a driving signal PWM _ GDV of an NMOS tube Q1, the output end of the LSGD is connected with the grid electrode of an NMOS tube Q1 through a resistor Rg2, and the source electrode of the NMOS tube Q1 is grounded.
High dv/dt can be generated at test point 3 by fast switching NFET Q1 (if the off current is large enough), and if HS pin (common mode input) of the half-bridge driver IC is connected to test point 3, the half-bridge driver IC operates at high dv/dt, which may cause level abnormality at the outputs of HO and LO pins of the half-bridge driver IC.
The test circuit shown in fig. 1 also has the following limitations:
limitation 1) the current of the inductor L is not controlled; without the introduction of current detection, the open-loop PWM control will increase the current of the inductor L uncontrollably, and eventually lead to the inductor saturation and the NMOS transistor Q1 being damaged. Therefore, to avoid this situation, the circuit can only operate for a short time, otherwise the NFET Q1 will be damaged by over-current;
limitation 2) the duty cycle of the NMOS transistor Q1 is not well selected: if the duty ratio is too large, the current rises quickly, and the tube is easy to burn; the duty ratio is too small, the current climbing is slow, the off current is small, and dv/dt generated at the test point 3 is insufficient;
and the limit 3) cannot automatically test the dv/dt critical endurance point, and the test circuit can only determine the dv/dt endurance point of the half-bridge drive IC through repeated experiments due to the limits of the limit 1 and the limit 2.
The method for testing the anti-interference capability of an IPM (Intelligent Power Module) Module (which has 6 IGBTs and 3 half-bridge driver ICs integrated therein) mentioned in patent CN106468757A is to generate dv/dt noise by the switch of a high side IGBT (Insulated Gate Bipolar Transistor). Because IPM packages chip and igbt (mosfet) together, its internal parasitic capacitance is large, and driver (driver) inside IPM drives igbt (mosfet), which may generate dv/dt noise enough to interfere with the operation of its internal half-bridge driving IC. However, this approach is not suitable for dv/dt testing of monolithic half-bridge driver ICs, because the parasitic capacitance of the monolithic half-bridge driver IC is relatively small, and therefore a larger dv/dt is required to cause its operation to fail.
The method for testing dv/dt tolerance mentioned in patent CN102109573A is to change dv/dt of the common mode voltage receiving terminal VS pin and GND pin of the chip under test in real time through an additional circuit, which is inconsistent with the application scenario of the actual chip, and therefore the tested result may have deviation.
Disclosure of Invention
The invention aims to provide a bootstrap type half-bridge driver common-mode voltage change rate tolerance test device and a bootstrap type half-bridge driver common-mode voltage change rate tolerance test method.
In order to achieve the above object, the present invention provides a bootstrap half-bridge driver common-mode voltage variation rate tolerance testing apparatus, including: the device comprises a bootstrap type half-bridge driving circuit to be tested, a sampling unit, a comparison unit and a boosting unit;
the bootstrap type half-bridge driving circuit to be tested comprises: the device comprises an HB pin, an HO pin, an HS pin, an LO pin, a GND pin, an HI pin and an LI pin, wherein the GND pin is grounded;
the input end of the boosting unit is connected with a power supply PVDD, and the output end of the boosting unit is connected with the HS pin; generating an impact current for testing the common-mode voltage conversion rate of the half-bridge driving circuit through the boosting unit; obtaining the tolerance range of the common-mode voltage change rate of the half-bridge driving circuit by testing the common-mode voltage change rate of a connection point between the output end of the boosting unit and the HS pin, and ensuring that the common-mode voltage change rate of the half-bridge driving circuit is in the safe tolerance range by the boosting unit;
the input end of the sampling unit Is connected with the boosting unit, the working current Is of the boosting unit Is collected, and the sampling unit Is used for sampling the working current Is to generate a sampling current V _ 1;
the input end of the comparison unit is connected with the output end of the sampling unit, and the output end of the comparison unit is connected with the boosting unit; when the comparison unit judges that V _1 is in the safe working current range of the boosting unit, the comparison unit generates a driving signal PWM _ GDV for driving the boosting unit to work; the comparison unit is also used for adjusting the safe working current range of the boosting unit.
Preferably, the sampling unit comprises an operational amplifier OPA, resistors R1, R2, R3; a first end of the resistor R1 IS connected with the boosting unit to obtain the working current IS, and a second end of the resistor R1 IS connected with the negative electrode of the input end of the operational amplifier OPA and a first end of the resistor R2; the first end of the resistor R3 is grounded, and the second end of the resistor R3 and the first end of the resistor R4 are connected with the positive electrode of the input end of the operational amplifier OPA; the second end of the resistor R2 is connected with the output end of the operational amplifier OPA; the second terminal of the resistor R4 is connected to the Offset voltage V _ Offset.
Preferably, the comparison unit comprises comparators COMP1 AND COMP2, resistors R5, R6, R7, Rd1 AND Rd2, adjustable resistors Rp1 AND Rp2, AND gate AND; the resistor R5 is connected and arranged between the output end of the operational amplifier OPA and the negative pole of the input end of the comparator COMP 1; the first end of the resistor Rd1 is grounded, and the first end of the adjustable resistor Rp1 is connected with a reference voltage V _ Ref; the second end of the resistor Rd1 and the second end of the adjustable resistor Rp1 are connected with the anode of the input end of the comparator COMP 1; the resistor R6 is connected and arranged between the output end of the operational amplifier OPA and the anode of the input end of the comparator COMP 2; the first end of the resistor Rd2 is grounded, the second end of the adjustable resistor Rp2 is connected with a reference voltage V _ Ref, and the second end of the resistor Rd2 and the second end of the adjustable resistor Rp2 are connected with the negative electrode of the input end of the comparator COMP 2; the output ends of the comparators COMP1 and COMP2 are connected with a voltage VCC through a resistor R7; the output ends of the comparators COMP1 AND COMP2 are connected with the first input end of an AND gate AND, AND the second input end of the AND gate AND is connected with a pulse width modulation signal PWM 1; AND the AND gate AND generates the driving signal PWM _ GDV when V _1 is within the safe working current range of the boosting unit.
Preferably, the voltage VCC matches the voltage of the AND gate AND, AND the duty cycle of the modulation signal PWM1 is 50%.
Preferably, the boosting unit includes: the circuit comprises an inductor L, resistors Rg1 and Rg2, a sampling resistor Rs, NMOS tubes Q1 and Q2 and a driving unit LSGD;
the first end of the inductor L is connected with a power supply PVDD, the second end of the inductor L is connected with the grid electrode of the NMOS tube Q1 through a resistor Rg1, and the second end of the inductor L is connected with the source electrode of the NMOS tube Q1, the drain electrode of the NMOS tube Q2 and the HS pin;
the first end of the driving unit LSGD is connected with the output end of the AND gate AND, the second end of the driving unit LSGD is connected with the grid electrode of the NMOS tube Q2 through a resistor Rg2, AND the third end of the driving unit LSGD is grounded; the source electrode of the NMOS tube Q2 is connected with the first end of the sampling resistor Rs and the first end of the resistor R1; the second end of the sampling resistor Rs is grounded; the source current of the NMOS tube Q2 Is the working current Is.
Preferably, the bootstrap half-bridge driver common-mode voltage variation rate tolerance test device is characterized by further comprising an input switch S1, which is connected and disposed between the power supply PVDD and the first end of the inductor L.
Preferably, the bootstrap half-bridge driver common-mode voltage change rate tolerance testing device further includes a load unit; the load unit comprises a bus capacitor C and an adjustable resistor RL; the first end of the bus capacitor C and the first end of the adjustable resistor RL are connected with the drain electrode of the NMOS tube Q1, and the second end of the bus capacitor C and the second end of the adjustable resistor RL are grounded.
Preferably, the half-bridge driving circuit further includes: capacitances Cb, Cg1, Cg 2; the capacitor Cb is connected between the HB pin and the HS pin, the capacitor Cg1 is connected between the HO pin and the HS pin, and the capacitor Cg2 is connected between the LO pin and the GND pin; the HI pin and the LI pin are used to input complementary bandwidth modulation signals PWM.
The invention also provides a method for testing the common-mode voltage change rate tolerance of the bootstrap type half-bridge driver, which is realized by adopting the device for testing the common-mode voltage change rate tolerance of the bootstrap type half-bridge driver, and comprises the following steps:
f1, setting a first measurement point between the HO pin and the capacitor Cg1, setting a second measurement point between the LO pin and the capacitor Cg2, and setting a third measurement point between the source of the NMOS transistor Q1 and the first end of the resistor Rg 1; connecting the first measuring point and the second measuring point through an oscilloscope, and measuring whether the bandwidth modulation signal PWM of the half-bridge driving circuit is in an abnormal state; connecting a third measuring point through an oscilloscope, and measuring the bus impact current output to the HS pin of the half-bridge driving circuit by the boosting unit;
f2, disconnecting the input switch S1, and adjusting the resistors Rp1 and Rp2 to enable the Rp1 and the Rp2 to meet the condition that when the power supply PVDD supplies power to the testing device, the current V1 of the Rp1 is larger than the current V2 of the Rp 2;
f3, closing the input switch S1, and observing the waveform of the bandwidth modulation signal PWM; when the wave form of the bandwidth modulation signal PWM has wave loss, reading out the failure point of the common-mode voltage conversion rate of the half-bridge driving circuit through an oscilloscope, and entering F4; otherwise, F2 is entered;
f4, disconnecting the input switch S1, adjusting Rp1 to increase the current V1 of the Rp1, and adjusting Rp2 to increase or decrease the current V2 of the Rp 2;
f5, closing the input switch S1, observing the oscilloscope, and judging whether the wave form of the bandwidth modulation signal PWM no longer loses waves; if yes, go to F6; if not, go to F4;
and F6, reading the recovery point of the common-mode voltage conversion rate of the half-bridge driving circuit from the oscilloscope.
Preferably, in step F2:
Rp1adjusted resistance value, R, for resistance Rp1p1Adjusted resistance value, R, for resistance Rp1sFor the resistance of the sampling resistor Rs, R1、R2Is the resistance value of the resistors R1 and R2, Rd1Is the resistance of resistor Rd1, Rd2Is the resistance of resistor Rd2, and (R)p1+Rd1)＝(Rp2+Rd2)＝Rp。
Compared with the prior art, the invention has the beneficial effects that:
1) the bootstrap type half-bridge driver common-mode voltage change rate tolerance testing device can effectively test to obtain a common-mode voltage change rate dv/dt failure point and a recovery point, so as to obtain the tolerance capability of a half-bridge driving circuit to be tested on the common-mode voltage change rate;
2) by arranging the sampling unit and the comparison unit, the invention ensures that the boosting unit works in a safe working current range in the measuring process, ensures that the voltage of the HS pin of the half-bridge driving circuit to be measured cannot overshoot, effectively protects the testing device and prevents elements from being damaged;
3) according to the invention, by arranging the load unit, the input power of the testing device to the half-bridge driving circuit to be tested and the boosting module is balanced, and the power tube is prevented from being damaged due to overvoltage or overcurrent;
4) the range of the working current of the boosting unit can be adjusted by adjusting the resistors Rp1 and Rp2 of the comparison unit, and an NMOS tube in a testing device does not need to be replaced in each test.
Drawings
In order to more clearly illustrate the technical solution of the present invention, the drawings used in the description will be briefly introduced, and it is obvious that the drawings in the following description are an embodiment of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts according to the drawings:
FIG. 1 is a schematic diagram of a circuit for testing a common mode voltage variation rate of a half-bridge driver IC in the prior art;
FIG. 2 is a schematic diagram of a bootstrap half-bridge driver common-mode voltage variation rate tolerance testing apparatus according to the present invention;
FIG. 3 is a flowchart of a method for testing common mode voltage variation rate tolerance of a bootstrap half-bridge driver according to the present invention;
FIG. 4 is a schematic diagram of the operation region of the NMOS transistor Q1 according to the embodiment of the present invention;
FIG. 5 is a schematic diagram of determining a dv/dt failure point and a recovery point according to the PWM wave and the HS pin voltage wave collected at the first test point and the third test point in the embodiment of the present invention;
fig. 6 is a schematic diagram of waveforms of PWM and HS pin voltages collected at the first test point and the third test point in the embodiment of the present invention;
fig. 7 is a schematic diagram of the PWM waves collected at the first and second test points and the voltage waveform collected at the third test point according to the embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
As shown in fig. 1, the present invention provides a bootstrap half-bridge driver common-mode voltage variation rate tolerance testing apparatus, including: the device comprises a bootstrap type half-bridge driving circuit to be tested, a sampling unit, a comparison unit, a boosting unit, an input switch S1 and a load unit.
The bootstrap type half-bridge driving circuit to be tested comprises: the device comprises an HB pin, an HO pin, an HS pin, an LO pin, a GND pin, an HI pin and an LI pin, wherein the GND pin is grounded; the half-bridge drive circuit further includes: capacitances Cb, Cg1, Cg 2; the capacitor Cb is connected between the HB pin and the HS pin, the capacitor Cg1 is connected between the HO pin and the HS pin, and the capacitor Cg2 is connected between the LO pin and the GND pin; the HI pin and the LI pin are used to input complementary bandwidth modulation signals PWM. Setting a first measuring point at an HO pin, a second measuring point at an LO pin, and a third measuring point at an HS pin; connecting the first and second measuring points through an oscilloscope, and measuring whether the bandwidth modulation signal PWM of the half-bridge driving circuit is in an abnormal state (wave loss); and connecting the third measuring point through an oscilloscope, and observing the bus impact current (also referred to as the impact current for short) output to the HS pin by the boosting unit through the oscilloscope according to the state measuring result of the PWM waveform to obtain a tolerance failure point and a tolerance recovery point of the half-bridge drive circuit dv/dt.
The input end of the boosting unit is connected with a power supply PVDD, and the output end of the boosting unit is connected with the HS pin. The input switch S1 is provided between the booster cell and the power supply PVDD, and when S1 changes from the open state to the closed state, a transient rush current is generated in the booster cell. And obtaining the dv/dt tolerance range of the half-bridge drive circuit by testing the common-mode voltage change rate dv/dt of a connection point (a third measurement point) between the boosting unit and the HS pin, and ensuring that the dv/dt of the half-bridge drive circuit is in the safe tolerance range by controlling the impact current of the boosting unit.
As shown in fig. 2, the boosting unit includes: the circuit comprises an inductor L, resistors Rg1 and Rg2, a sampling resistor Rs, NMOS tubes Q1 and Q2 and a driving unit LSGD;
an input switch S1, which is connected between the power supply PVDD and the first end of the inductor L; the first end of the inductor L is connected with a power supply PVDD, the second end of the inductor L is connected with the grid electrode of the NMOS tube Q1 through a resistor Rg1, and the second end of the inductor L is connected with the source electrode of the NMOS tube Q1, the drain electrode of the NMOS tube Q2 and the HS pin;
the first end of the driving unit LSGD is connected with the output end of the AND gate AND, the second end of the driving unit LSGD is connected with the grid electrode of the NMOS tube Q2 through a resistor Rg2, AND the third end of the driving unit LSGD is grounded; the source electrode of the NMOS tube Q2 is connected with the first end of the sampling resistor Rs and the first end of the resistor R1; the second end of the sampling resistor Rs is grounded;
the input end of the sampling unit Is connected with the source electrode of an NMOS (N-channel metal oxide semiconductor) tube Q2 of the boosting unit, the source electrode current of the NMOS tube Q2 Is used as the working current Is of the boosting unit, the working current Is sampled through the sampling unit, and the sampling current V _1 Is generated. Of course, in other embodiments, the operation current of the boost unit is not limited to be obtained from the source of the NMOS transistor Q2, which is merely an example of the present invention and should not be taken as a limitation of the present invention.
As shown in fig. 2, the sampling unit includes an operational amplifier OPA, resistors R1, R2, R3; the first end of the resistor R1 IS connected with the source electrode of the NMOS tube Q1 of the boosting unit to obtain the working current IS; the second end of the resistor R1 is connected with the negative electrode of the input end of the operational amplifier OPA and the first end of the resistor R2; the first end of the resistor R3 is grounded, and the second end of the resistor R3 and the first end of the resistor R4 are connected with the positive electrode of the input end of the operational amplifier OPA; the second end of the resistor R2 is connected with the output end of the operational amplifier OPA; the second terminal of the resistor R4 is connected to the Offset voltage V _ Offset. The Offset voltage V _ Offset is a sampling Offset voltage, which is used to eliminate the influence of noise on the GND pin on the sampling signal and convert the negative current signal into a positive voltage signal, and the Offset voltage V _ Offset is generally half of the voltage VCC. The output terminal of the operational amplifier OPA outputs the sampling current V _ 1.
The input end of the comparison unit is connected with the output end of the sampling unit, and the output end of the comparison unit is connected with the boosting unit. The obtained sampling current V _1 is used by the comparison unit for detecting the working state of the boosting unit. When the comparison unit judges that V _1 is in the safe working current range of the boosting unit, the comparison unit generates a high-level driving signal PWM _ GDV for driving a Q1 to work to the grid electrode of an NMOS tube Q1; otherwise, the PWM _ GDV is in a low level, the NMOS tube Q1 stops working, and the boosting unit loses power. The comparison unit is also used for adjusting the safe working current range of the boosting unit, further controlling the size of the impact current and preventing the HS pin from generating overhigh dv/dt.
As shown in fig. 2, the comparing unit includes comparators COMP1 AND COMP2, resistors R5, R6, R7, Rd1 AND Rd2, adjustable resistors Rp1 AND Rp2, AND gate; the resistor R5 is connected and arranged between the output end of the operational amplifier OPA and the negative pole of the input end of the comparator COMP 1; the first end of the resistor Rd1 is grounded, and the first end of the adjustable resistor Rp1 is connected with a reference voltage V _ Ref; the second end of the resistor Rd1 and the second end of the adjustable resistor Rp1 are connected with the anode of the input end of the comparator COMP 1; the resistor R6 is connected and arranged between the output end of the operational amplifier OPA and the anode of the input end of the comparator COMP 2; the first end of the resistor Rd2 is grounded, the second end of the adjustable resistor Rp2 is connected with a reference voltage V _ Ref, and the second end of the resistor Rd2 and the second end of the adjustable resistor Rp2 are connected with the negative electrode of the input end of the comparator COMP 2; the output ends of the comparators COMP1 and COMP2 are connected with a voltage VCC through a resistor R7; the output ends of the comparators COMP1 AND COMP2 are connected with the first input end of an AND gate AND, AND the second input end of the AND gate AND is connected with a pulse width modulation signal PWM 1; AND the AND gate AND generates the driving signal PWM _ GDV when V _1 is within the safe working current range of the boosting unit.
In the embodiment of the invention, the safe current range of the NMOS transistor Q1 is determined by adjusting the adjustable resistors Rp1 and RP 2. If the preset safe current range of the NMOS tube Q1 is [ V1, V2], the current of Rp1 is V1 by adjusting the adjustable resistor Rp1, and the current of Rp2 is V2 by adjusting the adjustable resistor Rp 2. When V _1 falls in the range of [ V1, V2], the first input terminal of the AND gate AND can obtain a high level signal, AND when the PWM1 is also high level, the comparing unit outputs a high level driving signal PWM _ GDV for driving the NMOS transistor Q1 to operate. Obviously, the magnitude of the inrush current generated by the voltage boosting unit can be adjusted by adjusting the duty ratio of the PWM1 (i.e., the input power of the PVDD is balanced, and the NMOS transistors Q1 and Q2 are prevented from being damaged by overcurrent and overvoltage). In the embodiment of the present invention, the voltage VCC matches the voltage of the AND gate AND, AND the duty cycle of the modulation signal PWM1 is 50%.
The load unit comprises a bus capacitor C and an adjustable resistor RL; the first end of the bus capacitor C and the first end of the adjustable resistor RL are connected with the drain electrode of the NMOS tube Q1, and the second end of the bus capacitor C and the second end of the adjustable resistor RL are grounded. The input power of the power supply PVDD is balanced through the load unit, so that the whole testing device can work in a stable state, and the damage of NMOS transistors Q1 and Q2 due to overcurrent and overvoltage is avoided.
The basic principle of the invention is as follows: when S1 is closed, the power supply PVDD charges the bus capacitor C directly through the body diode of Q1, which generates a large inrush current at the input. If the Q2 works in a certain current interval, the current of the inductor L is selectively cut off, and a suitable inrush current is generated to allow the common mode voltage variation rate tolerance test of the driving half bridge driving circuit to be tested. Because the testing device has current selectivity, the duty ratio of the NMOS tube Q2 can be configured at will, and the testing device of the invention has small current under the steady-state condition and can work for a long time through the variable resistor RL of the load unit. The invention can overcome the defects of uncontrollable inductive current, poor selection of the duty ratio of Q1 and the like in the measurement of the dv/dt of the half-bridge driving circuit in the prior art.
As shown in fig. 4, in the embodiment of the present invention, the maximum operating current I1 and the minimum operating current I2 of the NMOS transistor are implemented by adjusting the adjustable resistors Rp1 and Rp2, and when the bus rush current is within this range, the PWM of Q2 is in an operating state (PWM ON), otherwise, it is in an OFF state (PWM OFF). During the bus current ramp, dv/dt has reached the failure point a of the IC at time T1, and the half-bridge driving circuit will lose the wave. At time T2 when the bus current drops, dv/dt falls back to B, and the half-bridge driving circuit no longer loses wave and returns to normal.
When the bus impact current is too large, I1 can be adjusted to enable the turn-off current of the NMOS tube Q1 to be in a safe area, so that the tubes Q1 and Q2 are prevented from being damaged, and the half-bridge driving circuit is prevented from being damaged under the condition of too large dv/dt.
Example one
As shown in fig. 5, the peak envelope waveform of the CH2 channel (corresponding to the third test point) in fig. 5 reflects the variation curve of the bus bar surge voltage. Before the dv/dt failure point, the CH1 channel (corresponding to the first test point) shows that the PWM of the half-bridge driving circuit to be tested is in a normal state (common mode signal is superimposed on 50% duty ratio), between the dv/dt failure point and the recovery point, the PWM of the half-bridge driving circuit to be tested is in an abnormal state (wave loss), and after the dv/dt recovery point, the half-bridge driving circuit to be tested is restored to the normal state (common mode signal is superimposed on 50% duty ratio). Therefore, only the values of dv/dt at the dv/dt failure point and the dv/dt recovery point need to be tested, so that the critical dv/dt tolerance value of the half-bridge driving circuit to be tested can be obtained, which is the most effective improvement of the circuit to the traditional mode in the industry.
Fig. 6 shows waveforms of the first and third test points collected when testing the dv/dt failure point, which correspond to the PWM waveform of HO pin (CH1 channel) and the voltage waveform of HS pin (CH2 channel), respectively. By observing the waveforms of the two channels, it is found that in the process of losing the wave of the PWM wave, the bus bar impact voltage rises from 66V (point a) to 203V (point b) within 2.2ns, and therefore, the tolerance failure point of dv/dt is calculated as (203-66)/2.2 as 62V/ns.
Fig. 7 is waveforms of the first to third test points collected when testing the dv/dt recovery point, where the waveforms of the first and second test points are PWM waveforms of HO and IO pins (corresponding to the waveforms of CH1 channel 1 and CH3 channel in fig. 7, respectively), and the waveform of the third test point is a voltage waveform of HS pin (corresponding to the waveform of CH2 channel in fig. 7). When the PWM wave returns to normal, the bus surge voltage decreases from 210V to 71V within 2.44ns, and therefore the tolerable recovery point dv/dt is calculated as (210-71)/2.44 as 56V/ns.
The invention also provides a method for testing the common-mode voltage change rate tolerance of the bootstrap type half-bridge driver, which is realized by adopting the device for testing the common-mode voltage change rate tolerance of the bootstrap type half-bridge driver, and as shown in fig. 3, the method comprises the following steps:
f1, setting a first measurement point between the HO pin and the capacitor Cg1, setting a second measurement point between the LO pin and the capacitor Cg2, and setting a third measurement point between the source of the NMOS transistor Q1 and the first end of the resistor Rg 1; connecting the first measuring point and the second measuring point through an oscilloscope, and measuring whether the bandwidth modulation signal PWM of the half-bridge driving circuit is in an abnormal state; connecting a third measuring point through an oscilloscope, and measuring the bus impact current output to the HS pin of the half-bridge driving circuit by the boosting unit;
f2, disconnecting the input switch S1, and adjusting the resistors Rp1 and Rp2 to enable the Rp1 and the Rp2 to meet the condition that when the power supply PVDD supplies power to the testing device, the current V1 of the Rp1 is larger than the current V2 of the Rp 2;
in step F2:
Rp1adjusted resistance value, R, for resistance Rp1p1Adjusted resistance value, R, for resistance Rp1sFor the resistance of the sampling resistor Rs, R1、R2Is the resistance value of the resistors R1 and R2, Rd1Is the resistance of resistor Rd1, Rd2Is the resistance of resistor Rd2, and (R)p1+Rd1)＝(Rp2+Rd2)＝Rp。
F3, closing the input switch S1, and observing the waveform of the bandwidth modulation signal PWM; when the wave form of the bandwidth modulation signal PWM has wave loss, reading out the failure point of the common-mode voltage conversion rate of the half-bridge driving circuit through an oscilloscope, and entering F4; otherwise, F2 is entered;
f4, disconnecting the input switch S1, adjusting Rp1 to increase the current V1 of the Rp1, and adjusting Rp2 to increase or decrease the current V2 of the Rp 2;
f5, closing the input switch S1, observing the oscilloscope, and judging whether the wave form of the bandwidth modulation signal PWM no longer loses waves; if yes, go to F6; if not, go to F4;
and F6, reading the recovery point of the common-mode voltage conversion rate of the half-bridge driving circuit from the oscilloscope.
In the embodiment of the present invention, in order to achieve a good test effect, the driving unit LSGD further has the following requirements for the inductance L of the endurance testing apparatus, the NMOS transistors Q1, Q2:
1. selection of inductance L
What this patent adopted is that boost main circuit topology is as the boost unit, in order to prevent inductance L saturation, leads to the circuit to damageThe appropriate inductance L must be selected to allow the test apparatus to eventually operate to a steady state. Suppose the final output voltage of the test device is VoFinal steady state inductor current is ILPVDD has an input voltage of VinThe duty ratio of the PWM1 is d, the ripple coefficient is delta, and the switching frequency of the S1 is fsThen, the inductance is:
the magnetic core of the inductor needs to be a magnetic core with a certain direct current bias, such as a ring-shaped magnetic core of sendust or ferrosilicon. Meanwhile, the wire diameter of the inductor needs to meet the requirement of continuous operation under steady-state working current.
2. Selection of NMOS transistors Q1, Q2
Since the measuring device needs to generate high dv/dt, the NMOS transistors Q1 and Q2 not only need to meet the operating voltage and operating current requirements during testing, but also must be able to withstand high dv/dt so as to prevent the internal diodes of Q1 and Q2 from being damaged due to too large dv/dt. Meanwhile, to achieve very fast switching speeds, Q1 and Q2 must select devices with very small Qg (gate charge), which is typically Qg <15 nC.
2. Selection of drive unit LSGD
In the invention, only the NMOS transistors Q1 and Q2 at the Low side (Low side) need to be driven to work, so that an appropriate bottom side driving unit LSGD is selected, and in order to switch the Q1 and Q2 quickly, LSGD chips with high driving current are selected, and the peak value of the LSGD chips is required to be more than 5A.
While the invention has been described with reference to specific embodiments, the invention is not limited thereto, and various equivalent modifications and substitutions can be easily made by those skilled in the art within the technical scope of the invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (10)
1. A bootstrap type half-bridge driver common-mode voltage variation rate tolerance testing device, comprising: the device comprises a bootstrap type half-bridge driving circuit to be tested, a sampling unit, a comparison unit and a boosting unit;
the bootstrap type half-bridge driving circuit to be tested comprises: the device comprises an HB pin, an HO pin, an HS pin, an LO pin, a GND pin, an HI pin and an LI pin, wherein the GND pin is grounded;
the input end of the boosting unit is connected with a power supply PVDD, and the output end of the boosting unit is connected with the HS pin; generating an impact current for testing the common-mode voltage conversion rate of the half-bridge driving circuit through the boosting unit; obtaining the tolerance range of the common-mode voltage change rate of the half-bridge driving circuit by testing the common-mode voltage change rate of a connection point between the output end of the boosting unit and the HS pin, and ensuring that the common-mode voltage change rate of the half-bridge driving circuit is in the safe tolerance range by the boosting unit;
the input end of the sampling unit Is connected with the boosting unit, the working current Is of the boosting unit Is collected, and the sampling unit Is used for sampling the working current Is to generate a sampling current V _ 1;
the input end of the comparison unit is connected with the output end of the sampling unit, and the output end of the comparison unit is connected with the boosting unit; when the comparison unit judges that V _1 is in the safe working current range of the boosting unit, the comparison unit generates a driving signal PWM _ GDV for driving the boosting unit to work; the comparison unit is also used for adjusting the safe working current range of the boosting unit.
2. The bootstrap half-bridge driver common-mode voltage variation rate tolerance test device of claim 1, wherein the sampling unit includes an operational amplifier OPA, resistors R1, R2, R3; a first end of the resistor R1 IS connected with the boosting unit to obtain the working current IS, and a second end of the resistor R1 IS connected with the negative electrode of the input end of the operational amplifier OPA and a first end of the resistor R2; the first end of the resistor R3 is grounded, and the second end of the resistor R3 and the first end of the resistor R4 are connected with the positive electrode of the input end of the operational amplifier OPA; the second end of the resistor R2 is connected with the output end of the operational amplifier OPA; the second terminal of the resistor R4 is connected to the Offset voltage V _ Offset.
3. The bootstrap half-bridge driver common-mode voltage rate of change endurance testing apparatus of claim 1, wherein the comparing unit comprises comparators COMP1, COMP2, resistors R5, R6, R7, Rd1, Rd2, adjustable resistors Rp1, Rp2, AND gate AND; the resistor R5 is connected and arranged between the output end of the operational amplifier OPA and the negative pole of the input end of the comparator COMP 1; the first end of the resistor Rd1 is grounded, and the first end of the adjustable resistor Rp1 is connected with a reference voltage V _ Ref; the second end of the resistor Rd1 and the second end of the adjustable resistor Rp1 are connected with the anode of the input end of the comparator COMP 1; the resistor R6 is connected and arranged between the output end of the operational amplifier OPA and the anode of the input end of the comparator COMP 2; the first end of the resistor Rd2 is grounded, the second end of the adjustable resistor Rp2 is connected with a reference voltage V _ Ref, and the second end of the resistor Rd2 and the second end of the adjustable resistor Rp2 are connected with the negative electrode of the input end of the comparator COMP 2; the output ends of the comparators COMP1 and COMP2 are connected with a voltage VCC through a resistor R7; the output ends of the comparators COMP1 AND COMP2 are connected with the first input end of an AND gate AND, AND the second input end of the AND gate AND is connected with a pulse width modulation signal PWM 1; AND the AND gate AND generates the driving signal PWM _ GDV when V _1 is within the safe working current range of the boosting unit.
4. The bootstrap half-bridge driver common-mode voltage variation rate tolerance test device of claim 3, wherein the voltage VCC matches with a voltage of an AND gate AND, AND a duty cycle of the modulation signal PWM1 is 50%.
5. The bootstrap half-bridge driver common-mode voltage rate of change endurance testing apparatus of claim 1, wherein the boosting unit includes: the circuit comprises an inductor L, resistors Rg1 and Rg2, a sampling resistor Rs, NMOS tubes Q1 and Q2 and a driving unit LSGD;
the first end of the inductor L is connected with a power supply PVDD, the second end of the inductor L is connected with the grid electrode of the NMOS tube Q1 through a resistor Rg1, and the second end of the inductor L is connected with the source electrode of the NMOS tube Q1, the drain electrode of the NMOS tube Q2 and the HS pin;
the first end of the driving unit LSGD is connected with the output end of the AND gate AND, the second end of the driving unit LSGD is connected with the grid electrode of the NMOS tube Q2 through a resistor Rg2, AND the third end of the driving unit LSGD is grounded; the source electrode of the NMOS tube Q2 is connected with the first end of the sampling resistor Rs and the first end of the resistor R1; the second end of the sampling resistor Rs is grounded; the source current of the NMOS tube Q2 Is the working current Is.
6. The bootstrap half-bridge driver common-mode voltage variation rate tolerance test device of claim 1, further comprising an input switch S1, which is connected and disposed between the power supply PVDD and the first terminal of the inductor L.
7. The bootstrap half-bridge driver common-mode voltage variation rate tolerance test device of claim 1, further comprising a load unit; the load unit comprises a bus capacitor C and an adjustable resistor RL; the first end of the bus capacitor C and the first end of the adjustable resistor RL are connected with the drain electrode of the NMOS tube Q1, and the second end of the bus capacitor C and the second end of the adjustable resistor RL are grounded.
8. The bootstrap half-bridge driver common-mode voltage rate of change endurance testing apparatus of claim 1, wherein the half-bridge driving circuit further comprises: capacitances Cb, Cg1, Cg 2; the capacitor Cb is connected between the HB pin and the HS pin, the capacitor Cg1 is connected between the HO pin and the HS pin, and the capacitor Cg2 is connected between the LO pin and the GND pin; the HI pin and the LI pin are used to input complementary bandwidth modulation signals PWM.
9. A bootstrap type half-bridge driver common-mode voltage change rate tolerance test method, which is implemented by using the bootstrap type half-bridge driver common-mode voltage change rate tolerance test device according to any one of claims 1 to 7, characterized by comprising the following steps:
f1, setting a first measurement point between the HO pin and the capacitor Cg1, setting a second measurement point between the LO pin and the capacitor Cg2, and setting a third measurement point between the source of the NMOS transistor Q1 and the first end of the resistor Rg 1; connecting the first measuring point and the second measuring point through an oscilloscope, and measuring whether the bandwidth modulation signal PWM of the half-bridge driving circuit is in an abnormal state; connecting a third measuring point through an oscilloscope, and measuring the bus impact current output to the HS pin of the half-bridge driving circuit by the boosting unit;
f2, disconnecting the input switch S1, and adjusting the resistors Rp1 and Rp2 to enable the Rp1 and the Rp2 to meet the condition that when the power supply PVDD supplies power to the testing device, the current V1 of the Rp1 is larger than the current V2 of the Rp 2;
f3, closing the input switch S1, and observing the waveform of the bandwidth modulation signal PWM; when the wave form of the bandwidth modulation signal PWM has wave loss, reading out the failure point of the common-mode voltage conversion rate of the half-bridge driving circuit through an oscilloscope, and entering F4; otherwise, F2 is entered;
f4, disconnecting the input switch S1, adjusting Rp1 to increase the current V1 of the Rp1, and adjusting Rp2 to increase or decrease the current V2 of the Rp 2;
f5, closing the input switch S1, observing the oscilloscope, and judging whether the wave form of the bandwidth modulation signal PWM no longer loses waves; if yes, go to F6; if not, go to F4;
and F6, reading the recovery point of the common-mode voltage conversion rate of the half-bridge driving circuit from the oscilloscope.
10. The bootstrap half-bridge driver common-mode voltage variation rate tolerance test method of claim 8, wherein in step F2:
Rp1adjusted resistance value, R, for resistance Rp1p1Adjusted resistance value, R, for resistance Rp1sFor the resistance of the sampling resistor Rs, R1、R2Is the resistance value of the resistors R1 and R2, Rd1Is the resistance of resistor Rd1, Rd2Is the resistance of resistor Rd2, and (R)p1+Rd1)＝(Rp2+Rd2)＝Rp。
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