CN112670387B - Surface plasmon enhanced LED and preparation method thereof - Google Patents
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Abstract
The invention belongs to the technical field of LEDs, and discloses a surface plasmon enhanced LED and a preparation method thereof. The surface plasmon enhanced LED comprises a conductive substrate, a first insulating layer, a metal P electrode, a metal nano layer, a metal bonding layer, a columnar N electrode, a second insulating layer, a DBR reflecting layer, a P-type GaN layer, an InGaN/GaN multiple quantum well layer and an N-type GaN layer; the electrode in the structure is an embedded electrode structure. The invention also discloses a preparation method of the surface plasmon enhanced LED. The embedded electrode structure and the metal nano layer are combined, so that the quantum efficiency, the light output power and the modulation bandwidth of the optical communication of the GaN-based LED light source are improved; the metal nano layer is manufactured before the P electrode is manufactured and after the epitaxial growth, so that the problem that the epitaxial chamber is finally polluted due to the fact that the epitaxial layer growth is interrupted to deposit metal in the past is avoided.
Description
Technical Field
The invention relates to the technical field of LEDs, in particular to a surface plasmon enhanced LED and a preparation method thereof.
Background
LEDs are due to their excellent properties, such as: the luminous stability, the heat loss is little, and the life-span is long, is extensively used in traffic, military affairs and daily illumination. In particular, the white light LED replaces the traditional illumination light source, is energy-saving and environment-friendly, and is a new generation of solid-state illumination power supply widely accepted in all circles. As a basis for white LEDs, gaN-based blue LEDs are receiving a great deal of attention. High-efficiency high-power LEDs are an important goal in current LED research and development. Limited by the materials and the technological level, the quantum efficiency of the blue light LED has a great improvement space at present. Therefore, how to improve the luminous efficiency of the LED, design and manufacture the LED with high brightness and high efficiency has very important research and application values.
The surface plasmon generated by the metal nanostructure is utilized to enhance the LED luminescence, so that the internal quantum efficiency of the LED can be improved, and the modulation bandwidth of the LED can be improved to be suitable for visible light communication. However, the doping of the metal nanostructure into the LED epitaxial structure often requires interruption of the epitaxial layer growth, preparation of the metal nanostructure, and completion of the epitaxial growth, and the prepared metal nanoparticle often causes contamination of the equipment chamber for the epitaxial growth, and also increases the complexity of the process.
Disclosure of Invention
In order to overcome the defects of the prior art, the invention aims to provide a surface plasmon enhanced LED and a preparation method thereof. According to the invention, the metal nano layer is manufactured before the P electrode is manufactured and after the epitaxial growth, so that the problem that the conventional structure interrupts the epitaxial growth to deposit the metal nano structure and then further extends to cause metal pollution to the epitaxial chamber is avoided. The embedded electrode structure is combined with the nano layer of the surface plasmon, so that the LED has better performance. The invention can also change the distance between the metal nano layer and the quantum well by changing the etching depth of the P electrode hole so as to improve and optimize the surface plasmon effect.
The aim of the invention is achieved by the following technical scheme.
The surface plasmon enhanced LED comprises a conductive substrate, a first insulating layer, a metal P electrode, a metal nano layer, a metal bonding layer, a columnar N electrode, a second insulating layer, a DBR reflecting layer, a P-type GaN layer, an InGaN/GaN multiple quantum well layer and an N-type GaN layer; a metal bonding layer, a second insulating layer, a DBR reflecting layer, a p-type GaN layer, an InGaN/GaN multiple quantum well layer and an n-type GaN layer are sequentially formed on the conductive substrate; the metal P electrode sequentially penetrates through the conductive substrate, the metal bonding layer, the second insulating layer and the DBR reflecting layer until the end part of the metal P electrode extends to the inside of the P-type GaN layer; one end of the metal P electrode extending to the inside of the P-type GaN layer is provided with a metal nano layer; the first insulating layer is positioned on the surface of the metal P electrode, the first insulating layers are not arranged at the two ends of the metal P electrode, and the first insulating layers sequentially penetrate through the conductive substrate, the metal bonding layer, the second insulating layer and the DBR reflecting layer to the inside of the P-type GaN layer; the columnar N electrode sequentially penetrates through the second insulating layer, the DBR reflecting layer, the p-type GaN layer and the InGaN/GaN multiple quantum well layer until reaching the inside of the N-type GaN layer, and does not penetrate through the N-type GaN layer; the surface of the columnar N electrode is provided with an insulating layer, the insulating layer and the second insulating layer form a whole, and the two ends of the columnar N electrode are not provided with insulating layers (one end of the N electrode is contacted with the N-type GaN layer).
And an insulating layer arranged on the surface of the columnar N electrode sequentially penetrates through the DBR reflecting layer, the p-type GaN layer and the InGaN/GaN multiple quantum well layer until reaching the inside of the N-type GaN layer.
The columnar N electrode and the conductive substrate form a conductive path. The columnar N electrode penetrates through the conductive substrate and the metal bonding layer, namely, the columnar N electrode penetrates through the conductive substrate, the metal bonding layer, the second insulating layer, the DBR reflecting layer, the p-type GaN layer, the InGaN/GaN multiple quantum well layer and the N-type GaN layer in sequence. At this time, an insulating layer is arranged on the surface of the N electrode penetrating through the conductive substrate and the metal bonding layer, the lower end of the N electrode is not provided with the insulating layer, and the lower end comprises an end face and a part of the surface penetrating through the conductive substrate.
The metal nano layer is positioned at the contact interface of the metal P electrode and the P-type GaN. The metal nano layer partially covers the p-type GaN layer.
At the interface, the end surface formed by the metal nano layer and the metal P electrode is a horizontal plane or a tooth shape.
Further, the metal nano layer is positioned at the contact interface between the metal P electrode and the P-type GaN, and can be more than one of Ag nano columns, ag nano discs and Ag nano particles.
Further, the resonance wavelength of the metal nano layer is matched with that of the LED device.
Further, the diameter of the metal nano layer is 50-3000nm, and the height is 50-500nm.
Further, the saidThe metal P electrode is positioned at the bottom of the LED chip, ohmic contact is formed between the top of the metal P electrode and P-type GaN, and the outer wall of the P electrode is separated from the N electrode by an insulating medium. The insulating medium is SiO 2 。
The insulating layer in the structure is made of SiO 2 。
The first insulating layer is made of SiO 2 The method comprises the steps of carrying out a first treatment on the surface of the The second insulating layer is made of SiO 2 。
Further, the upper surface of the columnar N electrode is in ohmic contact with the N-type GaN.
Further, the conductive substrate is a SiC substrate or a Si substrate, and the thickness is 50-500 mu m; the first insulating layer and the second insulating layer are SiO2 insulating layers, and the thickness is 100-2000nm.
Further, the DBR reflection layer is SiO 2 /TiO 2 The periodic material is 6-18 periods, and the thickness of each period is 50-200nm.
Further, the columnar N electrode is more than one of Ti, cr, ag, au, pt. The height of the columnar N electrode is 2-10 mu m; the metal P electrode is one or more of Cr, pt and Au.
Further, the metal bonding layer is more than one of Ni, au, sn, ti, and the thickness is 500nm-5 μm.
The number of the N electrodes is more than or equal to 2.
The preparation method of the surface plasmon enhanced LED comprises the following steps:
(1) Taking an epitaxial substrate, sequentially growing a buffer layer, an n-type GaN layer, an InGaN/GaN multiple quantum well layer and a p-type GaN layer on the epitaxial substrate, and preparing a DBR reflecting layer to obtain an LED epitaxial wafer;
(2) Preparing a through hole structure on the LED epitaxial wafer in the step (1); the through hole structure radially penetrates through the DBR reflecting layer, the p-type GaN layer and the InGaN/GaN multiple quantum well layer in sequence, and extends into the N-type GaN layer to obtain an embedded columnar N electrode channel;
(3) Growing a second insulating layer on the upper surface of the DBR reflecting layer and on the inner wall of the through hole structure, wherein the inner wall does not comprise the bottom of the through hole structure;
(4) Depositing an embedded columnar N electrode in the through hole structure;
(5) Depositing a metal bonding layer on the second insulating layer and the end face of the columnar N electrode to obtain a wafer; a conductive substrate is taken, and a metal bonding layer is deposited on the conductive substrate; bonding and connecting the wafer and the conductive substrate through a metal bonding layer by adopting a metal bonding process;
(6) Preparing a metal P electrode channel by etching; the metal P electrode channel sequentially radially penetrates through the conductive substrate, the metal bonding layer, the second insulating layer, the DBR reflecting layer and extends into the P-type GaN layer; the conductive substrate is etched after being thinned by adopting a thinning process;
(7) Growing a first insulating layer on the inner wall of the metal P electrode channel; the bottom of the metal P electrode channel is free of a first insulating layer;
(8) Carrying out metal evaporation on the bottom of the metal P electrode channel, and carrying out annealing treatment in a protective atmosphere to obtain a metal nano layer;
(9) P electrode metal deposition is carried out in a metal P electrode channel for preparing a metal nano layer, so as to obtain a metal P electrode;
(10) And finally, stripping the epitaxial substrate, and etching the buffer layer to obtain the LED chip.
In the step (2), photoetching and ICP etching can be adopted to prepare a through hole structure;
in the step (8), the annealing temperature of the metal nano layer is 500-900 ℃ and the annealing time is 2-5min, and the diameter of the metal nano particles is controlled to be 50-800nm by adjusting the annealing temperature, the annealing time and the thickness of the metal film; the protective atmosphere is a nitrogen atmosphere.
In the step (10), the epitaxial substrate is peeled off by adopting a method of mechanical thinning, chemical polishing, chemical corrosion and laser peeling, and the buffer layer is peeled off by adopting ICP dry etching.
Or the steps (2) to (5) are as follows:
(2) Preparing a second insulating layer on the DBR reflective layer; depositing a metal bonding layer on the second insulating layer to obtain a wafer; a conductive substrate is taken, and a metal bonding layer is deposited on the conductive substrate; bonding and connecting the wafer and the conductive substrate through a metal bonding layer by adopting a metal bonding process;
(3) Preparing a through hole structure; the through hole structure sequentially penetrates through the conductive substrate, the metal bonding layer, the second insulating layer, the DBR reflecting layer, the p-type GaN layer and the InGaN/GaN multiple quantum well layer in the radial direction, and extends to the inside of the N-type GaN layer to obtain a columnar N electrode channel;
(4) Growing an insulating layer on the inner wall of the through hole structure, wherein the inner wall does not comprise the bottom of the through hole structure, and the insulating layer does not exist from the opening part of the through hole structure to part of the inner wall in the conductive substrate;
(5) And depositing a columnar N electrode in the through hole structure.
Compared with the prior art, the invention has the following advantages:
according to the surface plasmon enhanced LED chip provided by the invention, the quantum efficiency, the light output power and the modulation bandwidth of optical communication of the GaN-based LED light source can be improved by utilizing the metal surface plasmon effect; and the metal nano layer is manufactured after epitaxial growth, so that the problem that the epitaxial chamber is finally polluted due to the fact that the epitaxial layer is interrupted to grow so as to deposit metal in the past is avoided.
Drawings
Fig. 1 is a cross-sectional view of an epitaxial wafer obtained by preparing an epitaxial substrate in example 1; a 100-AlGaN buffer layer, a 101-epitaxial substrate, a 102-n type GaN layer, a 103-InGaN/GaN multiple quantum well layer, a 104-p type GaN layer and a 105-DBR reflecting layer;
fig. 2 is a cross-sectional view of a columnar N electrode fabricated on an epitaxial wafer in example 1; a 100-AlGaN buffer layer, a 101-epitaxial substrate, a 102-N type GaN layer, a 103-InGaN/GaN multiple quantum well layer, a 104-p type GaN layer, a 105-DBR reflecting layer, a 106-columnar N electrode and a 107-second insulating layer;
fig. 3 is a cross-sectional view of the fabrication of a metal nanolayer on an epitaxial wafer in example 1; 100-AlGaN buffer layer, 101-epitaxial substrate, 102-N type GaN layer, 103-InGaN/GaN multiple quantum well layer, 104-p type GaN layer, 105-DBR reflection layer, 106-columnar N electrode, 107-second insulating layer, 108-metal bonding layer, 109-conductive substrate, 110-metal nano layer and 111-first insulating layer;
fig. 4 is a cross-sectional view of the surface plasmon enhanced LED provided in embodiment 1; 102-N type GaN layer, 103-InGaN/GaN multiple quantum well layer, 104-P type GaN layer, 105-DBR reflecting layer, 106-column N electrode, 107-second insulating layer, 108-metal bonding layer, 109-conductive substrate, 110-metal nano layer, 111-first insulating layer, 112-metal P electrode;
fig. 5 is a top cross-sectional view of the surface plasmon enhanced LED provided in embodiment 1; 106-columnar N electrode and 110-metal nano layer;
fig. 6 is a bottom electrode diagram of the surface plasmon enhanced LED provided in embodiment 1; 109-a conductive substrate, 111-a first insulating layer, 112-a metal P electrode;
fig. 7 is a cross-sectional view of a surface plasmon enhanced LED provided in embodiment 2; 102-N type GaN layer, 103-InGaN/GaN multiple quantum well layer, 104-P type GaN layer, 105-DBR reflecting layer, 106-column N electrode, 107-second insulating layer, 108-metal bonding layer, 109-conductive substrate, 110-metal nano layer, 111-first insulating layer, 112-metal P electrode;
fig. 8 is a cross-sectional view of a surface plasmon enhanced LED provided in embodiment 3; 102-N type GaN layer, 103-InGaN/GaN multiple quantum well layer, 104-P type GaN layer, 105-DBR reflection layer, 106-column N electrode, 107-second insulation layer, 108-metal bonding layer, 109-conductive substrate, 110-metal nano layer, 111-first insulation layer, and 112-metal P electrode.
Detailed Description
The following describes the embodiments of the present invention further with reference to specific examples and drawings, but the embodiments of the present invention are not limited thereto.
Example 1
The present embodiment provides a surface plasmon enhanced LED, as shown in fig. 4, which includes a conductive substrate 109, a metal bonding layer 108, a second insulating layer 107, a DBR reflecting layer 105, a p-type GaN layer 104, an InGaN/GaN multiple quantum well layer 103, and an n-type GaN layer 102, which are sequentially distributed from bottom to top;
the surface plasmon enhanced LED further comprises a metal P electrode 112, a first insulating layer 111 and a columnar N electrode 106; the metal P electrode 112 sequentially penetrates through the conductive substrate 109, the metal bonding layer 108, the second insulating layer 107, and the dbr reflecting layer 105 until the end of the metal P electrode extends into the P-type GaN layer 104; one end of the metal P electrode extending to the inside of the P-type GaN layer is provided with a metal nano layer 110; the first insulating layer 111 is located on the surface of the metal P electrode, and there is no first insulating layer at two ends of the metal P electrode, and the first insulating layer 111 sequentially penetrates through the conductive substrate 109, the metal bonding layer 108, the second insulating layer 107, the dbr reflecting layer 105, and the P-type GaN layer 104; the columnar N electrode 106 sequentially penetrates through the second insulating layer 107, the dbr reflecting layer 105, the p-type GaN layer 104, and the ingan/GaN multiple quantum well layer 103 until reaching the inside of the N-type GaN layer 102, and the columnar N electrode does not penetrate through the N-type GaN layer; the surface of the columnar N electrode is provided with an insulating layer, the insulating layer and the second insulating layer form a whole, and the two ends of the columnar N electrode are not provided with insulating layers.
The metal nano-layer 110 is located at the contact interface of the metal P-electrode 112 and the P-type GaN layer 104.
The metal P-electrode 112 is located at the bottom of the LED chip, the top of the metal P-electrode is in ohmic contact with the P-type GaN layer 104, and the outer wall of the P-electrode 112 is separated from the N-electrode 106 by an insulating medium.
The upper surface of the columnar N electrode 106 contacts with the N-type GaN layer 102 to form an ohmic contact.
The thickness of the p-type GaN layer 104 is 200nm; the InGaN/GaN multiple quantum well layer 103 has 8 periods and a thickness of 50nm; the thickness of n-type GaN is 3 μm; the first insulating layer is 1 μm thick SiO 2 A layer; the second insulating layer is 2 μm of SiO 2 A layer.
The DBR reflection layer 105 is SiO 2 Layer and TiO 2 The layers are alternately grown for 5 periods of SiO 2 The thickness of the layer is 75nm, tiO 2 The thickness of the layer was 45nm.
The conductive substrate 109 is a Si substrate with a thickness of 400 μm.
The metal P electrode 112 is a composite electrode composed of a Cr electrode, a Pt electrode and an Au electrode; the columnar N electrode 106 is a composite electrode of a Cr electrode and an Al electrode.
The metal bonding layer 108 is Ni/Au with a thickness of 500nm.
The embodiment provides a preparation method of the surface plasmon enhanced LED, which comprises the following steps:
(1) An epitaxial substrate (SiC substrate) is taken, an AlGaN buffer layer 100, an n-type GaN layer 102, an InGaN/GaN multi-quantum well layer 103 and a p-type GaN layer 104 which are 5um thick are sequentially grown on the epitaxial substrate 101 (SiC substrate) by adopting MOCVD equipment, and a PECVD (plasma enhanced chemical vapor deposition) is continuously used for depositing a DBR reflecting layer 105 on the p-type GaN layer 104, so that an LED epitaxial wafer is obtained; preparing an LED epitaxial wafer on an epitaxial substrate, wherein the epitaxial wafer comprises an epitaxial substrate 101, an AlGaN buffer layer 100, an n-type GaN layer 102, an InGaN/GaN multi-quantum well layer 103, a p-type GaN layer 104 and a DBR reflecting layer 105 from bottom to top in sequence, as shown in FIG. 1;
(2) Preparing a plurality of hole structures which sequentially penetrate through the DBR reflecting layer 105, the p-type GaN layer 104 and the InGaN/GaN multiple quantum well luminous layer 103 and extend into the N-type GaN layer 102 on the LED epitaxial wafer to obtain an embedded columnar N electrode channel;
(3) Growing a second insulating layer 107 on the upper surface of the DBR reflecting layer 105 and the inner wall of the through hole structure by PECVD so as to completely cover the DBR reflecting layer 105, the inner wall of the through hole structure and the bottom, and removing the second insulating layer 107 at the bottom of the through hole structure by selective acid corrosion to expose the bottom of the through hole structure;
(4) Depositing an N electrode in the through hole structure to form an embedded columnar N electrode 106; a cross-sectional view of a columnar N electrode fabricated on an epitaxial wafer is shown in fig. 2;
(5) A metal bonding layer is deposited on the top of the second insulating layer 107 and the columnar N electrode 108 by using an electron beam evaporation apparatus, and a conductive Si substrate 109 is further used to deposit the metal bonding layer. Bonding and connecting the two wafers through a metal bonding process, applying pressure from the center of the transfer conductive substrate 109 of the second wafer in the bonding process, gradually expanding the pressure to the edge, bonding for 2 hours at 300 ℃ after the bonding pressure reaches 2MPa, annealing, taking out, feeding into an annealing furnace, preserving heat for 30 minutes at 200 ℃, and forming firm bonding between the pre-bonded wafers;
(6) Thinning the transfer conductive substrate by adopting a thinning process, and then performing ICP etching to obtain a metal P electrode channel;
(7) Growing a first insulating layer positioned on the inner wall and the bottom of the channel in the metal P electrode channel by adopting PECVD, and then etching the insulating layer at the bottom by adopting acid to obtain a first insulating layer 111;
(8) Depositing metal Ag in the through hole structure, performing high-temperature rapid heat treatment by adopting a rapid annealing furnace, annealing in a high-temperature high-purity nitrogen environment at 550 ℃, and forming Ag metal nano particles 110 in a nitrogen environment for 80 seconds, wherein the distance between the metal nano particles and a quantum well is relatively short, so that the near-field coupling requirement of surface plasmons can be met; a cross-sectional view of a metal nano layer fabricated on an epitaxial wafer is shown in fig. 3;
(9) Depositing metal in the metal P electrode through hole to obtain a metal P electrode;
(10) And mechanically grinding the epitaxial substrate of the double-substrate LED epitaxial wafer, stripping the substrate by adopting laser until the epitaxial substrate 101 disappears, removing the AlGaN buffer layer by adopting ICP etching, exposing the n-type GaN layer 102, and finally obtaining the surface plasmon enhanced LED.
Fig. 1 is a cross-sectional view of an epitaxial wafer obtained by preparing an epitaxial substrate in example 1; fig. 2 is a cross-sectional view of a columnar N electrode fabricated on an epitaxial wafer in example 1; fig. 3 is a cross-sectional view of the fabrication of a metal nanolayer on an epitaxial wafer in example 1; fig. 4 is a cross-sectional view of the surface plasmon enhanced LED provided in embodiment 1; fig. 5 is a top cross-sectional view of the surface plasmon enhanced LED provided in embodiment 1; fig. 6 is a bottom electrode view of the surface plasmon enhanced LED provided in embodiment 1.
Example 2
The embodiment provides an LED chip (LED-2), which is different from embodiment 1 in that the manufacturing process of the columnar N electrode is mainly characterized in that after bonding a first wafer which is not subjected to photoetching etching of an N-type hole and N electrode deposition with a second wafer, the columnar electrode hole of the N electrode is manufactured through photoetching etching and other processes, an insulating layer is grown inside the N electrode hole through PECVD, and a section of inner wall of the top part is left without SiO in the growing process 2 Covering to ensure that the columnar N electrode is connected with the conductive substrate to form electric conduction, and finally depositing the N electrode in the columnar hole through a metal evaporation process.
Specifically, the steps (2) to (5) are different from example 1:
(2) Preparing a second insulating layer on the DBR reflective layer; depositing a metal bonding layer on the second insulating layer to obtain a wafer; a conductive substrate is taken, and a metal bonding layer is deposited on the conductive substrate; bonding and connecting the wafer and the conductive substrate through a metal bonding layer by adopting a metal bonding process;
(3) Preparing a through hole structure; the through hole structure sequentially penetrates through the conductive substrate, the metal bonding layer, the second insulating layer, the DBR reflecting layer, the p-type GaN layer and the InGaN/GaN multiple quantum well layer in the radial direction, and extends to the inside of the N-type GaN layer to obtain a columnar N electrode channel;
(4) Growing an insulating layer on the inner wall of the through hole structure, wherein the inner wall does not comprise the bottom of the through hole structure, and the insulating layer does not exist from the opening part of the through hole structure to part of the inner wall in the conductive substrate;
(5) And depositing a columnar N electrode in the through hole structure.
Other structural methods are exactly the same as in example 1.
Fig. 7 is a cross-sectional view of the surface plasmon enhanced LED provided in embodiment 2.
The surface plasmon enhanced LED in this embodiment includes a conductive substrate 109, a first insulating layer 111, a metal P electrode 112, a metal nano layer 110, a metal bonding layer 108, a columnar N electrode 106, a second insulating layer 107, a DBR reflecting layer 105, a P-type GaN layer 104, an InGaN/GaN multiple quantum well layer 103, an N-type GaN layer 102; a metal bonding layer 108, a second insulating layer 107, a DBR reflecting layer 105, a p-type GaN layer 104, an InGaN/GaN multiple quantum well layer 103 and an n-type GaN layer 102 are sequentially formed on the conductive substrate 109; the metal P electrode 112 sequentially penetrates through the conductive substrate 109, the metal bonding layer 108, the second insulating layer 107, and the dbr reflecting layer 105 until the end of the metal P electrode 112 extends into the P-type GaN layer 104; one end of the metal P electrode extending to the inside of the P-type GaN layer is provided with a metal nano layer 110; the first insulating layer 111 is located on the surface of the metal P electrode 112, and there is no first insulating layer at two ends of the metal P electrode, and the first insulating layer 111 sequentially penetrates through the conductive substrate 109, the metal bonding layer 108, the second insulating layer 107, the dbr reflecting layer 105, and the P-type GaN layer 104; the columnar N electrode 106 sequentially penetrates through the second insulating layer 107, the dbr reflecting layer 105, the p-type GaN layer 104, and the ingan/GaN multiple quantum well layer 103 until reaching the inside of the N-type GaN layer 102, and the columnar N electrode 106 does not penetrate through the N-type GaN layer 102; the surface of the columnar N electrode 106 is provided with an insulating layer, the insulating layer and the second insulating layer form a whole, and two ends of the columnar N electrode 106 are not provided with insulating layers.
The insulating layer provided on the surface of the columnar N electrode 106 penetrates the DBR reflecting layer 105, the p-type GaN layer 104, and the ingan/GaN multiple quantum well layer 103 in order until reaching the inside of the N-type GaN layer 102.
The columnar N electrode and the conductive substrate form a conductive path. The columnar N electrode 106 further penetrates through the conductive substrate 109 and the metal bonding layer 108, that is, the columnar N electrode 106 penetrates through the conductive substrate 106, the metal bonding layer 108, the second insulating layer 107, the DBR reflecting layer 105, the p-type GaN layer 104, the InGaN/GaN multiple quantum well layer 103, and up to the inside of the N-type GaN layer 102 in this order. At this time, an insulating layer is arranged on the surface of the N electrode penetrating through the conductive substrate and the metal bonding layer, the lower end of the N electrode is not provided with the insulating layer, and the lower end comprises an end face and a part of the surface penetrating through the conductive substrate.
Example 3
The difference between the LED chip (LED-3) and the embodiment 1 is that the bottom of the P-electrode channel is in a trapezoid structure or tooth shape when the P-electrode channel is manufactured, so that the etching depth of P-type GaN and the coupling distance between the metal nanostructure and the multiple quantum dots can be changed, and the photoelectric property is affected. Other structural methods are exactly the same as in example 1.
Fig. 8 is a cross-sectional view of the surface plasmon enhanced LED provided in embodiment 3.
The above embodiments are only preferred embodiments of the present invention, and the scope of the present invention is not limited thereto, but any insubstantial changes and substitutions made by those skilled in the art on the basis of the present invention are intended to be within the scope of the present invention as claimed.
Claims (8)
1. A surface plasmon enhanced LED, characterized by: the semiconductor device comprises a conductive substrate, a first insulating layer, a metal P electrode, a metal nano layer, a metal bonding layer, a columnar N electrode, a second insulating layer, a DBR reflecting layer, a P-type GaN layer, an InGaN/GaN multiple quantum well layer and an N-type GaN layer; a metal bonding layer, a second insulating layer, a DBR reflecting layer, a p-type GaN layer, an InGaN/GaN multiple quantum well layer and an n-type GaN layer are sequentially formed on the conductive substrate; the metal P electrode sequentially penetrates through the conductive substrate, the metal bonding layer, the second insulating layer and the DBR reflecting layer until the end part of the metal P electrode extends to the inside of the P-type GaN layer; one end of the metal P electrode extending to the inside of the P-type GaN layer is provided with a metal nano layer; the first insulating layer is positioned on the surface of the metal P electrode, the first insulating layers are not arranged at the two ends of the metal P electrode, and the first insulating layers sequentially penetrate through the conductive substrate, the metal bonding layer, the second insulating layer and the DBR reflecting layer to the inside of the P-type GaN layer; the columnar N electrode sequentially penetrates through the second insulating layer, the DBR reflecting layer, the p-type GaN layer and the InGaN/GaN multiple quantum well layer until reaching the inside of the N-type GaN layer, and does not penetrate through the N-type GaN layer; the surface of the columnar N electrode is provided with an insulating layer, the insulating layer and the second insulating layer form a whole, and the two ends of the columnar N electrode are not provided with insulating layers;
the DBR reflecting layer is SiO 2 /TiO 2 The periodic material is 5-18 periods, and the thickness of each period is 50-200nm;
the columnar N electrode is more than one of Ti, cr, ag, au, pt;
the metal P electrode is one or more of Cr, pt and Au;
the metal bonding layer is more than one of Ni, au, sn, ti;
the diameter of the metal nano layer is 50-3000nm, and the height is 50-500nm;
the conductive substrate is a SiC substrate or a Si substrate, and the thickness is 50-500 mu m; the first insulating layer and the second insulating layer are SiO 2 An insulating layer with an independent thickness of 100-2000nm;
the height of the columnar N electrode is 2-10 mu m;
the thickness of the metal bonding layer is 500nm-5 mu m;
the number of the N electrodes is more than or equal to 2.
2. The surface plasmon enhanced LED of claim 1 wherein: the insulating layer arranged on the surface of the columnar N electrode sequentially penetrates through the DBR reflecting layer, the p-type GaN layer and the InGaN/GaN multiple quantum well layer until reaching the inside of the N-type GaN layer;
the metal nano layer is positioned at the contact interface of the metal P electrode and the P-type GaN.
3. The surface plasmon enhanced LED of claim 1 wherein: the columnar N electrode penetrates through the conductive substrate and the metal bonding layer, namely the columnar N electrode penetrates through the conductive substrate, the metal bonding layer, the second insulating layer, the DBR reflecting layer, the p-type GaN layer, the InGaN/GaN multiple quantum well layer and the N-type GaN layer in sequence; at this time, an insulating layer is arranged on the surface of the N electrode penetrating through the conductive substrate and the metal bonding layer, the lower end of the N electrode is not provided with the insulating layer, and the lower end comprises an end face and a part of the surface penetrating through the conductive substrate.
4. The surface plasmon enhanced LED of claim 1 wherein: at the interface of the metal P electrode and the P-type GaN, the end surface formed by the metal nano layer and the metal P electrode is horizontal or tooth-shaped.
5. The surface plasmon enhanced LED of claim 1 wherein: the metal nano layer is one or more of Ag nano columns, ag nano discs and Ag nano particles;
the first insulating layer is made of SiO 2 The method comprises the steps of carrying out a first treatment on the surface of the The second insulating layer is made of SiO 2 。
6. The method for preparing the surface plasmon enhanced LED according to any one of claims 1 to 5, characterized in that: the method comprises the following steps:
(1) Taking an epitaxial substrate, and sequentially growing a buffer layer, an n-type GaN layer and InGaN +.
The GaN multi-quantum well layer, the p-type GaN layer, and the DBR reflecting layer are prepared to obtain the LED epitaxial wafer;
(2) Preparing a through hole structure on the LED epitaxial wafer in the step (1); the through hole structure radially penetrates through the DBR reflecting layer, the p-type GaN layer and the InGaN/GaN multiple quantum well layer in sequence, and extends into the N-type GaN layer to obtain an embedded columnar N electrode channel;
(3) Growing a second insulating layer on the upper surface of the DBR reflecting layer and on the inner wall of the through hole structure, wherein the inner wall does not comprise the bottom of the through hole structure;
(4) Depositing an embedded columnar N electrode in the through hole structure;
(5) Depositing a metal bonding layer on the second insulating layer and the end face of the columnar N electrode to obtain a wafer; a conductive substrate is taken, and a metal bonding layer is deposited on the conductive substrate; bonding and connecting the wafer and the conductive substrate through a metal bonding layer by adopting a metal bonding process;
(6) Preparing a metal P electrode channel by etching; the metal P electrode channel sequentially radially penetrates through the conductive substrate, the metal bonding layer, the second insulating layer, the DBR reflecting layer and extends into the P-type GaN layer;
(7) Growing a first insulating layer on the inner wall of the metal P electrode channel; the bottom of the metal P electrode channel is free of a first insulating layer;
(8) Metal evaporation is carried out at the bottom of the metal P electrode channel, annealing treatment is carried out under a protective atmosphere,
obtaining a metal nano layer;
(9) P electrode metal deposition is carried out in a metal P electrode channel for preparing a metal nano layer, so as to obtain a metal P electrode;
(10) And finally, stripping the epitaxial substrate, and etching the buffer layer to obtain the LED chip.
7. The method for manufacturing a surface plasmon enhanced LED of claim 6, wherein: in the step (8), the annealing temperature is 500-900 ℃, and the annealing time is 2-5min.
8. The method for manufacturing a surface plasmon enhanced LED of claim 6, wherein: or the steps (2) - (5) are as follows:
(2) Preparing a second insulating layer on the DBR reflective layer; depositing a metal bonding layer on the second insulating layer to obtain a wafer; a conductive substrate is taken, and a metal bonding layer is deposited on the conductive substrate; bonding and connecting the wafer and the conductive substrate through a metal bonding layer by adopting a metal bonding process;
(3) Preparing a through hole structure; the through hole structure sequentially penetrates through the conductive substrate, the metal bonding layer, the second insulating layer, the DBR reflecting layer, the p-type GaN layer and the InGaN/GaN multiple quantum well layer in the radial direction, and extends to the inside of the N-type GaN layer to obtain a columnar N electrode channel;
(4) Growing an insulating layer on the inner wall of the through hole structure, wherein the inner wall does not comprise the bottom of the through hole structure, and the insulating layer does not exist from the opening part of the through hole structure to part of the inner wall in the conductive substrate;
(5) And depositing a columnar N electrode in the through hole structure.
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