CN112670175B - Method for manufacturing semiconductor structure - Google Patents
Method for manufacturing semiconductor structure Download PDFInfo
- Publication number
- CN112670175B CN112670175B CN202011544162.3A CN202011544162A CN112670175B CN 112670175 B CN112670175 B CN 112670175B CN 202011544162 A CN202011544162 A CN 202011544162A CN 112670175 B CN112670175 B CN 112670175B
- Authority
- CN
- China
- Prior art keywords
- dielectric
- layer
- dielectric block
- block
- dielectric layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims abstract description 62
- 239000004065 semiconductor Substances 0.000 title claims abstract description 32
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 24
- 239000000463 material Substances 0.000 claims abstract description 58
- 239000000758 substrate Substances 0.000 claims abstract description 35
- 238000002444 silanisation Methods 0.000 claims abstract description 11
- 229920002120 photoresistant polymer Polymers 0.000 claims description 43
- 238000005530 etching Methods 0.000 claims description 19
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 18
- 238000000206 photolithography Methods 0.000 claims description 15
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 15
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 10
- 229920001477 hydrophilic polymer Polymers 0.000 claims description 8
- 238000001039 wet etching Methods 0.000 claims description 8
- 230000003647 oxidation Effects 0.000 claims description 7
- 238000007254 oxidation reaction Methods 0.000 claims description 7
- 239000000126 substance Substances 0.000 claims description 6
- 230000000717 retained effect Effects 0.000 claims description 5
- 238000000151 deposition Methods 0.000 claims 1
- 238000000059 patterning Methods 0.000 abstract description 12
- 238000001259 photo etching Methods 0.000 abstract description 3
- 239000010408 film Substances 0.000 description 35
- 229910004298 SiO 2 Inorganic materials 0.000 description 12
- 238000010586 diagram Methods 0.000 description 12
- 238000005516 engineering process Methods 0.000 description 7
- 238000001312 dry etching Methods 0.000 description 6
- 238000000231 atomic layer deposition Methods 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- CURLTUGMZLYLDI-UHFFFAOYSA-N Carbon dioxide Chemical compound O=C=O CURLTUGMZLYLDI-UHFFFAOYSA-N 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical group [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 4
- 238000005137 deposition process Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 229910052760 oxygen Inorganic materials 0.000 description 4
- 239000001301 oxygen Substances 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 238000006884 silylation reaction Methods 0.000 description 4
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 description 4
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 3
- 230000008014 freezing Effects 0.000 description 3
- 238000007710 freezing Methods 0.000 description 3
- 229910052739 hydrogen Inorganic materials 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 229910052755 nonmetal Inorganic materials 0.000 description 3
- 239000011347 resin Substances 0.000 description 3
- 229920005989 resin Polymers 0.000 description 3
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 3
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 2
- 239000002253 acid Substances 0.000 description 2
- 239000012670 alkaline solution Substances 0.000 description 2
- 239000007864 aqueous solution Substances 0.000 description 2
- 229910052799 carbon Inorganic materials 0.000 description 2
- 229910002092 carbon dioxide Inorganic materials 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 239000001257 hydrogen Substances 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 229920000642 polymer Polymers 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 229910000077 silane Inorganic materials 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 125000003277 amino group Chemical group 0.000 description 1
- 230000003667 anti-reflective effect Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000001569 carbon dioxide Substances 0.000 description 1
- 125000002843 carboxylic acid group Chemical group 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 125000000524 functional group Chemical group 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 229920001600 hydrophobic polymer Polymers 0.000 description 1
- 125000002887 hydroxy group Chemical group [H]O* 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- VUZPPFZMUPKLLV-UHFFFAOYSA-N methane;hydrate Chemical compound C.O VUZPPFZMUPKLLV-UHFFFAOYSA-N 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000003960 organic solvent Substances 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000006552 photochemical reaction Methods 0.000 description 1
- 230000035484 reaction time Effects 0.000 description 1
- 239000013049 sediment Substances 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 238000004381 surface treatment Methods 0.000 description 1
- 239000004094 surface-active agent Substances 0.000 description 1
- 125000003396 thiol group Chemical group [H]S* 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Landscapes
- Drying Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention relates to a manufacturing method of a semiconductor structure, which comprises the following steps: providing a substrate, forming a film layer to be etched on the substrate and a first dielectric layer on the film layer to be etched, wherein the first dielectric layer is formed into a plurality of independent first dielectric blocks arranged at intervals; performing silanization treatment on the surface of the first dielectric block to form a second dielectric layer around the first dielectric block; the second dielectric layer is chemically treated to form a third dielectric layer of a material different from the second dielectric. The method has the advantages that the result of quadruple patterning can be achieved by only one-time photoetching, the method can be suitable for process nodes with critical dimensions of 5nm or even smaller, the number of masks is saved, and the cost and the production period are saved.
Description
[ Field of technology ]
The invention relates to the technical field of semiconductors, in particular to a manufacturing method of a semiconductor structure.
[ Background Art ]
With the continuous development of the integrated circuit industry, the size of semiconductor devices is smaller and smaller, and the integration level is higher and higher. In order to integrate larger numbers of smaller transistors on a chip, new technologies are continually being developed to continually reduce the transistor size. While the size of semiconductor devices is limited by the wavelength of the lithographic light source, extreme ultraviolet light (EUV) is ultraviolet light with a wavelength of 13.4nm, which is currently the smallest wavelength light source. While users require the smallest dimension of the semiconductor device to be 5nm or less, it is necessary to overcome the limitation of the wavelength of the light source by other methods. By utilizing the characteristics of the photoresist, the limitation of wavelength is overcome, and a smaller size than that obtainable by the minimum wavelength is realized.
How to overcome the problem that the minimum feature size is difficult to realize due to the limitation of wavelength in lithography, and further to improve the density and the integration level of the semiconductor device, needs to be solved.
[ Invention ]
The invention aims to provide a manufacturing method of a semiconductor structure, which can overcome the problem that the minimum feature size is difficult to realize smaller due to the limitation of wavelength in photoetching while reducing the number of masks, thereby improving the density and the integration level of a semiconductor device.
In order to solve the above problems, the present invention provides a method for fabricating a semiconductor structure, including: providing a substrate, forming a film layer to be etched on the substrate and a first dielectric layer on the film layer to be etched, wherein the first dielectric layer is formed into a plurality of independent first dielectric blocks arranged at intervals; performing silanization treatment on the surface of the first dielectric block to form a second dielectric layer around the first dielectric block; the second dielectric layer is chemically treated to form a third dielectric layer of a material different from the second dielectric.
Wherein the material of the first dielectric layer comprises a negative photoresist material, and before the substrate is provided, the method further comprises: the exposed portions are retained by a photolithographic process to form a first dielectric block.
Wherein the material of the first dielectric layer comprises a non-hydrophilic polymer, and further comprises, before providing the substrate: the exposed portions are retained by a negative development technique to form a first dielectric block.
Before the silanization treatment is performed on the surface of the first dielectric block, the method further comprises the following steps: and baking the first dielectric block.
Wherein after the chemical treatment is performed on the second dielectric layer to form the third dielectric layer, the method further comprises: removing the third dielectric layer on the upper surface of the first dielectric block to expose the upper surface of the first dielectric block; and removing the first dielectric block to expose the film layer to be etched under the first dielectric block, and forming a plurality of second dielectric blocks arranged at intervals by the residual third dielectric layer.
Wherein the section width of the second dielectric block is 10-80nm.
Wherein, the material of the second dielectric block comprises silicon oxide.
The removing the first dielectric block specifically includes: and removing the first dielectric block by plasma dry photoresist removal or/and wet etching.
The film layer to be etched comprises an upper hard mask layer, and after the second dielectric blocks are formed at a plurality of intervals, the film layer to be etched further comprises: forming a fourth dielectric layer on the second dielectric block, wherein the fourth dielectric layer covers the second dielectric block; removing the fourth dielectric layer and the second dielectric block on the upper surface of the second dielectric block and the hard mask layer to form a third dielectric block formed by the residual fourth dielectric layer originally positioned on the side surface of the second dielectric block; and etching the hard mask layer which is not covered by the third dielectric block to form an etching mask block with the rest hard mask layer and the third dielectric block.
Wherein, the material of the third dielectric block comprises titanium nitride.
Wherein the chemical treatment comprises an oxidation treatment.
Wherein the cross section width of the first dielectric block is 10-80nm.
The beneficial effects of the invention are as follows: different from the prior art, the manufacturing method of the semiconductor structure provided by the invention comprises the following steps: providing a substrate, forming a film layer to be etched on the substrate and a first dielectric layer on the film layer to be etched, wherein the first dielectric layer is formed into a plurality of independent first dielectric blocks arranged at intervals; performing silanization treatment on the surface of the first dielectric block to form a second dielectric layer around the first dielectric block; the second dielectric layer is chemically treated to form a third dielectric layer of a material different from the second dielectric. By the technology of the invention, the number of masks can be saved, the cost and the production period can be reduced, and the quadruple patterning can be realized by a Self-aligned double patterning process (Self-aligned Double Patterning, SADP) to obtain a size smaller than the size obtained by the minimum wavelength.
[ Description of the drawings ]
FIG. 1 is a structural flow diagram of a prior art LFLFLFLE preparation process;
FIG. 2 is a structural flow diagram of a prior art SAQP preparation process;
FIG. 3 is a flow chart of a method for fabricating a semiconductor structure according to an embodiment of the invention;
FIG. 4 is a schematic diagram of a structure of a substrate according to an embodiment of the present invention;
FIG. 5 is a schematic diagram illustrating a structure of forming a second dielectric layer according to an embodiment of the present invention;
FIG. 6 is a schematic diagram illustrating a structure of forming a third dielectric layer according to an embodiment of the present invention;
FIG. 7 is a schematic diagram illustrating a structure of forming a second dielectric block according to an embodiment of the present invention;
FIG. 8 is a flow chart of a method for fabricating a semiconductor structure according to another embodiment of the present invention;
FIG. 9 is a schematic diagram illustrating a structure of forming a fourth dielectric layer according to another embodiment of the present invention;
FIG. 10 is a schematic diagram illustrating a structure of removing the top fourth dielectric layer according to another embodiment of the present invention;
FIG. 11 is a schematic diagram illustrating a structure for removing a second dielectric block according to another embodiment of the present invention;
FIG. 12 is a schematic diagram of a structure for forming an etching mask block according to another embodiment of the present invention;
[ detailed description ] of the invention
The invention is described in further detail below with reference to the drawings and examples. It is specifically noted that the following examples are only for illustrating the present invention, but do not limit the scope of the present invention. Likewise, the following examples are only some, but not all, of the examples of the present invention, and all other examples, which a person of ordinary skill in the art would obtain without making any inventive effort, are within the scope of the present invention.
In addition, directional terms such as [ upper ], [ lower ], [ front ], [ rear ], [ left ], [ right ], [ inner ], [ outer ], [ side ], etc., as used herein, refer only to the directions of the attached drawings. Accordingly, directional terminology is used to describe and understand the invention and is not limiting of the invention. In the various drawings, like elements are designated by like reference numerals. For clarity, the various features of the drawings are not drawn to scale. Furthermore, some well-known portions may not be shown in the drawings.
The quad patterning technique can overcome the wavelength limitation and achieve smaller dimensions than those achievable with the smallest wavelength, and existing quad patterning techniques include LFLFLFLE (Litho-Freeze-Litho-Freeze-Litho-Freeze-Litho-Etch lithography-Freeze-lithography-etching) and SAQP (Self-aligned quadruple PATTERNI NG Self-aligned quad pattern).
Wherein LFLFLFLE (Litho-Freeze-Litho-Freeze-Litho-Freeze-Litho-Etch lithography-Freeze-lithography-Etch) generally comprises the steps of:
S1: referring to fig. 1 (a), a first dielectric block 230 is formed on a film layer 210 to be etched and a hard mask layer 220 by a photolithography process;
s2: referring to fig. 1 (b), the first dielectric block 230 is converted into the first dielectric block 240 by a freezing method, and the materials of the first dielectric block 240 and the first dielectric block 230 are different, so that the first dielectric block 240 is not deformed by the subsequent photolithography process;
S3: referring to fig. 1 (c), a second dielectric block 250 is formed beside the first dielectric block 240 through a photolithography process;
S4: referring to fig. 1 (d), the second dielectric block 250 is converted into a second dielectric block 260 by a freezing method, and the second dielectric block 260 and the second dielectric block 250 are made of different materials, so that the second dielectric block 260 is not deformed by the subsequent photolithography process;
S5: referring to fig. 1 (e), a third dielectric block 270 is formed beside the second dielectric block 260 through a photolithography process;
S6: referring to fig. 1 (f), the third dielectric block 270 is converted into a third dielectric block 280 by a freezing method, and the third dielectric block 280 and the third dielectric block 270 are made of different materials, so that the third dielectric block 280 is not deformed by the subsequent photolithography process;
s7: referring to fig. 1 (g), a fourth dielectric block 290 is formed beside the third dielectric block 280 through a photolithography process;
S8: referring to fig. 1 (h), the hard mask layer 220 uncovered by the first, second, third and fourth dielectric blocks 240, 260, 280 and 290 is removed by an etching process, and the remaining hard mask layer 220 is formed into a plurality of fifth dielectric blocks 221 disposed at intervals.
Wherein SAQP (Self-aligned quadruple Patterning Self-aligned quad pattern) generally comprises the steps of:
s1: referring to fig. 2 (a), a first dielectric block 340 is formed on the film layer 310 to be etched, the first hard mask layer 320 and the second hard mask layer 330 by a photolithography process;
S2: referring to fig. 2 (b), the second hard mask layer 330 uncovered by the first dielectric block 340 is removed by an etching process, the remaining second hard mask layer 330 is formed into a second dielectric block 331, and then the first dielectric block 340 is removed by a dry photoresist removal or a wet photoresist removal process;
s3: referring to fig. 2 (c), a first dielectric layer 350 is formed on the second dielectric block 331 by a deposition process, and the first dielectric layer completely covers the second dielectric block 331;
S4: referring to fig. 2 (d), a portion of the first dielectric layer 350 on the top of the second dielectric block 331 and the first hard mask layer 320 is removed to expose an upper surface of the second dielectric block 331, and then the second dielectric block 331 is removed, and the remaining first dielectric layer 350 forms a plurality of third dielectric blocks 351 disposed at intervals;
S5: referring to fig. 2 (e), a second dielectric layer 360 is formed on the third dielectric block 351 through a deposition process;
s6: referring to fig. 2 (f), a portion of the second dielectric layer 360 on the top of the third dielectric block 351 and the first hard mask layer 320 is removed to expose the upper surface of the third dielectric block 351, and then the third dielectric block 351 is removed, and the remaining second dielectric layer 360 forms a plurality of fourth dielectric blocks 361 disposed at intervals.
It follows that the quadruple patterning of LELFLFLE (Litho-Freeze-Litho-Freeze-Litho-Freeze-Litho-Etch lithography-Freeze-lithography-etching) requires four exposures, whereas one mask (mask) is required for one exposure, resulting in an increase in the number of masks and thus in an increase in cost. SAQP (Self-aligned quadruple Patterning Self-aligned quad pattern) can be understood as two SADP (Self-aligned Double Patterning Self-aligned double pattern) but this technique requires a relatively large number of process steps, resulting in an increased production cycle.
In view of this, as shown in fig. 3, the present invention provides a method for manufacturing a semiconductor structure, where the method is applied to the field of semiconductor technology, and the specific flow is compared with the structure diagrams of fig. 4 to 7, and may include the following steps:
s101, step: providing a substrate 110, forming a film layer 120 to be etched on the substrate 110 and a first dielectric layer 130 on the film layer 120 to be etched, wherein the first dielectric layer 130 is formed to have a plurality of independent first dielectric blocks 131 arranged at intervals.
Wherein the cross-section width of the first dielectric block in the step S101 is 10-80nm.
Specifically, when the material of the first dielectric block is a photoresist material, the first dielectric block 131 is formed by exposure, development, etc., however, the cross-sectional width of the first dielectric block 131 is limited by the wavelength of the light source of the exposure, while the deep ultraviolet light source (DUV) wavelength using an excimer laser is 193nm, the width of one peak or valley is likely to break through the diffraction limit in terms of light field distribution alone, but the characteristic of the photoresist can be utilized, the solubility after the photoresist exposure depends on the exposure amount, but this depends on the exposure amount nonlinearity, by controlling this nonlinearity such that a small point is not dissolved at all near a certain threshold exposure amount, a large point is easily dissolved, and by controlling the exposure amount, the line width of the minimum size can be controlled, thereby realizing the cross-sectional width of the first dielectric block 131 to be 10 to 80nm.
In particular, the method for fabricating the semiconductor structure according to the embodiments of the present invention will be described in detail with reference to fig. 4 to 7.
Fig. 4 shows the structure formed in step S101, including: the substrate 110, the film 120 to be etched and the first dielectric layer 130 on the film 120 to be etched are formed on the substrate 110, and the first dielectric layer 130 is formed to have a plurality of independent first dielectric blocks 131 arranged at intervals.
Specifically, the substrate 110 is a semiconductor material, which may be silicon (Si), germanium (Ge) or silicon germanium (GeSi), silicon carbide (SiC), or other materials, and may further include an active device or a passive device that is formed on the substrate 110, where the film 120 to be etched may be one or more layers formed of a metal or non-metal material, for example, silicon oxide (SiO 2) or silicon nitride (SiN), which is a common material, may be removed by dry etching or wet etching, the first dielectric layer 130 may be formed into a patterned dielectric layer by a photolithography process, and the size, shape, and size of the pattern may be defined according to the design of a mask, the patterned first dielectric layer 130 may be obtained by the photolithography process, and the first dielectric layer 130 may be formed into a plurality of independent first dielectric blocks 131 disposed at intervals.
Further, to obtain the structure of step S101, it may be obtained by a photolithographic process of a negative photoresist, or by a negative development technique of a non-hydrophilic polymer.
Wherein, when obtained by a photolithography process of a negative photoresist material, the material of the first dielectric layer 130 includes the negative photoresist material, the first dielectric layer 130 is formed to have a plurality of independent first dielectric blocks 131 arranged at intervals, and the forming step includes:
the exposed portion is left by a photolithography process to form the first dielectric block 131.
Specifically, the first dielectric layer 130 may be a photoresist material, wherein the photoresist material includes a negative photoresist material and a positive photoresist material, the positive photoresist material is removed after exposure, the unexposed portion is preserved, and the negative photoresist material is preserved after exposure, and the unexposed portion is removed. When the first dielectric layer 130 is a negative photoresist material, the unexposed portion is removed by exposure, development, etc., and the exposed portion is left to form an independent first dielectric block 131 having a plurality of spaced arrangement, so that the exposed first dielectric block 131 can be directly subjected to a silylation process, thereby saving exposure steps, saving costs, and reducing a production period.
Wherein the material of the first dielectric layer 130 comprises a non-hydrophilic polymer when obtained by a negative development technique of the non-hydrophilic polymer, the first dielectric layer 130 is formed to have a plurality of separate first dielectric blocks 131 arranged at intervals, the forming step comprising:
the exposed portions are left by a negative development technique to form the first dielectric block 131.
In particular, most photoresists used for photolithography are generally positive photoresists, however, as semiconductor process nodes continue to shrink, printing small features such as small-sized trenches and vias with alkaline aqueous developer has become more challenging using conventional positive photoresists because of the poor optical image contrast of dark field masks used to create the trenches and vias, the concept of negative development (negative tone develop, NTD) has been proposed, i.e., using positive photoresist exposure, negative developer (instead of standard TMAH aqueous solution) to achieve the same effect as negative photoresist development to achieve narrower trenches. Preferably, the material of the first dielectric layer 130 is a non-hydrophilic polymer (hydrophobic polymer), and before exposure, the material is soluble in an organic solvent (NTD developer), but not soluble in an alkaline solution (TMAH developer), and after exposure, the photochemical reaction is excited to generate an acid, the polarity of the polymer after baking is changed to become a hydrophilic polymer (hydrophilic polymer), and the polymer is not soluble in the NTD developer, but soluble in the alkaline solution, and the exposed part is retained by adopting a negative development technology (NTD) to form the first dielectric blocks 131, and by adopting the negative development technology, the gaps between the first dielectric blocks 131 are smaller to be suitable for forming smaller feature sizes, and meanwhile, the formed first dielectric blocks 131 are the retained part after exposure, and can be directly subjected to silanization treatment, so that the exposure step is saved, the cost is saved, and the production period is reduced.
S102, step: the surface of the first dielectric block 131 is subjected to a silylation process to form a second dielectric layer around the first dielectric block 131.
Fig. 5 shows the structure formed in step S102, including: the substrate 110, the film 120 to be etched and the first dielectric layer 130 on the film 120 to be etched are formed on the substrate 110, the first dielectric layer 130 is formed to have a plurality of independent first dielectric blocks 131 arranged at intervals, and the second dielectric layer 140 is formed around the first dielectric blocks 131, wherein the second dielectric layer 140 is formed by performing silanization treatment on the surface of the first dielectric blocks 131.
Specifically, the silanization is a process of carrying out surface treatment on a metal or nonmetal material by taking an organic silane aqueous solution as a main component, and the silane treatment process does not generate sediment, and has the advantages of short treatment time and simple and convenient control. The material of the first dielectric block 131 is a photoresist material, the photoresist material includes a resin, the resin includes a hydroxyl functional group, a carboxylic acid functional group, an amine functional group or a thiol functional group, and when a subsequent silylation process is performed, a hydrogen element in the functional group is replaced by a silane group, so as to form a silylated layer, that is, the second dielectric layer 140. The second dielectric layer 140 is directly formed on the surface of the exposed first dielectric block 131 by a silanization technology, while the prior art obtains a structure of forming the second dielectric layer 140 on the first dielectric block 131, a hard mask layer is required to be deposited, a photoresist layer is coated on the hard mask layer, the photoresist is patterned into small blocks arranged at intervals through procedures such as exposure and development, the hard mask layer is etched into small blocks arranged at intervals, and finally a thin film is deposited on the small blocks. At the same time, by controlling the permeation of the silylating agent, the thickness of the membrane layer of the silylated layer can be controlled, that is, the thickness of the second dielectric layer 140 can be controlled, and finally, different feature sizes can be obtained.
Preferably, before step S102, a baking process is further performed on the first dielectric block.
Specifically, a baking process (rake) is performed on the exposed first dielectric block, so that the developer remained after the development is evaporated, and after the curing and development are completed, a plurality of independent first dielectric blocks 131 arranged at intervals are formed, so as to prepare for the subsequent silanization treatment on the surface of the first dielectric blocks 131.
S103, step: the second dielectric layer 140 is chemically treated to form a third dielectric layer of a material different from the second dielectric.
Fig. 6 shows the structure formed in step S103, comprising: the substrate 110, the film 120 to be etched and the first dielectric layer 130 on the film 120 to be etched are formed on the substrate 110, the first dielectric layer 130 is formed to have a plurality of independent first dielectric blocks 131 arranged at intervals, the second dielectric layer 140 is formed around the first dielectric blocks 131, the second dielectric layer 140 is chemically treated to form the third dielectric layer 150, wherein the second dielectric layer 140 is chemically reacted to form the third dielectric layer 150, the second dielectric layer 140 is a silylated layer formed by silylation of a photoresist material, the third dielectric layer 150 is obtained by chemically treating the second dielectric layer 140, for example, when the silylated layer is oxidized, the third dielectric layer 150 is a silicon oxide (SiO 2) layer, and obviously, the second dielectric layer 140 and the third dielectric layer 150 are not the same material.
Wherein the chemical treatment in step S103 includes: and (5) oxidizing treatment.
Specifically, the oxidation treatment is an oxygen-containing plasma oxidation treatment, the second dielectric layer 140 is a silylated layer, and carbon element and hydrogen element in the silylated layer are removed by performing oxidation treatment on the silylated layer, so that the remaining oxygen element and silicon element in the silylated layer are crosslinked to form a silicon oxide (SiO 2) layer, that is, the third dielectric layer 150, wherein the silicon oxide (SiO 2) layer formed after the oxidation treatment has higher compactness and hardness than the silylated layer, can maintain a stable morphology, is not easy to deform or collapse when the first dielectric block 131 is subsequently removed, converts the silylated layer into the silicon oxide (SiO 2) layer, and avoids the problems that if the third dielectric layer 150 is a silylated layer which is not oxidized to form the silicon oxide (SiO 2) layer, the second dielectric block 151 is easy to deform after the second dielectric block 151 is formed on top of the third dielectric layer 150 is removed, the morphology of the second dielectric block 151 is unstable, and the depth of a groove on two sides of the second dielectric block 151 is not uniform after the subsequent etching.
Wherein, after step S103, further comprising:
S104, step: the third dielectric layer 150 on the upper surface of the first dielectric block 131 is removed to expose the upper surface of the first dielectric block 131.
Specifically, an anisotropic dry etching process may be used to remove the third dielectric layer 150 on the first dielectric block 131, for example, when the material of the third dielectric layer 150 is silicon oxide (SiO 2), the etching gas used may be carbon tetrafluoride (CF 4) and oxygen (O2), and the reaction is stopped by the anisotropic dry etching when the reaction time reaches a certain set value or when the thickness of the etched film reaches a certain set value, so that the removal of the third dielectric layer 150 on the upper surface of the first dielectric block 131 is precisely controlled to expose the upper surface of the first dielectric block 131 without damaging the remaining third dielectric layer 150 and other film layers that are needed to remain on the side surface of the second dielectric block 151.
S105, step: the first dielectric block 131 is removed to expose the film 120 to be etched under the first dielectric block 131, and the remaining third dielectric layer 150 forms a plurality of second dielectric blocks 151 disposed at intervals.
Wherein the cross-sectional width of the second dielectric block 151 in step S105 is 10-80nm.
Wherein the material of the second dielectric block 151 in step S105 includes silicon oxide.
Specifically, by removing the first dielectric block 131 to expose the film 120 to be etched under the first dielectric block 131, the remaining third dielectric layer 150 forms a plurality of second dielectric blocks 151 disposed at intervals, that is, the third dielectric layer 150 includes a plurality of second dielectric blocks 151 disposed at intervals, and the second dielectric blocks 151 are completely consistent with the material of the third dielectric layer 150, as can be seen from the above, the material of the third dielectric layer 150 may be a silicon oxide (SiO 2) layer, so the material of the second dielectric blocks 151 may be silicon oxide (SiO 2).
In step S105, the removing the first dielectric block 131 specifically includes:
the first dielectric block 131 is removed by plasma dry photoresist removal or/and wet etching.
Specifically, the first dielectric block 131 is removed by plasma dry photoresist removal or/and wet etching, the plasma dry photoresist removal is performed in vacuum by utilizing the reaction of active oxidation groups in plasma with photoresist to generate carbon dioxide and water, the plasma dry photoresist removal has high precision, the cleaning surface is not polluted by secondary pollution, or the wet etching is performed by adopting a chemical solution with a certain selection ratio, the etching rate of the solution on the first dielectric block 131 (photoresist material) is very high, the etching rate on other film layers is very low, other film layers are not damaged basically when the first dielectric block 131 is removed, for example, the main components C, H in the photoresist are oxidized to form CO2 and H2O by utilizing the strong oxidability of sulfuric acid (H2 SO 4) and hydrogen peroxide (H2O 2), SO that the photoresist is removed. In order to thoroughly remove the first dielectric block 131 and avoid the defects such as defects caused by the residue of the first dielectric to the influence of the subsequent process, preferably, the first dielectric block 131 can be thoroughly removed by combining plasma dry photoresist removal and wet etching or by using plasma dry photoresist removal or wet etching multiple times, so as to expose the film layer 120 to be etched under the first dielectric block 131, and the remaining third dielectric layer 150 forms a plurality of second dielectric blocks 151 arranged at intervals.
Fig. 7 shows the structure formed after steps S104 and S105, including: the substrate 110, the film 120 to be etched is formed on the substrate 110, and a plurality of second dielectric blocks 151 disposed at intervals are formed on the film 120 to be etched.
The above steps are a first embodiment of the present invention, and according to another embodiment of the present invention, the above process may be applied to SADP (Self-aligned double pattern of Self-aligned Double Patterning) to further reduce the feature size, and as shown in fig. 8, a flowchart of another embodiment of the present invention is shown, and the specific flowchart may include the following steps compared to the block diagrams of fig. 9 to 12:
Wherein, the film layer 120 to be etched includes an upper hard mask layer 122, and after step S105, further includes:
S106, step: a fourth dielectric layer 160 is formed on the second dielectric block 151, the fourth dielectric layer 160 covering the second dielectric block 151.
The film layer 120 to be etched may include a patterned layer 121 to be etched and a hard mask layer 122 on the patterned layer 121.
Specifically, when etching the patterned layer 121, a Hard Mask layer 122 may be disposed on the patterned layer 121 to protect the portions of the patterned layer 121 that do not need to be etched from being damaged, and a Hard Mask (Hard Mask) is an inorganic thin film material formed by chemical vapor deposition (Chemical Vapor Deposition, CVD) and generally comprises titanium nitride (TiN), silicon nitride (SiN), silicon oxide (SiO 2), etc. as main components, and is mainly used in a photolithography process, and pattern etching is transferred to the patterned layer 121 through transferring a pattern of photoresist to the Hard Mask layer 122 and then through the Hard Mask layer 122. Due to the optical reflection effect of the surface of the substrate 110, the reflected light and the incident light interfere with each other, forming a standing wave effect and multiple exposures inside the photoresist, resulting in uncontrollable critical dimensions of the pattern, reducing etching accuracy, preferably, a bottom anti-reflective layer (BARC) whose main components are crosslinkable resin, thermal acid generator, surfactant and solvent may be added between the photoresist layer and the hard mask layer 122, reducing reflection, effectively improving standing wave effect and multiple exposures, etc.
Fig. 9 shows the structure formed after step S106, comprising: the substrate 110 includes a patterned layer 121, a hard mask layer 122, a plurality of second dielectric blocks 151 spaced apart from each other, and a fourth dielectric layer 160 formed on the second dielectric blocks 151 in this order on the substrate 110.
Specifically, a deposition process may be used to form the fourth dielectric layer 160 on the second dielectric block 151, a metal layer or a non-metal layer may be deposited on the second dielectric block 151, a material of the fourth dielectric layer 160 may be titanium nitride (TiN) or tantalum nitride (TaN), etc., and a deposition process may be Physical Vapor Deposition (PVD), chemical Vapor Deposition (CVD) or Atomic Layer Deposition (ALD), and in order to achieve compactness and uniformity of the deposited film layer, preferably, an Atomic Layer Deposition (ALD) may be used to deposit a titanium nitride (TiN) film on the second dielectric block 151 to form the fourth dielectric layer 160.
S107, step: the fourth dielectric layer 160 on the upper surface of the second dielectric block 151 and on the hard mask layer 122 and the second dielectric block 151 are removed, and a third dielectric block 161 formed of the remaining fourth dielectric layer 160 originally located on the side surface of the second dielectric block 151 is formed.
Wherein the material of the third dielectric block 161 in step S107 includes titanium nitride.
Specifically, the third dielectric block 161 formed of the remaining fourth dielectric layer 160, which is originally located on the side surface of the second dielectric block 151, is formed by removing the fourth dielectric layer 160 and the second dielectric block 151 on the upper surface of the second dielectric block 151 and on the hard mask layer 122, that is, the remaining fourth dielectric layer 160 forms the third dielectric block 161, and the material of the third dielectric block 161 and the material of the fourth dielectric layer 160 are completely identical, and as apparent from the above, the fourth dielectric layer 160 may be formed by atomic layer deposition of titanium nitride (TiN), so the material of the third dielectric block may be titanium nitride (TiN).
Fig. 10 shows a structure formed after removing the fourth dielectric layer 160 on the upper surface of the second dielectric block 151 and on the hard mask layer 122 in step S107, including: the substrate 110, the substrate 110 has a patterned layer 121, a hard mask layer 122, a plurality of second dielectric blocks 151 disposed at intervals, and third dielectric blocks 161 formed of a remaining fourth dielectric layer 160 on both sides of the plurality of second dielectric blocks 151 in this order.
Specifically, the fourth dielectric layer 160 and the fourth dielectric layer 160 on the hard mask layer 122 may be removed by anisotropic dry etching, and the top fourth dielectric layer 160 may be selectively etched away, while the fourth dielectric layer 160 on both sides of the second dielectric block 151 remains.
Fig. 11 shows a structure formed after the second dielectric block 151 is removed in step S107, including: the substrate 110, the patterned layer 121 as the film layer 120 to be etched, the hard mask layer 122 on the patterned layer 121, and the third dielectric block 161 formed of the remaining fourth dielectric layer 160 are formed on the substrate 110.
Specifically, the second dielectric block 151 may be removed by anisotropic dry etching, where the material of the second dielectric block 151 is silicon oxide (SiO 2), and the material of the fourth dielectric layer 160 is titanium nitride (TiN) or tantalum nitride (TaN) which is different from the material of the second dielectric block 151, and the silicon oxide (SiO 2) has a higher etching selectivity to titanium nitride (TiN) or tantalum nitride (TaN) so as to remove the second dielectric block 151 without damaging other film layers.
S108, step: the hard mask layer 122 not covered by the third dielectric block 161 is etched such that the remaining hard mask layer 122 and the third dielectric block 161 form an etch mask block 170.
Fig. 12 shows a structure formed in step S110, including: the substrate 110, and the etch mask block 170 are formed from the remaining hard mask layer 122 and the third dielectric block 161, wherein the etch mask block 170 includes the third dielectric block 161 and etches the hard mask layer 122 that is not covered by the third dielectric block 161 and remains.
Specifically, the hard mask layer 122 not covered by the third dielectric block 161 may be removed by an anisotropic dry etching, and the etching gas may be carbon tetrafluoride (CF 4), trifluoromethane (CHF 3) and oxygen (O2), so that the remaining hard mask layer 122 and the third dielectric block 161 form an etching mask block 170.
Unlike the prior art, the method for fabricating the semiconductor structure in this embodiment includes: providing a substrate, forming a film layer to be etched on the substrate and a first dielectric layer on the film layer to be etched, wherein the first dielectric layer is formed into a plurality of independent first dielectric blocks arranged at intervals; performing silanization treatment on the surface of the first dielectric block to form a second dielectric layer around the first dielectric block; the second dielectric layer is chemically treated to form a third dielectric layer of a material different from the second dielectric. The manufacturing method of the semiconductor structure is provided, and the result of quadruple patterning can be achieved only by one-time photoetching, so that the method can be applied to process nodes with critical dimensions of 5nm or smaller, the number of masks is saved, and the cost and the production period are saved.
The foregoing description of the preferred embodiments of the invention is not intended to be limiting, but rather is intended to cover all modifications, equivalents, and alternatives falling within the spirit and principles of the invention.
Claims (10)
1. A method of fabricating a semiconductor structure, comprising:
Providing a substrate, wherein a film layer to be etched and a first dielectric layer on the film layer to be etched are formed on the substrate, the film layer to be etched comprises an upper hard mask layer, and the first dielectric layer is formed to be provided with a plurality of independent first dielectric blocks arranged at intervals;
performing silanization treatment on the surface of the first dielectric block to form a second dielectric layer around the first dielectric block;
performing chemical treatment on the second dielectric layer to form a third dielectric layer with a material different from that of the second dielectric;
removing the third dielectric layer on the upper surface of the first dielectric block to expose the upper surface of the first dielectric block;
removing the first dielectric block to expose the film layer to be etched under the first dielectric block, and forming a plurality of second dielectric blocks arranged at intervals by the rest of the third dielectric layer;
Depositing a fourth dielectric layer on the second dielectric block, wherein the fourth dielectric layer covers the second dielectric block;
removing the fourth dielectric layer and the second dielectric block on the upper surface of the second dielectric block and the hard mask layer to form a third dielectric block formed by the remaining fourth dielectric layer originally positioned on the side surface of the second dielectric block;
And etching the hard mask layer which is not covered by the third dielectric block to enable the residual hard mask layer and the third dielectric block to form an etching mask block.
2. The method of fabricating a semiconductor structure as recited in claim 1, wherein the material of the first dielectric layer comprises a negative photoresist material, and further comprising, prior to said providing the substrate:
the exposed portion is left by a photolithography process to form the first dielectric block.
3. The method of fabricating a semiconductor structure as recited in claim 1, wherein the material of the first dielectric layer comprises a non-hydrophilic polymer, and further comprising, prior to said providing the substrate:
the exposed portions are retained by a negative development technique to form the first dielectric block.
4. The method of fabricating a semiconductor structure according to claim 1, further comprising, prior to said silylating the surface of the first dielectric block:
and baking the first dielectric block.
5. The method of fabricating a semiconductor structure of claim 1, wherein a cross-sectional width of the second dielectric block is 10-80nm.
6. The method of fabricating a semiconductor structure of claim 1, wherein the material of the second dielectric block comprises silicon oxide.
7. The method of fabricating a semiconductor structure of claim 1, wherein said removing said first dielectric block comprises:
And removing the first dielectric block by plasma dry photoresist removal or/and wet etching.
8. The method of fabricating a semiconductor structure of claim 1, wherein the material of the third dielectric block comprises titanium nitride.
9. The method of fabricating a semiconductor structure of claim 1, wherein the chemical treatment comprises an oxidation treatment.
10. The method of fabricating a semiconductor structure of claim 1, wherein a cross-sectional width of the first dielectric block is between 10nm and 80nm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011544162.3A CN112670175B (en) | 2020-12-24 | 2020-12-24 | Method for manufacturing semiconductor structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011544162.3A CN112670175B (en) | 2020-12-24 | 2020-12-24 | Method for manufacturing semiconductor structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN112670175A CN112670175A (en) | 2021-04-16 |
| CN112670175B true CN112670175B (en) | 2024-05-03 |
Family
ID=75409602
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202011544162.3A Active CN112670175B (en) | 2020-12-24 | 2020-12-24 | Method for manufacturing semiconductor structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112670175B (en) |
Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20050002489A (en) * | 2003-06-30 | 2005-01-07 | 주식회사 하이닉스반도체 | Method for forming fine pattern of semiconductor device using polymer and dual silylation |
| CN1619774A (en) * | 2003-11-19 | 2005-05-25 | 旺宏电子股份有限公司 | Semi conductor element having reduced spacing and its forming method |
| JP2010066597A (en) * | 2008-09-11 | 2010-03-25 | Shin-Etsu Chemical Co Ltd | Pattern forming method |
| CN104347371A (en) * | 2013-07-24 | 2015-02-11 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure formation method |
| CN104516138A (en) * | 2013-09-29 | 2015-04-15 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of silicon based liquid crystal panel |
| CN107210196A (en) * | 2015-02-09 | 2017-09-26 | 应用材料公司 | The selective lateral growth of silicon oxide film |
| CN109411337A (en) * | 2017-08-16 | 2019-03-01 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor devices and forming method thereof |
| CN109950140A (en) * | 2019-04-18 | 2019-06-28 | 上海华力微电子有限公司 | A kind of forming method of autoregistration bilayer figure |
| CN110676157A (en) * | 2019-09-18 | 2020-01-10 | 天津大学 | Optimization of self-aligned quad technology process design using oxide and TiN |
| CN111863602A (en) * | 2019-04-30 | 2020-10-30 | 芯恩（青岛）集成电路有限公司 | Preparation method of self-aligned pattern structure |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7253113B2 (en) * | 2003-11-13 | 2007-08-07 | Macronix International Co., Ltd. | Methods for using a silylation technique to reduce cell pitch in semiconductor devices |
| US10002762B2 (en) * | 2016-09-09 | 2018-06-19 | International Business Machines Corporation | Multi-angled deposition and masking for custom spacer trim and selected spacer removal |
| CN109494149B (en) * | 2017-09-13 | 2020-10-23 | 联华电子股份有限公司 | Method for manufacturing semiconductor structure |
| CN110739210B (en) * | 2018-07-18 | 2022-04-12 | 中芯国际集成电路制造(北京)有限公司 | Semiconductor structure and forming method thereof |
-
2020
- 2020-12-24 CN CN202011544162.3A patent/CN112670175B/en active Active
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20050002489A (en) * | 2003-06-30 | 2005-01-07 | 주식회사 하이닉스반도체 | Method for forming fine pattern of semiconductor device using polymer and dual silylation |
| CN1619774A (en) * | 2003-11-19 | 2005-05-25 | 旺宏电子股份有限公司 | Semi conductor element having reduced spacing and its forming method |
| JP2010066597A (en) * | 2008-09-11 | 2010-03-25 | Shin-Etsu Chemical Co Ltd | Pattern forming method |
| CN104347371A (en) * | 2013-07-24 | 2015-02-11 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure formation method |
| CN104516138A (en) * | 2013-09-29 | 2015-04-15 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of silicon based liquid crystal panel |
| CN107210196A (en) * | 2015-02-09 | 2017-09-26 | 应用材料公司 | The selective lateral growth of silicon oxide film |
| CN109411337A (en) * | 2017-08-16 | 2019-03-01 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor devices and forming method thereof |
| CN109950140A (en) * | 2019-04-18 | 2019-06-28 | 上海华力微电子有限公司 | A kind of forming method of autoregistration bilayer figure |
| CN111863602A (en) * | 2019-04-30 | 2020-10-30 | 芯恩（青岛）集成电路有限公司 | Preparation method of self-aligned pattern structure |
| CN110676157A (en) * | 2019-09-18 | 2020-01-10 | 天津大学 | Optimization of self-aligned quad technology process design using oxide and TiN |
Also Published As
| Publication number | Publication date |
|---|---|
| CN112670175A (en) | 2021-04-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7354847B2 (en) | Method of trimming technology | |
| JP4890524B2 (en) | Lithographic pattern forming method | |
| KR100320163B1 (en) | Method for using a hardmask to form an opening in a semiconductor substrate | |
| TWI424469B (en) | Double patterning strategy for contact hole and trench | |
| JP3848070B2 (en) | Pattern formation method | |
| JP5290204B2 (en) | Fine pattern mask, method of manufacturing the same, and method of forming fine pattern using the same | |
| KR100876892B1 (en) | Method for manufacturing semiconductor device | |
| US20100176479A1 (en) | Method of fabricating a semiconductor device | |
| US8303831B2 (en) | Methods for fabricating semiconductor devices | |
| US7943521B2 (en) | Method for patterning a semiconductor device | |
| CN109950140B (en) | Method for forming self-aligned double-layer pattern | |
| JP5224919B2 (en) | Manufacturing method of semiconductor device | |
| US5922516A (en) | Bi-layer silylation process | |
| CN112670175B (en) | Method for manufacturing semiconductor structure | |
| US6551938B1 (en) | N2/H2 chemistry for dry development in top surface imaging technology | |
| KR100816210B1 (en) | Method of fabricating semiconductor devices | |
| CN112670168B (en) | Method for forming semiconductor structure and transistor | |
| CN112530793B (en) | Photoetching-freezing-photoetching-etching double patterning method | |
| JP2932462B1 (en) | Surface patterning method for semiconductor manufacturing | |
| KR19990065142A (en) | Method for forming vertical profile pattern of material layer containing silicon | |
| KR100366624B1 (en) | Method for manufacturing semiconductor device using anti-reflective coating film | |
| JP2006041364A (en) | Wiring forming method, and electronic-device manufacturing method | |
| KR20080015378A (en) | Fabricating method of a semiconductor integrated circuit device | |
| KR20050064265A (en) | Method of patterning insulating layer for semiconductor device | |
| JP5275085B2 (en) | Manufacturing method of semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |