CN112668266A - Correction method of time sequence path - Google Patents
Correction method of time sequence path Download PDFInfo
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- CN112668266A CN112668266A CN202011541189.7A CN202011541189A CN112668266A CN 112668266 A CN112668266 A CN 112668266A CN 202011541189 A CN202011541189 A CN 202011541189A CN 112668266 A CN112668266 A CN 112668266A
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Abstract
A method for correcting a time sequence path comprises the following steps: determining a path and a unit of the timing violation; setting a search range and searching for an exchangeable unit; interchanging the time sequence violation units and the exchangeable units, evaluating new time sequence values of the two time sequence paths, and adding the exchangeable units which do not violate the time sequence and weight values thereof into a result set; and in the result set, selecting the exchangeable unit with the maximum weight value to exchange with the timing violation unit, and generating a result path. The correction method of the timing path can achieve the goal of timing optimization through unit interchange under the premise of not changing the physical layout of chip design and ensuring that the functional behavior of the chip is not changed, thereby enabling timing correction to be carried out at a post-mask stage in the later stage of design and ensuring the correctness of chip design.
Description
Technical Field
The present invention relates to the field of Electronic Design Automation (EDA) technology, and more particularly, to a method for correcting timing without changing interchange of layout cells.
Background
In the design of a digital integrated circuit, in order to ensure that a chip can work normally and reach a desired frequency, whether the time for a clock signal and a data signal to reach a register synchronization unit meets the constraints of setup time (setup time) and hold time (hold time) needs to be checked. If a violation in timing is found, an ECO modification is required to adjust the timing path.
Buffer cell insertion, cell size variation, large net splitting, etc. are commonly employed timing optimization methods. Aiming at a timing path with timing violation, the delay of the timing path is increased or decreased by a method of cell insertion or cell size change, so that the timing violation problem is corrected. However, a prerequisite for such timing optimization is that sufficient room must be left in the chip design to accommodate newly inserted cells or cells of increased size. At the later stage of chip design, especially when entering the post-mask stage, the physical place-and-route tool has inserted the Filler padding unit and Spare unit, and the cell row is already in the 100% occupied state, so that the above-mentioned ordinary timing optimization operation cannot be performed.
In the post-mask timing optimization, on the premise of not changing the physical layout, the Spare units reserved in the early stage are used, and the physical connection line of the metal layer is changed to realize the circuit structure change, so that the timing sequence is changed. However, when the number of Spare units is not enough, or the Spare units cannot be found within a predetermined range, the timing target cannot be optimized.
Disclosure of Invention
In order to solve the defects in the prior art, the invention aims to provide a timing path correction method, which can achieve the goal of timing optimization through unit interchange on the premise of not changing the physical layout of chip design and ensuring that the functional behavior of a chip is not changed, so that timing correction can be performed at a post-mask stage in the later stage of design, and the correctness of chip design is ensured.
In order to achieve the above object, the present invention provides a method for correcting a timing path, comprising the following steps:
determining a path and a unit of the timing violation;
setting a search range and searching for an exchangeable unit;
interchanging the time sequence violation units and the exchangeable units, evaluating new time sequence values of the two time sequence paths, and adding the exchangeable units which do not violate the time sequence and weight values thereof into a result set;
and in the result set, selecting the exchangeable unit with the maximum weight value to exchange with the timing violation unit, and generating a result path.
Further, the step of determining the timing violation path and the unit further includes determining the timing violation path, finding the timing violation unit for performing timing adjustment, and acquiring the unit type and the physical location.
Further, the step of setting a search range and finding exchangeable units further comprises,
and setting a distance range, and searching units with the same functions as the timing violation units but different driving capacities in the distance range by taking the timing violation units as centers.
Further, the method also comprises the step of judging whether the functions of the units are the same by comparing the keywords of the unit attributes.
Further, the step of setting the search range and searching for the exchangeable units further comprises the step of traversing all the found exchangeable units and screening and removing the units with insufficient timing sequence margin.
Further, the step of interchanging the timing violation unit and the exchangeable unit, evaluating new timing values of the two timing paths, and adding the exchangeable unit not violating the timing and the weight value thereof to the result set further includes calculating the weight value according to the physical position distance between the timing violation unit and the exchangeable unit and the variation of the timing values of the two timing paths.
Further, the step of selecting the exchangeable unit with the largest weight value in the result set to exchange with the timing violation unit to generate a result path further comprises exchanging the unit types and physical positions of the timing violation unit and the exchangeable unit, and outputting a result ECO script.
Further, the method also comprises the step of expanding the rotation of the units on the paths.
In order to achieve the above object, the present invention further provides an electronic device, which includes a memory and a processor, wherein the memory stores a computer program running on the processor, and the processor executes the steps of the method for correcting a timing path as described above when executing the computer program.
To achieve the above object, the present invention further provides a computer-readable storage medium having a computer program stored thereon, the computer program executing the steps of the method for correcting a timing path as described above.
The correction method of the time sequence path has the following beneficial effects:
1) when the chip design enters the post-mask later stage, the physical layout of the cell is not allowed to change, and common time sequence optimization operations such as buffer cell insertion, cell size change and the like cannot be performed. Timing problems can only be repaired by changing the wiring.
2) On the premise of not changing the positions and functions of the units, the timing sequence path is optimized through the interchange of the types and positions of the two units, and the normal work of the chip is ensured. The method can also be popularized to the rotation of a plurality of units.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.
Drawings
The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention. In the drawings:
FIG. 1 is a flow chart of a method for correcting a timing path according to the present invention;
FIG. 2 is a schematic diagram of a pick cell swap to optimize timing objectives according to an embodiment of the present invention;
FIG. 3 is a diagram illustrating a round-robin three unit optimization timing targets according to an embodiment of the invention.
Detailed Description
The preferred embodiments of the present invention will be described in conjunction with the accompanying drawings, and it will be understood that they are described herein for the purpose of illustration and explanation and not limitation.
Fig. 1 is a flowchart of a timing path correction method according to the present invention, and the timing path correction method of the present invention will be described in detail with reference to fig. 1.
First, in step 101, the path and cell for timing violation are determined.
Preferably, a timing path with a timing problem is determined, a unit needing timing adjustment is found, and the type of the unit and the physical position of the chip are obtained.
In this embodiment, it is assumed that the chip design enters the post-mask stage, and the physical layout of the cells is not allowed to be changed. Timing violations still exist on the timing path, and the goal of timing optimization is achieved by changing the timing units on the path.
In step 102, a search range is set for exchangeable cells that function the same as timing violating cells but have different drive capabilities.
Preferably, a distance range is set, and cells having the same function but different driving capability in the manhattan range are searched with the cells whose timing is violated as the center.
Preferably, whether the functions of the units are the same is judged by comparing the font attributes of the units.
In this embodiment, the font is defined in the lib library file, and is a key of the unit attribute, each unit has a corresponding font, and one font represents a group of units. The elements with the same footprint indicate the same function and can be used interchangeably.
Preferably, all the found exchangeable units are traversed, and the units with insufficient timing margin are screened out.
At step 103, an attempt is made to interchange swappable units with timing violation units, re-evaluate new timing values for the two timing paths, and if neither is violated, add weight values for swappable units and swappable units to the result set.
In step 104, in the result set, the exchangeable unit with the largest weight is selected to be exchanged with the timing violation unit, and an ECO script is output. In the step, the optimal scheme is selected through the weight value, the two unit types and the positions are exchanged, and a result ECO script is output.
Preferably, a rotation of the plurality of cells over the plurality of paths is extended.
In this embodiment, the timing violation problem existing on the timing path is corrected while keeping the physical layout of the cells unchanged.
The timing path correction method of the present invention is further described below with reference to an embodiment.
FIG. 2 is a schematic diagram of a pick cell swap to optimize timing objectives according to an embodiment of the invention.
In the stage of chip design post-mask, the layout of standard cells is fixed and cannot be changed, and important chip layers such as the M1 metal layer and the polysilicon layer cannot be changed. If a problem is found in the time sequence, a new unit cannot be inserted, the time sequence is adjusted and repaired by only changing the upper metal connecting wire, and the time sequence is corrected by using unit exchange on the premise of not changing the physical layout.
1) And determining a timing path pathA with a timing problem, and finding a cell CellA needing timing adjustment, wherein the cell type is TypeA, and the physical position of the chip is (xa, ya).
2) And in the specified range of the chip, unit screening and matching are carried out, and unit exchange is selected to optimize a time sequence target. As shown in FIG. 2, a user specifies a distance range dist, and uses cell CellA as the center to search for cells with the same function but different driving capability within the Manhattan range of { | x-xa | < dist, | y-ya | < dist }. Whether the functions of the units are the same can be judged by comparing the font attributes of the units.
3) And sequentially traversing the found units with the same functions, and checking whether a timing margin exists on a timing path where the unit is located (a unit timing slack value needs to be larger than 0, the slack is a timing margin value on the timing path, and the slack <0 indicates that a timing violation exists on the timing path).
4) For the cell CellB with timing margin, assuming that it is on the timing path PathB, its cell type is TypeB, and the physical position of the chip is (xb, yb), an attempt is made to change CellA TypeB, (xb, yb); CellB type A, (xa, ya). And recalculating the timing values of the timing paths PathA and PathB, and if any one timing path has a timing violation, indicating that the attempted exchange is unsuccessful. If no timing violation occurs in both timing paths, the attempt is successful, it is taken as an alternative, and the weight value is recorded:
WeightB＝w1*dist/(|xa-xb|+|ya-yb|)+w2*(|SlackA|+|SlackB|)
w1 and w2 are weight coefficients, w1 represents the influence of the physical positions of two units, and w2 represents the influence of the change of the timing values of two timing paths.
In this embodiment, the physical distance between the two units and the time sequence change of the two time sequence paths are comprehensively considered by using the weight value.
5) And traversing all the alternative schemes, finding the scheme with the maximum weight value as an optimal scheme, and exchanging the two units to realize the correction of the time sequence.
In this embodiment, examples of the Algorithm unit interchange optimization timing code include:
input, vision path and vision CellA, distance range dist parameter
Output Unit interchange script
1, foreach unit B: within dist range by taking vision cell as center, and the functions are the same
If CellB timing margin <0then
3:continue；
4:else
Attempt to change CellA TypeB, (xb, yb); CellB type A, (xa, ya)
6:if newSlackA<0or newSlackB<0then
7:continue；
8:else
9:weightB＝w1*dist/(|xa-xb|+|ya-yb|)+w2*(|SlackA|+|SlackB|)
10 Add CellB to the result set
10:endif
11:endif
12:endif
And 13, traversing the result set, selecting the unit with the maximum weight, exchanging with CellA, and outputting an ECO script.
In this embodiment, if the two units cannot correct the timing, the units on the timing paths may be rotated. As shown in fig. 3, three units are swapped in turn to optimize timing objectives: a < - > B, B < - > C, C < - > A. When multiple unit rotation is performed, it is necessary to ensure that a plurality of timing paths are behind the switching unit, and the timing value must not be in a timing violation condition.
The invention provides a method for correcting time sequence without changing layout unit interchange in the time sequence ECO process, which only changes the metal connecting wire of the upper layer and performs time sequence ECO optimization through unit interchange to achieve the aim of time sequence optimization on the premise of not changing the chip design physical layout and ensuring that the chip function behavior is not changed, thereby also performing time sequence correction in a post-mask stage of design and ensuring the correctness of chip design.
In an embodiment of the present invention, there is also provided an electronic device, including a memory and a processor, where the memory stores a computer program running on the processor, and the processor executes the computer program to perform the steps of the method for correcting a timing path as described above.
In an embodiment of the present invention, a computer-readable storage medium is also provided, on which a computer program is stored, which when running executes the steps of the method for correcting a timing path as described above.
Those of ordinary skill in the art will understand that: although the present invention has been described in detail with reference to the foregoing embodiments, it will be apparent to those skilled in the art that changes may be made in the embodiments and/or equivalents thereof without departing from the spirit and scope of the invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (10)
1. A method for correcting a timing path is characterized by comprising the following steps:
determining a path and a unit of the timing violation;
setting a search range and searching for an exchangeable unit;
interchanging the time sequence violation units and the exchangeable units, evaluating new time sequence values of the two time sequence paths, and adding the exchangeable units which do not violate the time sequence and weight values thereof into a result set;
and in the result set, selecting the exchangeable unit with the maximum weight value to exchange with the timing violation unit, and generating a result path.
2. The method according to claim 1, wherein the step of determining the path and the cell for timing violation further comprises determining the timing path for timing violation, finding the timing violation cell for timing adjustment, and obtaining the cell type and the physical location.
3. The method according to claim 1, wherein the step of setting a search range and finding exchangeable units further comprises,
and setting a distance range, and searching units with the same functions as the timing violation units but different driving capacities in the distance range by taking the timing violation units as centers.
4. The method according to claim 3, further comprising determining whether the functions of the cells are the same by comparing keywords of the cell attributes.
5. The method for correcting a timing path according to claim 1, wherein the step of setting a search range and finding exchangeable units further comprises, traversing all the found exchangeable units, and filtering out units with insufficient timing margin.
6. The method according to claim 1, wherein the steps of interchanging the timing violation units and the exchangeable units, evaluating new timing values of the two timing paths, and adding the exchangeable units that do not violate timing and their weight values to the result set further comprise calculating the weight values based on a physical position distance between the timing violation units and the exchangeable units and a timing value change of the two timing paths.
7. The method for correcting a timing path according to claim 1, wherein the step of selecting an exchangeable unit having a largest weight value in the result set to interchange with the timing violation unit to generate a result path further comprises exchanging the unit types and physical positions of the timing violation unit and the exchangeable unit to output a result ECO script.
8. The method according to claim 1, further comprising expanding the rotation of the plurality of cells on the plurality of paths.
9. An electronic device, comprising a memory and a processor, wherein the memory stores a computer program running on the processor, and the processor executes the computer program to perform the steps of the method for correcting a timing path according to any one of claims 1 to 8.
10. A computer-readable storage medium, on which a computer program is stored, characterized in that the computer program executes the steps of the method for correcting a timing path according to any one of claims 1 to 8.
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| CN202011541189.7A CN112668266A (en) | 2020-12-23 | 2020-12-23 | Correction method of time sequence path |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113673191A (en) * | 2021-08-19 | 2021-11-19 | 深圳华大九天科技有限公司 | Timing correction method and apparatus, calculation apparatus, and storage medium |
| CN117150997A (en) * | 2023-09-07 | 2023-12-01 | 广州市粤港澳大湾区前沿创新技术研究院 | Method and device for correcting timing violations of integrated circuits, electronic equipment and storage medium |
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| JP2005084795A (en) * | 2003-09-05 | 2005-03-31 | Matsushita Electric Ind Co Ltd | Semiconductor integrated circuit correction device |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113673191A (en) * | 2021-08-19 | 2021-11-19 | 深圳华大九天科技有限公司 | Timing correction method and apparatus, calculation apparatus, and storage medium |
| CN113673191B (en) * | 2021-08-19 | 2022-04-12 | 深圳华大九天科技有限公司 | Timing correction method and apparatus, calculation apparatus, and storage medium |
| WO2023019954A1 (en) * | 2021-08-19 | 2023-02-23 | 深圳华大九天科技有限公司 | Timing correction method and apparatus, computing apparatus, and storage medium |
| CN117150997A (en) * | 2023-09-07 | 2023-12-01 | 广州市粤港澳大湾区前沿创新技术研究院 | Method and device for correcting timing violations of integrated circuits, electronic equipment and storage medium |
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