CN112653399A - Noise elimination device of digital audio power amplifier - Google Patents
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/26—Modifications of amplifiers to reduce influence of noise generated by amplifying elements
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
- H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
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Abstract
The invention belongs to the field of digital audio power amplifier systems, and particularly relates to a noise elimination device of a digital audio power amplifier. The delay circuit mainly comprises an integrator, a comparator, a controllable switch and a delay circuit. The integrator is formed by transconductance amplifier and external circuits C1, C2 and R1, and forms a positive feedback loop, and the output end V is connected with the output endOTAA triangular waveform is generated. The comparator compares the output signals of the amplifiers
The value of the supply voltage generates a continuous square wave. The controllable switch S controls whether the positive feedback loop works or not according to the opening and control signals of the circuit. The delay module designs delay time through an RC circuit, combines the requirements of a system on circuit frequency, and reasonably designs electricityThe values of resistors R1 and C1 cause the output of the amplifier to oscillate above and below the bias voltage. This has the advantage of allowing the system to enter normal operation immediately, reducing the start-up time and eliminating "clicking" noise.
Description
Technical Field
The invention belongs to the field of digital audio power amplifier systems, and particularly relates to a noise elimination device of a digital audio power amplifier.
Background
With the development of mobile devices and sound systems, audio power amplifiers are widely used. Although unfiltered digital audio power amplifiers have relatively good performance in terms of dynamic range and efficiency, the "clickly" noise has limited the use of digital audio power amplifiers in some devices. Thus, "clickly" noise cancellation techniques have become particularly important in digital audio power amplifiers. When the whole circuit system is turned off, the transconductance amplifier has offset, so that the integrating capacitor is charged to the highest level, and when the whole circuit system is turned on, the integrating capacitor is discharged for a long time. In addition, digital audio power amplifiers often use closed loops to improve the performance of the amplifier, so that the feedback signal is superimposed with the input signal, sometimes saturating the integrator output signal, thereby disabling the pulse modulator, the output signal is always at a high level or a low level, and after a plurality of cycles, the output waveform is distorted, and a "crack" like noise is emitted at the output end through the speaker.
Disclosure of Invention
The invention aims to provide a noise elimination device of a digital audio power amplifier, which adopts the 'crack' noise elimination technology of the digital audio power amplifier to overcome the defects of the digital audio power amplifier system.
The technical scheme adopted by the invention for realizing the purpose is as follows:
a noise elimination device of a digital audio power amplifier comprises: integrator, comparator, controllable switch and delay circuit, wherein:
the input voltage is respectively connected with the input end of the integrator and one end of the controllable switch through the resistor R2, the output end of the integrator is connected with the reverse input end of the comparator, the forward input end of the comparator is connected with the power supply voltage, and the other end of the controllable switch is connected with the output end of the comparator through the delay circuit to serve as the output end of the device to output the comparison voltage.
The integrator includes: transconductance amplifier, electric capacity C1, electric capacity C2 and resistance R1, wherein:
the reverse input end of the transconductance amplifier is connected with the output end of the transconductance amplifier as the output end of the integrator through a capacitor C1 and a capacitor C2 in sequence, the forward input end of the transconductance amplifier is grounded, a node between a capacitor C1 and a capacitor C2 is grounded through a resistor R1, and the reverse input end of the transconductance amplifier is connected with a resistor R2 as the input end of the integrator.
The transconductance amplifier circuit is specifically as follows:
the gate of a MOS transistor MN1 is used as a forward input end of the cross-coupled amplifier, the gate of the MOS transistor MN2 is used as a reverse input end of the cross-coupled amplifier, the source of the MOS transistor MN1 is connected with the source of the MOS transistor MN2, the drain of the MOS transistor MN1 is connected with the drain of the MOS transistor MN2 through a resistor R4 and a resistor R5 in sequence, the drain of the MOS transistor MN1 is connected with the C-terminal of the first circuit, the drain of the MOS transistor MN2 is connected with the C-terminal of the second circuit, a node between the resistor R4 and the resistor R5 is respectively connected with the a-terminal of the first circuit and the a-terminal of the second circuit through a resistor R3, the D-terminal of the first circuit is connected with the D-terminal of the second circuit, the B-terminal of the first circuit is connected with the drain of the MOS transistor MN5, the drain of the MOS transistor MN5 is connected with the gate of the MOS transistor MN5, the source of the MOS transistor MN 635 is connected with the drain of the MOS transistor MN7, the drain of the MOS transistor MN-terminal MN7 is connected with the drain of the MOS transistor MN-terminal of the, the grid of MOS pipe MN5 is connected with the grid of MOS pipe MN6, the grid of MOS pipe MN7 is connected with the grid of MOS pipe MN8, the source of MOS pipe MN7 is connected with the source of MOS pipe MN8, the source of MOS pipe MN1 passes through current source I1, the D end of first circuit passes through current source I2 and links to each other with the source of MOS pipe MN8 respectively, the drain of MOS pipe MN6 passes through electric capacity C3 and grounds, the drain of MOS pipe MN6 is connected with the comparator, voltage VbThe gate of the MOS transistor MP3 in the first circuit and the gate of the MOS transistor MP7 in the second circuit are connected respectively.
The first circuit or the second circuit is specifically:
the source of the MOS transistor MP1 is connected to the source of the MOS transistor MP2, as the a terminal, the gate of the MOS transistor MP1 is connected to the gate of the MOS transistor MP2, the drain of the MOS transistor MP1 is connected to the source of the MOS transistor MP3, the drain of the MOS transistor MP2 is connected to the source of the MOS transistor MP4, the gate of the MOS transistor MP3 is connected to the gate of the MOS transistor MP4, the gate of the MOS transistor MP1 is connected to the drain of the MOS transistor MP4, the drain of the MOS transistor MP3 is the B terminal, the drain of the MOS transistor MP4 is connected to the drain of the MOS transistor MN3, the gate of the MOS transistor MN3 is the C terminal, and the source of the MOS transistor MN3 is the D terminal.
The comparator circuit is specifically:
the gate of the MOS transistor MP11 is connected to the gate of the MOS transistor MN12 as the inverting input of the comparator, the source of the MOS transistor MP11 is connected to the B terminals of the third, fourth, fifth and sixth circuits, respectively, the drain of the MOS transistor MP11 is connected to the source of the MOS transistor MP12, the drain of the MOS transistor MP12 is connected to the drain of the MOS transistor MN11, the gate of the MOS transistor MP12 is connected to the C terminal of the fourth circuit, the drain of the MOS transistor MP12 is connected to the a terminal of the fifth circuit, the source of the MOS transistor MN11 is connected to the drain of the MOS transistor MN12, the gate of the MOS transistor MN11 is connected to the C terminal of the third circuit, the source of the MOS transistor MN12 is connected to the D terminals of the third, fourth, fifth and sixth circuits, the gate of the MOS transistor MN12 is connected to the a terminal of the seventh circuit, the C terminal of the third circuit is connected to the a terminal of the fourth circuit, the C terminal of the fifth circuit is connected to the a terminal of the sixth circuit, and the a terminal of the third circuit is connected to the gate 16, and the gate of the third circuit is connected to the third circuit, The gate of the MOS transistor MN15 is connected to the level signal a, the level signal B is connected to the gate of the MOS transistor MP15 and the gate of the MOS transistor MN16, the drain of the MOS transistor MP16 is connected to the drain of the MOS transistor MN15, the source of the MOS transistor MP15 is connected to the source of the MOS transistor MP16, the source of the MOS transistor MN15 is connected to the drain of the MOS transistor MN16, the drain of the MOS transistor MP15 is connected to the delay circuit as the Y2 terminal, the sources of the MOS transistors MN16 are connected to the D terminals of the seventh circuit and the eighth circuit, the C terminal of the seventh circuit is connected to the a terminal of the eighth circuit, the B terminal of the seventh circuit is connected to the B terminal of the eighth circuit, and the C terminal of the eighth circuit is connected to the delay circuit as the Y3 terminal.
Any one of the third circuit, the fourth circuit, the fifth circuit, the sixth circuit, the seventh circuit and the eighth circuit is specifically:
the gate of the MOS transistor MP9 is connected to the gate of the MOS transistor MN9 as the a terminal, the source of the MOS transistor MP9 is the B terminal, the drain of the MOS transistor MP9 is connected to the drain of the MOS transistor MN9 as the C terminal, and the source of the MOS transistor MN9 is the D terminal.
The delay circuit specifically comprises:
the grid of the MOS tube MP19 is connected with the grid of the MOS tube MN19 to serve as a Y2 end and connected with the comparator, the source of the MOS tube MP19 is connected with the B end of the ninth circuit, the drain of the MOS tube MP19 is connected with the drain of the MOS tube MN19 and the A end of the ninth circuit respectively, the source of the MOS tube MN19 is connected with the C end of the ninth circuit, the D end of the ninth circuit serves as a Y3 end and connected with the comparator, the A end of the ninth circuit is connected with the A end of the tenth circuit, the E end of the ninth circuit is connected with the C end of the ninth circuit through a capacitor C4, the E end of the ninth circuit is connected with the D end of the tenth circuit, and the E end of the tenth circuit is connected with the reverse input end crossing the amplifier.
The ninth circuit or the tenth circuit is specifically:
the gate of MOS transistor MP20, the gate of MOS transistor MN20 and the gate of MOS transistor MN21 are connected, as an a-terminal, the source of MOS transistor MP20 is connected with the source of MOS transistor MP21 as a B-terminal, the drain of MOS transistor MP20 is connected with the gate of MOS transistor MP22 and the drain of MOS transistor MN20 respectively, the source of MOS transistor MN20 is connected with the source of MOS transistor MN22 as a C-terminal, the gate of MOS transistor MP21 is connected with the gate of MOS transistor MN22 as a D-terminal, the drain of MOS transistor MP21 is connected with the source of MOS transistor MP22, the source of MOS transistor MN21 is connected with the drain of MOS transistor MN22, the drain of MOS transistor MP22 is connected with the drain of MOS transistor MN21, and the drain of MOS transistor MP22 is connected with the E-terminal through resistor R6.
The invention has the following beneficial effects and advantages:
1. reducing the digital power amplifier startup time.
2. And eliminating output noise during power-on and power-off.
Drawings
FIG. 1 is a block diagram of the "clickly" noise cancellation architecture of the digital audio power amplifier of the present invention;
FIG. 2 is a waveform of the points after "clickly" noise cancellation;
FIG. 3 is a circuit diagram of a transconductance amplifier of the present invention;
FIG. 4 is a circuit diagram of the comparator of the present invention;
FIG. 5 is a circuit diagram of the delay module of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples.
A digital audio power amplifier 'clickly' noise cancellation technique includes: an integrator, a comparator, a controllable switch and a delay circuit;
the 'crack' noise eliminating circuit of the digital audio power amplifier is realized by a new loop formed by an integrator, a comparator, a controllable switch and a delay circuit.
The integrator is composed of a transconductance amplifier and an external circuit, and forms a positive feedback loop to generate a triangular waveform.
The comparator compares the output signals of the amplifiers
The value of (supply voltage) produces a continuous square wave.
The controllable switch controls the operating state of the loop when the circuit is turned on and off.
The delay module designs delay time through an RC circuit, so that the output of the amplifier oscillates up and down on the bias voltage, the starting time is reduced, and the 'clicking' noise is eliminated.
As shown in fig. 1, the "crack" noise cancellation module of the digital audio power amplifier mainly comprises an integrator, a comparator, a controllable switch and a delay circuit. When the control signal is at a high level, the output of the whole circuit system is in a high-impedance state, so that a feedback loop of the system does not work any more, and meanwhile, the control signal can close the controllable switch S, so that the transconductance amplifier, the comparator and the delay module work, and the RC of the delay circuit is reasonably designed so as to control the delay time and further enable the output of the transconductance amplifier to oscillate up and down at the bias voltage. When the control signal is at a low level, the controllable switch S is turned on, and the output of the transconductance amplifier oscillates up and down under the bias voltage, so that the system immediately enters a normal working state, the starting time is reduced, and the 'clicking' noise is eliminated. The waveforms of the points after the "click" noise is eliminated are shown in FIG. 2.
As shown in fig. 3, the circuit can be regarded as a two-stage transconductance amplifier structure, the first stage is an N-type differential input composed of MN1 and MN2, and the resistors R3 and R4 are used as a load of the differential output structure, and the noise ratio generated by using the resistors as the load is smaller than that generated by using the MOS as the load, but the required layout area is larger, so that the gain of the first stage of the amplifier is smaller, and the full differential structure can effectively suppress even harmonics and common mode input noise. The second stage is a symmetrical OTA structure, MN3 and MN4 are used as input geminate transistors to further reduce common-mode noise, a load adopts a low-voltage cascode current mirror structure, and output resistance and gain are high; the cascode MOS adopts self-bias to increase the output voltage swing. The capacitor C1 is a compensation capacitor, and changes the position of the dominant pole to avoid the oscillation of the amplifier loop.
As shown in FIG. 4, the comparator circuit is composed of an inverter and a clocked inverter, and the power supply voltage is VCC, so the comparator threshold is designed to be
The MN10, MN11, MN12, MP10, MP11 and MP12 form a clocked inverter, and the working state of the inverter is controlled by taking a logic signal A as an enabling end. Output terminal V of amplifierOUTThe input of the clocked inverter simultaneously controls a Y3 end signal, a Y1 end signal drives an output signal of a system circuit, a logic A signal and a logic B signal simultaneously control an output signal of a Y2 end, and a Y2 end signal and a Y3 end signal jointly control the working state of the delay module.
As shown in FIG. 5, the delay circuit is composed of an inverter, a clocked inverter and an RC circuit, wherein signals of Y2 and Y3 are controlled by output logic of the comparator, the clocked inverter is composed of MN20, MN21, MN22, MP20, MP21 and MP22 to charge and discharge the RC circuit, the clocked inverter is composed of MN23, MN24, MN25, MP23, MP24 and MP25 respectively, for circuit matching, R6 is R7, Y-end output signal is connected to negative input end V of the transconductance amplifier-The positive feedback loop is formed, and the values of the resistors R6 and C4 are reasonably designed according to the requirements of the system on the circuit frequency, so that the output of the amplifier oscillates up and down on the bias voltage.
Claims (8)
1. A noise elimination device of a digital audio power amplifier is characterized by comprising: integrator, comparator, controllable switch and delay circuit, wherein:
the input voltage is respectively connected with the input end of the integrator and one end of the controllable switch through the resistor R2, the output end of the integrator is connected with the reverse input end of the comparator, the forward input end of the comparator is connected with the power supply voltage, and the other end of the controllable switch is connected with the output end of the comparator through the delay circuit to serve as the output end of the device to output the comparison voltage.
2. The apparatus of claim 1, wherein the integrator comprises: transconductance amplifier, electric capacity C1, electric capacity C2 and resistance R1, wherein:
the reverse input end of the transconductance amplifier is connected with the output end of the transconductance amplifier as the output end of the integrator through a capacitor C1 and a capacitor C2 in sequence, the forward input end of the transconductance amplifier is grounded, a node between a capacitor C1 and a capacitor C2 is grounded through a resistor R1, and the reverse input end of the transconductance amplifier is connected with a resistor R2 as the input end of the integrator.
3. The noise cancellation device of a digital audio power amplifier according to claim 2, wherein the transconductance amplifier circuit is specifically:
the gate of a MOS tube MN1 is used as a forward input end of a cross-amplifier, the gate of a MOS tube MN2 is used as a reverse input end of the cross-amplifier, the source of the MOS tube MN1 is connected with the source of the MOS tube MN2, the drain of the MOS tube MN1 is connected with the drain of a MOS tube MN2 sequentially through a resistor R4 and a resistor R5, the drain of the MOS tube MN1 is connected with the C-terminal of the first circuit, the drain of the MOS tube MN2 is connected with the C-terminal of the second circuit, a node between the resistor R4 and the resistor R5 is respectively connected with the a-terminals of the first circuit and the second circuit through a resistor R3, the D-terminal of the first circuit is connected with the D-terminal of the second circuit, the B-terminal of the first circuit is connected with the drain of a MOS tube MN5, the drain of the MOS tube MN5 is connected with the gate of the MOS tube MN5, the source of the MOS tube MN5 is connected with the drain of the MOS tube MN7, the drain of the MOS tube MN7 is connected with the gate of the MOS tube MNThe source of MOS pipe MN6 is connected with the drain of MOS pipe MN8, the gate of MOS pipe MN5 is connected with the gate of MOS pipe MN6, the gate of MOS pipe MN7 is connected with the gate of MOS pipe MN8, the source of MOS pipe MN7 is connected with the source of MOS pipe MN8, the source of MOS pipe MN1 passes through current source I1, the D end of the first circuit passes through current source I2 and is connected with the source of MOS pipe MN8 respectively, the drain of MOS pipe MN6 passes through capacitor C3 and is grounded, the drain of MOS pipe MN6 is connected with the comparator, and voltage V is connected with the comparatorbThe gate of the MOS transistor MP3 in the first circuit and the gate of the MOS transistor MP7 in the second circuit are connected respectively.
4. The apparatus of claim 3, wherein the first circuit or the second circuit is specifically:
the source of the MOS transistor MP1 is connected to the source of the MOS transistor MP2, as the a terminal, the gate of the MOS transistor MP1 is connected to the gate of the MOS transistor MP2, the drain of the MOS transistor MP1 is connected to the source of the MOS transistor MP3, the drain of the MOS transistor MP2 is connected to the source of the MOS transistor MP4, the gate of the MOS transistor MP3 is connected to the gate of the MOS transistor MP4, the gate of the MOS transistor MP1 is connected to the drain of the MOS transistor MP4, the drain of the MOS transistor MP3 is the B terminal, the drain of the MOS transistor MP4 is connected to the drain of the MOS transistor MN3, the gate of the MOS transistor MN3 is the C terminal, and the source of the MOS transistor MN3 is the D terminal.
5. The apparatus of claim 1, wherein the comparator circuit is specifically configured to:
the gate of the MOS transistor MP11 is connected to the gate of the MOS transistor MN12 as the inverting input of the comparator, the source of the MOS transistor MP11 is connected to the B terminals of the third, fourth, fifth and sixth circuits, respectively, the drain of the MOS transistor MP11 is connected to the source of the MOS transistor MP12, the drain of the MOS transistor MP12 is connected to the drain of the MOS transistor MN11, the gate of the MOS transistor MP12 is connected to the C terminal of the fourth circuit, the drain of the MOS transistor MP12 is connected to the a terminal of the fifth circuit, the source of the MOS transistor MN11 is connected to the drain of the MOS transistor MN12, the gate of the MOS transistor MN11 is connected to the C terminal of the third circuit, the source of the MOS transistor MN12 is connected to the D terminals of the third, fourth, fifth and sixth circuits, the gate of the MOS transistor MN12 is connected to the a terminal of the seventh circuit, the C terminal of the third circuit is connected to the a terminal of the fourth circuit, the C terminal of the fifth circuit is connected to the a terminal of the sixth circuit, and the a terminal of the third circuit is connected to the gate 16, and the gate of the third circuit is connected to the third circuit, The gate of the MOS transistor MN15 is connected to the level signal a, the level signal B is connected to the gate of the MOS transistor MP15 and the gate of the MOS transistor MN16, the drain of the MOS transistor MP16 is connected to the drain of the MOS transistor MN15, the source of the MOS transistor MP15 is connected to the source of the MOS transistor MP16, the source of the MOS transistor MN15 is connected to the drain of the MOS transistor MN16, the drain of the MOS transistor MP15 is connected to the delay circuit as the Y2 terminal, the sources of the MOS transistors MN16 are connected to the D terminals of the seventh circuit and the eighth circuit, the C terminal of the seventh circuit is connected to the a terminal of the eighth circuit, the B terminal of the seventh circuit is connected to the B terminal of the eighth circuit, and the C terminal of the eighth circuit is connected to the delay circuit as the Y3 terminal.
6. The noise cancellation device of a digital audio power amplifier according to claim 5, wherein any one of the third circuit, the fourth circuit, the fifth circuit, the sixth circuit, the seventh circuit, and the eighth circuit is specifically:
the gate of the MOS transistor MP9 is connected to the gate of the MOS transistor MN9 as the a terminal, the source of the MOS transistor MP9 is the B terminal, the drain of the MOS transistor MP9 is connected to the drain of the MOS transistor MN9 as the C terminal, and the source of the MOS transistor MN9 is the D terminal.
7. The apparatus of claim 1, wherein the delay circuit is specifically configured to:
the grid of the MOS tube MP19 is connected with the grid of the MOS tube MN19 to serve as a Y2 end and connected with the comparator, the source of the MOS tube MP19 is connected with the B end of the ninth circuit, the drain of the MOS tube MP19 is connected with the drain of the MOS tube MN19 and the A end of the ninth circuit respectively, the source of the MOS tube MN19 is connected with the C end of the ninth circuit, the D end of the ninth circuit serves as a Y3 end and connected with the comparator, the A end of the ninth circuit is connected with the A end of the tenth circuit, the E end of the ninth circuit is connected with the C end of the ninth circuit through a capacitor C4, the E end of the ninth circuit is connected with the D end of the tenth circuit, and the E end of the tenth circuit is connected with the reverse input end crossing the amplifier.
8. The apparatus of claim 7, wherein the ninth circuit or the tenth circuit is specifically:
the gate of MOS transistor MP20, the gate of MOS transistor MN20 and the gate of MOS transistor MN21 are connected, as an a-terminal, the source of MOS transistor MP20 is connected with the source of MOS transistor MP21 as a B-terminal, the drain of MOS transistor MP20 is connected with the gate of MOS transistor MP22 and the drain of MOS transistor MN20 respectively, the source of MOS transistor MN20 is connected with the source of MOS transistor MN22 as a C-terminal, the gate of MOS transistor MP21 is connected with the gate of MOS transistor MN22 as a D-terminal, the drain of MOS transistor MP21 is connected with the source of MOS transistor MP22, the source of MOS transistor MN21 is connected with the drain of MOS transistor MN22, the drain of MOS transistor MP22 is connected with the drain of MOS transistor MN21, and the drain of MOS transistor MP22 is connected with the E-terminal through resistor R6.
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| CN116723451A (en) * | 2023-08-10 | 2023-09-08 | 上海海栎创科技股份有限公司 | Playback power supply control circuit and control method |
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| CN116723451A (en) * | 2023-08-10 | 2023-09-08 | 上海海栎创科技股份有限公司 | Playback power supply control circuit and control method |
| CN116723451B (en) * | 2023-08-10 | 2023-11-03 | 上海海栎创科技股份有限公司 | Playback power supply control circuit and control method |
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| CN112653399B (en) | 2024-04-23 |
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