CN112652523A - Back gold technology of semiconductor device - Google Patents

Back gold technology of semiconductor device Download PDF

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Publication number
CN112652523A
CN112652523A CN202011517395.4A CN202011517395A CN112652523A CN 112652523 A CN112652523 A CN 112652523A CN 202011517395 A CN202011517395 A CN 202011517395A CN 112652523 A CN112652523 A CN 112652523A
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CN
China
Prior art keywords
etching
semiconductor device
layer
gold
photoresist
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Pending
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CN202011517395.4A
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Chinese (zh)
Inventor
蔡文必
其他发明人请求不公开姓名
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Xiamen Sanan Integrated Circuit Co Ltd
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Xiamen Sanan Integrated Circuit Co Ltd
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Publication date
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Priority to CN202011517395.4A priority Critical patent/CN112652523A/en
Publication of CN112652523A publication Critical patent/CN112652523A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/04—Coating on selected surface areas, e.g. using masks
    • C23C14/042—Coating on selected surface areas, e.g. using masks using masks
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/06—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the coating material
    • C23C14/14—Metallic material, boron or silicon
    • C23C14/18—Metallic material, boron or silicon on other inorganic substrates
    • C23C14/185—Metallic material, boron or silicon on other inorganic substrates by cathodic sputtering
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C28/00—Coating for obtaining at least two superposed coatings either by methods not provided for in a single one of groups C23C2/00 - C23C26/00 or by combinations of methods provided for in subclasses C23C and C25C or C25D
    • C23C28/02—Coating for obtaining at least two superposed coatings either by methods not provided for in a single one of groups C23C2/00 - C23C26/00 or by combinations of methods provided for in subclasses C23C and C25C or C25D only coatings only including layers of metallic material
    • C23C28/021—Coating for obtaining at least two superposed coatings either by methods not provided for in a single one of groups C23C2/00 - C23C26/00 or by combinations of methods provided for in subclasses C23C and C25C or C25D only coatings only including layers of metallic material including at least one metal alloy layer
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/02—Electroplating of selected surface areas
    • C25D5/022—Electroplating of selected surface areas using masking means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors
    • H01L29/737—Hetero-junction transistors

Abstract

The invention discloses a back gold process of a semiconductor device, which comprises the following steps: 1) sputtering a first metal thin layer on the back of the semiconductor device; 2) coating a photoresist on the first metal thin layer to obtain a photoresist layer; 3) exposing and developing the photoresist layer in sequence to form an electroplating area uncovered by the photoresist layer and an etching area covered by the photoresist layer on the surface of the first metal thin layer; 4) sputtering and/or electroplating are carried out on the electroplating area to obtain a second metal layer; 5) removing the photoresist layer on the etching area; 6) the first thin metal layer of the etched region is removed by etching. When the etching is carried out, only the first metal thin layer is needed to be etched, so the etching thickness is greatly reduced, the etching process parameters are easier to control, the condition that the etching is not clean and needs to be compensated for etching is greatly reduced or avoided, meanwhile, the etching time is greatly shortened, and the production efficiency is improved; the consumption of the etching solution required by etching is reduced, thereby reducing the production cost.

Description

Back gold technology of semiconductor device
Technical Field
The present invention relates to a semiconductor device processing process, and more particularly, to a back-gold process for a semiconductor device.
Background
In the case of a semiconductor device (e.g., a heterojunction bipolar transistor, etc.), a back gold process is an essential process in the production and fabrication of the semiconductor device, and a metal layer with a certain thickness and an area not covered by the metal layer are attached to the back surface of the semiconductor device through a back gold process, the area not covered by the metal layer is generally used as a scribe line to avoid the wear of a dicing tool and reduce the back gold stress, and the area not covered by the metal layer can also be used as an insulation area to prevent electrical leakage. At present, in the semiconductor device in the prior art, the metal layer on the back surface of the semiconductor device is etched to obtain the area not covered by the metal layer, and the thickness of the metal layer is large (generally 3-5 μm), so that the etching time is long, the manufacturing process is not easy to control, and sometimes the situation that the etching is not clean and the complementary etching is needed is easy to occur. Moreover, the etching time is too long to affect the production efficiency; the use amount of the etching solution is large, which is not beneficial to saving the production cost.
Disclosure of Invention
Aiming at the technical problems in the prior art, the invention provides a back gold process of a semiconductor device, which can reduce the etching thickness, shorten the etching time, improve the production efficiency and reduce the production cost.
The technical scheme adopted by the invention for solving the technical problems is as follows: a back gold process of a semiconductor device comprises the following steps:
1) sputtering a first metal thin layer on the back of the semiconductor device;
2) coating a photoresist on the first metal thin layer to obtain a photoresist layer;
3) exposing and developing the photoresist layer in sequence to form an electroplating area uncovered by the photoresist layer and an etching area covered by the photoresist layer on the surface of the first metal thin layer;
4) sputtering and/or electroplating are carried out on the electroplating area to obtain a second metal layer;
5) removing the photoresist layer on the etching area;
6) the first thin metal layer of the etched region is removed by etching.
Further, in the step 6), a gold etching solution is used for etching, the operation temperature is 20-35 ℃, and the operation time is 70-126 s.
Further, in the step 5), a photoresist removing liquid is used for removing the photoresist layer on the etching area, the operation temperature is 76-100 ℃, and the operation time is 180-250 s.
Further, the operation temperature of the step 4) is 38-56 ℃, and the operation time is 75-95 s.
Further, in the step 2), the photoresist is a negative photoresist, and the operating temperature is 20-35 ℃.
Further, the first metal thin layer is titanium tungsten or gold; the second metal layer is gold.
Further, the thickness of the first metal thin layer is smaller than that of the second metal layer.
Furthermore, the thickness of the first metal thin layer is 0.2-0.6 μm, and the thickness of the second metal layer is 2.4-4.8 μm.
Further, the semiconductor device is a III-V semiconductor device.
Further, the semiconductor device is a heterojunction bipolar transistor.
Compared with the prior art, the invention has the following beneficial effects:
the invention firstly sputters the first metal thin layer on the back of the semiconductor device, then coats the photoresist on the second metal layer to obtain the photoresist layer, forms the electroplating area which is not covered by the photoresist layer and the etching area which is covered by the photoresist layer on the surface of the first metal thin layer by the exposure and development modes, then sputters and/or electroplates in the electroplating area to obtain the second metal layer, and finally removes the photoresist layer on the etching area and removes the first metal thin layer in the etching area by etching, so that the invention only needs to etch the first metal thin layer when etching, the etching thickness is greatly reduced, the etching process parameters are easier to control, and the condition that the etching is not clean and needs to be compensated and etched is greatly reduced or avoided; the second metal layer can be electroplated thicker to ensure excellent electrical performance because etching is not required; meanwhile, the etching time is greatly shortened, so that the production efficiency is improved; the consumption of the etching solution required by etching is reduced, thereby reducing the production cost.
The invention is further explained in detail with the accompanying drawings and the embodiments; a gold-back process of a semiconductor device of the present invention is not limited to the embodiment.
Drawings
FIG. 1 is a cross-sectional view of a semiconductor device after sputtering a thin layer of a first metal;
FIG. 2 is a cross-sectional view of a first thin metal layer coated with photoresist;
FIG. 3 is a cross-sectional view of a photoresist layer after exposure and development;
FIG. 4 is a cross-sectional view of the plated area after plating a second metal layer;
FIG. 5 is a cross-sectional view after removing the photoresist layer over the etched area;
fig. 6 is a cross-sectional view after removing the first thin metal layer in the etched region.
Detailed Description
In an embodiment, referring to fig. 1 to fig. 6, a back gold process of a semiconductor device according to the present invention includes the following steps:
1) sputtering a first metal thin layer 2 on the back surface of a semiconductor device 1, as shown in fig. 1, wherein the semiconductor device 1 is shown in a simple schematic view in fig. 1;
2) coating photoresist on the first metal thin layer 2 to obtain a photoresist layer 3, as shown in FIG. 2;
3) exposing and developing the photoresist layer 3 in sequence to form an electroplating region 21 uncovered by the photoresist layer 3 and an etching region 22 covered by the photoresist layer 3 on the surface of the first metal thin layer 2, as shown in fig. 3;
4) sputtering and/or electroplating are/is carried out on the electroplating area 21 to obtain a second metal layer 4, as shown in fig. 4;
5) removing the photoresist layer 3 on the etching region 22, as shown in fig. 5;
6) the first thin metal layer 2 of said etched area 22 is removed by etching, as shown in fig. 6.
In this embodiment, the first metal thin layer 2 in step 1) may be gold, and then gold in a layer thickness can be directly electroplated in the electroplating region 21 in step 4), because the metals are the same, the electroplated metal features are better; the first metal thin layer 2 in the step 1) can also be titanium tungsten with better adhesion, and then in the step 4), a layer of thinner gold is sputtered in the electroplating area 21, and then the gold is electroplated to form a thick second metal layer 4, so that the electroplated metal appearance is better.
In this embodiment, in the step 2), the photoresist is a negative photoresist, and the operating temperature is 20 to 35 ℃. The operation temperature of the step 4) is 38-56 ℃, and the operation time is 75-95 s. In the step 5), the photoresist layer 3 on the etching area 22 is removed by using a photoresist removing liquid, wherein the operating temperature is 76-100 ℃, and the operating time is 180-250 s. And 6) etching by using a gold etching solution, wherein the operation temperature is 20-35 ℃, and the operation time is 70-126 s.
In this embodiment, the first metal thin layer 2 and the second metal thin layer 4 are made of titanium tungsten or gold, respectively. The thickness of the first metal thin layer 2 is smaller than that of the second metal layer 4. Specifically, the thickness of the first metal thin layer 2 is 0.2-0.6 μm, and the thickness of the second metal layer 4 is 2.4-4.8 μm.
In the present embodiment, the semiconductor device 1 is a III-V semiconductor device, and specifically, the semiconductor device 1 is a heterojunction bipolar transistor, but is not limited thereto.
The invention relates to a back gold process of a semiconductor device, which comprises the steps of sputtering a first metal thin layer 2 on the back surface of a semiconductor device 1, coating a photoresist on a second metal layer 4 to obtain a photoresist layer 3, forming an electroplating area 21 which is not covered by the photoresist layer 3 and an etching area 22 which is covered by the photoresist layer 3 on the surface of the first metal thin layer 2 in an exposure and development mode, then sputtering and/or electroplating in the electroplating area 21 to obtain a second metal layer 4, finally removing the photoresist layer 3 on the etching area 22, and removing the first metal thin layer 2 in the etching area 22 by etching, so that the first metal thin layer 2 is only required to be etched with the etching thickness of 0.2-0.6 mu m when the back gold process is used for etching, obviously, compared with the etching thickness of the prior art (the etching thickness of the prior art is 3-5 mu m), the etching thickness of the back gold process is greatly reduced, therefore, it is easier to control the etching process parameters, and the situation that the etching is not clean and needs to be performed with the complementary etching is greatly reduced or avoided. In addition, the etching thickness of the invention is greatly reduced, so the etching time of the invention can be greatly shortened, the production efficiency is improved, the productivity is improved, and meanwhile, the consumption of the etching solution required by etching is also greatly reduced, thereby the production cost can be reduced.
According to the back gold technology of the semiconductor device, after the steps are carried out, a metal layer is attached to the back surface of the semiconductor device 1, the metal layer is formed by overlapping the first metal thin layer 2 and the second metal layer 4, and the thickness of the metal layer is 2.6-5.4 microns. Meanwhile, the back surface of the semiconductor device 1 is formed with a region 5 not covered with the metal layer.
The back gold technology of the semiconductor device of the invention has the same or can be realized by adopting the prior art for the non-related parts. For example, the exposure, development and etching processes are all prior art processes, and the invention is not described further.
The above embodiments are only used to further illustrate the back gold process of the semiconductor device of the present invention, but the present invention is not limited to the embodiments, and any simple modification, equivalent change and modification made to the above embodiments according to the technical spirit of the present invention fall within the protection scope of the technical solution of the present invention.

Claims (10)

1. A back gold technology of a semiconductor device is characterized in that: the method comprises the following steps:
1) sputtering a first metal thin layer on the back of the semiconductor device;
2) coating a photoresist on the first metal thin layer to obtain a photoresist layer;
3) exposing and developing the photoresist layer in sequence to form an electroplating area uncovered by the photoresist layer and an etching area covered by the photoresist layer on the surface of the first metal thin layer;
4) sputtering and/or electroplating are carried out on the electroplating area to obtain a second metal layer;
5) removing the photoresist layer on the etching area;
6) the first thin metal layer of the etched region is removed by etching.
2. The gold-back process of a semiconductor device according to claim 1, wherein: etching is carried out by adopting etching liquid in the step 6), wherein the operation temperature is 20-35 ℃, and the operation time is 70-126 s.
3. The gold-back process of a semiconductor device according to claim 1, wherein: and in the step 5), removing the photoresist layer on the etching area by using a photoresist removing liquid, wherein the operation temperature is 76-100 ℃, and the operation time is 180-250 s.
4. The gold-back process of a semiconductor device according to claim 1, wherein: the operation temperature of the step 4) is 38-56 ℃, and the operation time is 75-95 s.
5. The gold-back process of a semiconductor device according to claim 1, wherein: in the step 2), the photoresist is a negative photoresist, and the operating temperature is 20-35 ℃.
6. The gold-back process of a semiconductor device according to claim 1, wherein: the first metal thin layer is tungsten titanium or gold; the second metal layer is gold.
7. The gold-back process of a semiconductor device according to claim 1, wherein: the thickness of the first metal thin layer is smaller than that of the second metal layer.
8. The gold-back process of a semiconductor device according to claim 1 or 7, wherein: the thickness of the first metal thin layer is 0.2-0.6 mu m, and the thickness of the second metal layer is 2.4-4.8 mu m.
9. The gold-back process of a semiconductor device according to claim 1, wherein: the semiconductor device is a group III-V semiconductor device.
10. The gold-backed process for a semiconductor device according to claim 9, wherein: the semiconductor device is a heterojunction bipolar transistor.
CN202011517395.4A 2020-12-21 2020-12-21 Back gold technology of semiconductor device Pending CN112652523A (en)

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Application Number Priority Date Filing Date Title
CN202011517395.4A CN112652523A (en) 2020-12-21 2020-12-21 Back gold technology of semiconductor device

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102339795A (en) * 2010-07-15 2012-02-01 英飞凌科技奥地利有限公司 Method for manufacturing semiconductor devices having a metallisation layer
US20130299944A1 (en) * 2012-05-14 2013-11-14 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and Apparatus for Bipolar Junction Transistors and Resistors
US20150221764A1 (en) * 2014-02-04 2015-08-06 Infineon Technologies Ag Wafer based beol process for chip embedding
CN107039375A (en) * 2015-12-30 2017-08-11 台湾积体电路制造股份有限公司 Semiconductor devices and its manufacture method
CN111627880A (en) * 2020-06-04 2020-09-04 厦门通富微电子有限公司 Semiconductor bump, manufacturing method thereof and packaging structure

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102339795A (en) * 2010-07-15 2012-02-01 英飞凌科技奥地利有限公司 Method for manufacturing semiconductor devices having a metallisation layer
US20130299944A1 (en) * 2012-05-14 2013-11-14 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and Apparatus for Bipolar Junction Transistors and Resistors
US20150221764A1 (en) * 2014-02-04 2015-08-06 Infineon Technologies Ag Wafer based beol process for chip embedding
CN107039375A (en) * 2015-12-30 2017-08-11 台湾积体电路制造股份有限公司 Semiconductor devices and its manufacture method
CN111627880A (en) * 2020-06-04 2020-09-04 厦门通富微电子有限公司 Semiconductor bump, manufacturing method thereof and packaging structure

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Application publication date: 20210413