CN112652337B - Line decoder for memory - Google Patents
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- CN112652337B CN112652337B CN201910959692.5A CN201910959692A CN112652337B CN 112652337 B CN112652337 B CN 112652337B CN 201910959692 A CN201910959692 A CN 201910959692A CN 112652337 B CN112652337 B CN 112652337B
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- G—PHYSICS
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- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/10—Decoders
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- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/165—Auxiliary circuits
- G11C11/1653—Address circuits or decoders
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- G11C11/165—Auxiliary circuits
- G11C11/1653—Address circuits or decoders
- G11C11/1657—Word-line or row circuits
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- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
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Abstract
The application provides a row decoder of a memory, which is mainly structurally characterized in that a selection decoder, a pre-decoder and a main decoder are of a multi-to-multi decoder structure, the selection decoder and the pre-decoder are controlled by a discharge signal control line to output or clear an address selection signal, and a driving module is arranged at the output end of the selection decoder to adjust the address selection and read/write control potentials of all word line driving circuits, and each output of the driving module is connected with the corresponding word line driving circuit. The selection decoder, the pre-decoder and the main decoder are combined with the driving module to convert the read/write operation potential according to the output address selection signal, the timing module coordinates the signal delay of the three-state gate transmission circuits, and the word line driving circuit is used for selecting and controlling word line data under the structure of the row decoder of the reduced component architecture. The row decoder has the advantages of simple structure, low manufacturing cost, high reliability and the like.
Description
Technical Field
The present invention relates to the field of memory technology, and in particular, to a row decoder for a memory.
Background
The row decoder circuit converts the multi-bit input signal into a multi-bit output signal for selecting the word lines of the memory array cells. In the case of a nonvolatile memory of a Magnetoresistive Random Access Memory (MRAM), in order to achieve reliable operation, during a write operation, since a large driving current capability is required for the Magnetic Tunneling Junction (MTJ) to switch from high resistance to low resistance (or vice versa), word lines are typically subjected to over-voltage processing for the write operation, i.e., the selected cell word line potential is high at this time; when the read operation is performed, only the external circuit is needed to read the resistance value of the selected cell MTJ, so that the data is prevented from being rewritten, the power consumption is reduced, and the word line potential is lower relative to that of the write operation during the read operation. Therefore, special processing is required to design MRAM memory row decoder circuits.
Memories typically use high voltage devices to reliably transfer high voltage signals, along with potential shifting (Level Shift) and transmissions using high voltage devices. As the process progresses, the size of the high-voltage device is not proportionally reduced, and the current practice is to combine the corresponding 512 potential conversion circuits and transmission gates through the two-stage decoder, so that the row decoder circuit in the direction of the array word line may occupy a large area, and the cost of manufacturing the memory chip is increased. The next relevant pull-down transistors are controlled by the discharge signal (DISCAHRGE) because the circuit driving capability is high. And secondly, the delay of the discharge signal to the input end of the word line driving circuit and the delay of the relevant pull-down tube are difficult to be consistent, the time required for selecting the word line is easy to be prolonged, the charge and discharge of the selected word line and the on and off time of the relevant transistor are unstable, and more power consumption is wasted.
U.S. Pat. No. 5719818 discloses a DECODER which controls the address segmentation to control a part of the address lines to control the PRE-DECODER (PRE-DECODER) and the MAIN DECODER (MAIN-DECODER) and controls the input signals (F0-Fi) of the word line driving circuit by the read/write potential selection signals of VCC/VHH; the other part of address lines controls a selection DECODER (SELECT-DECODER) to drive selection signals (S0-Sj) of the tri-state gate transmission circuit, and finally word lines (WL 0-WLj) are driven together through the input signals Fi and the selection signals Sj.
Disclosure of Invention
In order to solve the above-mentioned problems, an object of the present application is to provide a row decoder of a memory, which can realize the selection and control of word line data by a word line driving circuit by adjusting decoders with different functions under the structure of the row decoder with a reduced component architecture. The row decoder has the advantages of simple structure, low manufacturing cost, high reliability and the like.
The aim and the technical problems of the application are achieved by adopting the following technical scheme.
According to the present application, a row decoder of a memory is provided, and is suitable for a magnetic random access memory chip architecture, and the selected word lines and bit lines are connected through control of the row decoder and the column decoder, where the row decoder includes: the input end of the selection decoder is connected with a first group of bit address lines; the input end of the pre-decoder is connected with a second group of bit address lines; a discharge signal control line electrically connected to the control ends of the selection decoder and the front decoder; the input end of the main decoder is connected with the output end of the front decoder; the selection decoder, the front decoder and the main decoder are of a multi-to-multi decoder structure; a plurality of word line driving circuits, each word line driving circuit comprising: a potential converter connected to an output terminal of the main decoder for converting a low logic level signal suitable for a core device output from the main decoder into a high logic level signal suitable for a peripheral device; the input ends of the three-state gate transmission circuits are electrically connected with the output end of the selection decoder correspondingly, and the address selection control ends of the three-state gate transmission circuits are connected with the output end of the potential converter; the input end of the time sequence module is electrically connected with the address selection control ends of the three-state gate transmission circuits, and the output end of the time sequence module is connected with the word line selection control ends of the three-state gate transmission circuits; the driving module is arranged between the plurality of selection output ends and the plurality of word line driving circuits and is used for switching each output voltage of the selection decoder to different potentials according to control information; the main decoder drives the selected word line driving circuit according to the address selecting signal output by the pre-decoder, and the selected word line driving circuit enables the tri-state gate transmission circuit of the selected word line driving circuit to read or write bit word line data through the output information of the selected decoder and the driving module; the timing module coordinates signal timing delays of the address selection control end and the word line selection control end of the plurality of tri-state gate transmission circuits to be within a delay value.
The technical problem of the application can be further solved by adopting the following technical measures.
In an embodiment of the present application, when the discharge signal control line outputs an active control signal, the output terminals of the pre-decoder all output low voltages, and the main decoder is controlled to make all the output terminals output high voltages, so as to pull all the word lines low.
In an embodiment of the present application, when the discharge signal control line outputs an invalid control signal, the pre-decoder controls the main decoder according to the bit address line signal provided by the second set of bit address lines, so as to drive the corresponding word line driving circuit, and the potential converter of the corresponding word line driving circuit outputs a high potential.
In an embodiment of the present application, when the discharge signal control line outputs an invalid control signal, the selection decoder outputs an address signal to the plurality of word line driving circuits according to the bit address line signals provided by the first set of bit address lines, and the driving module selectively adjusts the potential of the address signal to be a read operation word line potential or a write operation word line potential.
In an embodiment of the present application, the write operation word line potential is higher than the read operation word line potential.
In an embodiment of the present application, each tri-state gate transmission circuit includes a signal transmission gate and a word line control transistor, a control end of the signal transmission gate is electrically connected to one of output ends of the driving module, a control end of the signal transmission gate is connected to an input end of the timing module, a control end of the word line control transistor is connected to an output end of the timing module, a drain electrode of the word line control transistor is connected to a corresponding word line, and an output end of the signal transmission gate is connected to a drain electrode of the word line control transistor.
In an embodiment of the present application, the signal transmission gate is formed by a P-type field effect transistor and an N-type field effect transistor, and the word line control transistor is an N-type field effect transistor, where the signals received by the P-type field effect transistor and the N-type field effect transistor of the signal transmission gate are opposite.
In an embodiment of the present application, the timing module includes a nand logic gate and an inverter, two input ends of the nand logic gate are connected to an output end of the potential converter, one of the two input ends is provided with a delay unit, an output end of the nand logic gate is connected to an input end of the inverter, and an output end of the inverter is connected to a word line selection control end of the plurality of tri-state gate transmission circuits; the timing module has an inverting function, so that the corresponding word line discharging capability and voltage signal transmission capability are completed.
In one embodiment of the present application, the delay unit is composed of an even number of inverters.
Another object of the present application is to provide a method for controlling the timing of a row decoder of any of the foregoing memories, including: when address information reaches the row decoder, the output of all potential conversion modules controlled by the selection decoder is pulled down to low potential according to the discharge signal, and meanwhile, the output of all drivers controlled by the front decoder and the main decoder is pulled down to low potential, so that a transmission gate controlled by a control signal is gradually turned off; after the delay value, charging delay signals corresponding to all address information to high potential signals, thereby discharging all word lines; when all word lines are discharged, the discharging signals are pulled down, the selection decoder controls the corresponding potential conversion module to output to be pulled up to high potential according to the address signals, meanwhile, the front decoder and the main decoder control the corresponding driver to output to be pulled up to high potential, so that the transmission gates controlled by the control signals are gradually opened, the output signals of the corresponding potential converter modules are transmitted to the corresponding word lines, and the potential of the selected word lines is raised to high potential; and, the selected cells in the memory array achieve proper configuration of the word line potential in accordance with read/write operations.
According to the method, through the change of the component connection structure, all the word line driving circuits are controlled by a single main decoder, the discharge signal control lines are only used for controlling the address selection and signal clearing of the selection decoder and the front decoder, the word line control ends of all the word line driving circuits are controlled by the respective time sequence modules, and the discharge signal control lines are connected to the word line control ends of all the word line driving circuits, so that the circuit scale can be selectively reduced, the information driving capability is reduced on the premise of maintaining the address selection information, and the chip cost is relatively reduced. And secondly, through the delay module, the word line selection signals of all the tri-state gate transmission circuits are obtained by delaying the output signals of the potential converter, the time sequences of the two signals are relatively fixed, the situation that the signals are delayed mutually is avoided, meanwhile, the situation that the prior selected word line is discharged and charged simultaneously is avoided, and the dynamic power consumption of the row decoding circuit can be reduced. Moreover, the unselected word lines greatly reduce the influence of the falling edge of the delay signal on the word lines due to the strong discharging capability of the N-type field effect transistor, thereby increasing the reliability of word line selection and operation. The row decoder disclosed by the application has the advantages of simplicity in operation, low chip cost, high reliability and the like, and is suitable for a memory circuit.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of an exemplary memory row decoder;
FIG. 2 is a schematic diagram of a row decoder of a memory according to an embodiment of the present application;
FIG. 3 is a schematic diagram illustrating a timing module of a row decoder according to an embodiment of the present disclosure;
FIG. 4 is a timing diagram illustrating operation of a memory row decoder according to an embodiment of the present application;
fig. 5a to 5d are schematic diagrams illustrating the implementation of the memory row decoder according to the embodiments of the present application.
Detailed Description
Referring to the drawings, wherein like reference numbers refer to like elements throughout. The following description is based on the illustrated embodiments of the present application and should not be taken as limiting other embodiments not described in detail herein.
The following description of the embodiments refers to the accompanying drawings, which illustrate specific embodiments that can be used to practice the present application. The directional terms mentioned in this application, such as "up", "down", "front", "back", "left", "right", "inside", "outside", "side", etc., refer only to the directions of the attached drawings. Accordingly, directional terminology is used to describe and understand the application and is not intended to be limiting of the application.
The terms "first," second, "" third and the like in the description and in the claims of this application and in the above-described figures, if any, are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It will be appreciated that the objects so described may be interchanged under appropriate circumstances. Furthermore, the terms "comprise" and "have," as well as variations thereof, are intended to cover a non-exclusive inclusion.
The terminology used in the description of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the concepts of the present application. The use of expressions in the singular encompasses plural forms of expressions unless the context clearly dictates otherwise. In this specification, it should be understood that terms such as "comprises," "comprising," "includes," and "including" are intended to specify the presence of the stated features, integers, steps, actions, or combinations thereof, disclosed in the specification, but are not intended to preclude the presence or addition of one or more other features, integers, steps, actions, or groups thereof. Like reference numerals in the drawings refer to like parts.
The drawings and description are to be regarded as illustrative in nature, and not as restrictive. In the drawings, like structural elements are denoted by like reference numerals. In addition, for the sake of understanding and convenience of description, the size and thickness of each component shown in the drawings are arbitrarily shown, but the present application is not limited thereto.
In the drawings, the scope of the arrangement of devices, systems, components, circuits, etc. is exaggerated for clarity, understanding, and convenience of description. It will be understood that when an element is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present.
In addition, in the description, unless explicitly described to the contrary, the word "comprising" will be understood to mean comprising the recited component, but not excluding any other components. Further, in the specification, "above" means above or below the target assembly, and does not mean necessarily on top based on the direction of gravity.
In order to further describe the technical means and effects adopted by the present invention to achieve the preset purpose, the following description refers to the specific implementation, structure, characteristics and effects of a memory row decoder according to the present invention with reference to the accompanying drawings and the specific embodiments.
FIG. 1 is a schematic diagram of an exemplary memory row decoder. As shown in fig. 1, the row Decoder includes a Select Decoder (Select-Decoder) 110, a Pre-Decoder (Pre-Decoder) 120, a Main Decoder (Main-Decoder) 130, a plurality of Word Line Driver circuits (Word Line Driver) 140, and a plurality of driving modules (driving modules) 150. The select decoder 110 and the pre-decoder 120 are many-to-many decoders, and the main decoder 130 is a many-to-one decoder. The input terminal of the selection decoder 110 is connected to the first group of bit address lines 210 to receive the first group of bit address signals, and the output terminal of the selection decoder 110 outputs the address selection signals (S0 to Sj). The input end of the pre-decoder 120 is connected to the second set of bit address lines 220 to receive the second set of bit address signals, and the output end of the pre-decoder 120 is connected to the input ends of all the main decoders 130 to be used as the selection control of the main decoders 130. The output end of each main decoder 130 is connected to the driving module 150 to adjust the control signals (F0-Fj) transmitted to the corresponding word line driving circuit 140, wherein the main decoder 130, the driving module 150 and the word line driving circuit 140 are correspondingly arranged, and i+1 groups are all provided. Each word line driving circuit 140 has j tri-state gate transmission circuits, whose signal input ends are respectively connected to the output ends of the selection decoder 110 to obtain the address selection signals (S0-Sj), whose address selection control ends are connected to the output ends of the driving module 150 to receive the control signals (Fi) of the corresponding word line driving circuit 140, and whose word line selection control ends of all the word line driving circuits 140 and the control end of the pre-decoder 120 are connected to the Discharge signal control line (Discharge). In some embodiments, the word lines (WL 0 to WLj to WL (i-1) j to WLi j) are commonly driven by a control signal (Fi) and an address signal (Sj) signal, and the charge and Discharge time of the word lines is controlled in conjunction with a Discharge signal (Discharge).
However, a Discharge signal (Discharge) controls the pre-decoder 120 and the pull-down tube driving all word line select control terminals. In the memory array structure shown in FIG. 1, j is generally 256/512, which means that 256/512 cells may be mounted on each word line, so that the size of the pull-down tube corresponding to the word line is required to be larger, and all the pull-down tubes are controlled by a Discharge signal (Discharge). Therefore, the signal driving capability of the Discharge signal (Discharge) circuit is required to be high.
Further, the delay of the Discharge signal (Discharge) to the control signal (Fi) and the delay of the Discharge signal (Discharge) to the pull-down tube of the word line selection control terminal are hardly uniform. Assuming that the rising edge of the control signal (Fi) is reached later, the word line selected by the front address is charged while discharging, resulting in a word line selection result depending on the magnitude of the charged and discharged current, i.e.: when the discharge current is small, the word line potential remains unchanged, otherwise, the potential drops. Similarly, assuming that the falling edge of the control signal (Fi) arrives first, it may cause the word line potential to drop. Therefore, the control signal (Fi) and the Discharge signal (Discharge) have inconsistent arrival times, which results in longer required time for the selected word line and additional power consumption.
In addition, after the address signal (Sj) is reached, when the potential of the control signal (Fi) is reduced, the selected word line potential is discharged, and the charging is performed through the PMOS transistor, which may require a long time; in addition, when the unselected word line finishes discharging, the PMOS tube is turned off because the control signal (Fi) is at high potential, and when the Discharge signal (Discharge) is changed from high to low, the NMOS tube controlled by the control signal (Fi) is gradually turned off and the PMOS tube is slowly turned on, and because parasitic capacitance exists at the drain end and the grid electrode of the pull-down tube at the word line selection control end, the charge on the word line is reduced to be negative because the charge is not timely supplemented; the magnitude of the negative potential value depends on the parasitic capacitance of the gate drain and the abrupt values of the gate capacitance and gate potential. If the word line potential is sufficiently negative, a large transient current may be generated. Even if the PMOS tube is opened slowly, the on-resistance is larger, and still a longer time is needed to pull the potential of the unselected word line back to zero level. Therefore, the conventional segment decoder has the problems of power consumption waste and long word line on time caused by difficulty in word line driving and different transmission delays.
Fig. 2 is a schematic diagram of a structure of a row decoder of the memory according to an embodiment of the present application. Referring to fig. 2, a row decoder of the memory is suitable for a magnetic random access memory chip architecture, and the selected word lines and bit lines are connected through control of the row decoder and the column decoder, the row decoder includes: a Select-Decoder 110, an input of the Select-Decoder 110 being connected to a first set of bit address lines 210; a Pre-Decoder (Pre-Decoder) 120, wherein an input end of the Pre-Decoder 120 is connected to a second group of bit address lines 220; a Discharge signal control line (Discharge) electrically connected to the control ends of the selection decoder 110 and the pre-decoder 120; a Main Decoder 130, an input terminal of which is connected to an output terminal of the pre-Decoder 120; the selection decoder 110, the pre-decoder 120 and the main decoder 130 are in a many-to-many decoder structure; a plurality of word line driving circuits 140, each word line driving circuit 140 comprising: a Level Shift (Level Shift) 160 connected to an output terminal of the main decoder 130, for converting a low logic Level signal suitable for a core device output from the main decoder 130 into a high logic Level signal suitable for a peripheral device; a plurality of tri-state gate transmission circuits, the input ends of which are electrically connected to the output end of the selection decoder 110, and the address selection control ends 141 of which are connected to the output end of the potential converter 160; the input end of the time sequence module 143 is electrically connected with the address selection control ends 141 of the three-state gate transmission circuits, and the output end of the time sequence module 143 is connected with the word line selection control ends 142 of the three-state gate transmission circuits; the driving module 150 is disposed between the plurality of selection output terminals and the plurality of word line driving circuits 140, and switches each output voltage of the selection decoder 110 to a different potential according to control information; wherein, the pre-decoder 120 and the selection decoder 110 output an address signal or clear the address signal according to the electric potential of the Discharge signal control line (Discharge), the main decoder 130 drives the selected word line driving circuit 140 according to the address signal output by the pre-decoder 120, and the selected word line driving circuit 140 makes the tri-state gate transmission circuit of the selected word line driving circuit 140 perform the reading or writing operation of the bit word line data through the output information of the selection decoder 110 and the driving module 150; the timing module 143 coordinates signal timing delays of the address selection control terminal and the word line selection control terminal of the plurality of tri-state gate transmission circuits to be within a delay value.
In some embodiments, the level shifter 160 mainly includes a signal driving unit and a level shifter circuit (transmission driving of a control signal (Fi) and driving of the timing module 143).
In one embodiment of the present application, the input signals of the pre-decoder 120 mainly come from the Discharge signal control line (Discharge) and the second set of bit address lines 220. The output signal of the pre-decoder 120 is directly input as the address of the main decoder 130. The multi-bit output signal of the main decoder 130 is potential-converted and signal-driven by the potential converter 160 to output a control signal (Fi).
In some embodiments, when the Discharge signal control line (Discharge) outputs an active control signal, the output terminals of the pre-decoder 120 all output low, and the main decoder 130 is controlled to make all output terminals output high, so that all word lines are effectively pulled down to low.
In some embodiments, when the Discharge signal control line (Discharge) outputs an inactive control signal, the pre-decoder 120 controls the main decoder 130 according to the bit address line signals provided by the second set of bit address lines 220 to drive the corresponding word line driving circuit 140, and the potential converter 160 of the corresponding word line driving circuit 140 outputs a high potential, i.e. only one bit of the i control signals (F) has a voltage value VHH.
In one embodiment of the present application, the input signals of the selection decoder 110 mainly come from the Discharge signal control line (Discharge) and the first group of bit address lines 210. The multi-bit signal decoded by the select decoder 110 is converted by the driving module 150 and is used as an input signal of the word line driving circuit 140.
In an embodiment of the present application, when the Discharge signal control line (Discharge) outputs an active control signal, the output terminal of the selection decoder 110 outputs a low voltage, and the driving module 150 is controlled to output a low voltage, i.e. all address signals (V0-Vj) are low voltages.
In an embodiment of the present application, when the Discharge signal control line (Discharge) outputs the disable control signal, the selection decoder 110 outputs the address signal to the word line driving circuits 140 according to the address line signals provided by the first set of address lines 210, and the driving module 150 selectively adjusts the potential of the address signal to be high, that is, only one high potential exists in the j address signals (V), and the specific high potential is configured according to the Write Enable (WEN) signal, that is, the read word line potential or the write word line potential is adjusted according to the level of the WEN signal.
In one embodiment of the present application, the entire row decoder includes i+1 word line driving circuits 140. Each word line driver circuit 140 includes 1 timing module 143 and j+1 tri-state gate transmission circuits. Whether the j+1 bit address signal (V) is connected to its corresponding bit word line WLi is controlled by i control signals (F) and delay signals (D).
In some embodiments, the tri-state gate transmission circuit is used to control whether the address signal (Vj) is effectively conducted with the corresponding word line. Each tri-state gate transmission circuit comprises a signal transmission gate (corresponding to the address selection control terminal 141) and a word line control transistor (corresponding to the word line selection control terminal 142), wherein the control terminal of the signal transmission gate is electrically connected with one of the output terminals of the driving module 150, the control terminal of the signal transmission gate is connected with the input terminal of the timing module 143, the control terminal of the word line control transistor is connected with the output terminal of the timing module 143, the drain electrode of the word line control transistor is connected with the word line, and the output terminal of the signal transmission gate is connected with the source electrode of the word line control transistor.
In some embodiments, the signal transmission gate is composed of a P-type field effect transistor and an N-type field effect transistor, wherein the signals received by the P-type field effect transistor and the N-type field effect transistor of the signal transmission gate are in opposite phases; for example: in the transmissions, the gate of PMOS is controlled by control signal Fi, but the gate of NMOS is controlled by the inverse of control signal Fi.
In some embodiments, the word line control transistor is an N-type field effect transistor.
Fig. 3 is a schematic diagram of a timing module 143 of a row decoder according to an embodiment of the present application. In an embodiment of the present application, the timing module 143 is configured by a logic Gate (logic Gate), the timing module 143 includes a NAND logic Gate (NAND Gate) 145 and an inverter 146, two input terminals of the NAND logic Gate 145 are connected to an output terminal of the potential converter 160, one of the two input terminals is provided with a delay unit 144, an output terminal of the NAND logic Gate 145 is connected to an input terminal of the inverter 146, and an output terminal of the inverter 146 is connected to a word line selection control terminal of the plurality of tri-state Gate transmission circuits; the timing module 143 has an inverting function to enable the corresponding word line discharging capability and voltage signal transmitting capability.
In some embodiments, the delay unit 144 is comprised of an even number of inverters.
In some embodiments, the timing module 143 performs a logical nand operation on the control signal (Fi) and the control signal (Fi) through the delay unit 144, and outputs the delay signal (Di) through the inverter 146 to drive the word line.
It should be noted that the delay unit 144 cannot be set too large or too small. If the delay is small, the transient high current cannot be effectively reduced; on the contrary, if the delay value is larger, the word line cannot be effectively driven, even the word line cannot be started, so that the setting of a smaller delay value is reasonable. The delay unit 144 may be constituted by a simple inverter chain or may be constituted by a resistor and a capacitor, and is selected mainly according to a delay value. If the delay value is small, the inverter chain is easier to construct, so that the chip area is saved.
In some embodiments, with MRAM, the selected bit word lines need to have different potentials for either write or read operations. In general, since the write word line potential is higher than the read word line potential, after the end of decoding by the select decoder 110, the potential is converted into the read word line potential VCC or the write word line potential VHH by the driving module 150 according to the WEN signal. In some embodiments, the write word line potential VHH is applied as an address signal (Vj) to the selected tri-state gate transfer circuit during a write operation, and the read word line potential VCC is applied as an address signal (Vj) to the selected tri-state gate transfer circuit during a read operation. In the level shifter 160, the write operation word line level VHH can perform the function of transmitting the address signal (Vj) to the corresponding word line and the function of discharging the word line, so that the level is only required to be shifted to VHH, thereby saving the chip cost.
Fig. 4 is a timing chart of the operation of the memory row decoder according to the embodiment of the present application, please refer to fig. 1 to 3 in conjunction with fig. 5a to 5d in advance for understanding. FIG. 4 illustrates the process of converting the address of the memory from ADD0 to ADD1, but is not limited thereto, and other address selection methods are also within the scope of this concept.
In some embodiments, when the ADD1 address information reaches the row decoder (whether via the first set of bit address lines 210 and the second set of bit address lines 220), all control signals (Fi) (including the F signal selected by the previous address) are pulled up to the VHH potential according to the Discharge signal (Discharge); all address signals (Vj) (including the V signal selected by the previous address) are pulled down to 0 potential. The transfer gate controlled by the control signal (Fi) is gradually turned off, and after a delay value, the corresponding delay signal (Di) is charged to the VHH signal, so that the selected word line (WLi is taken as an example in fig. 4) is effectively discharged. After all word lines are discharged, the Discharge signal (Discharge) starts to be pulled down, and at this time, the selected address signal (Vj) is charged to a high potential (i.e., the read operation potential VCC or the write operation word line potential VHH described earlier), and at the same time, the selected control signal (Fi) and the delay signal (Di) are pulled down to a 0 potential, so that the selected word line potential is raised to a high potential (WLj is taken as an example in fig. 4, and the potential is VCC or VHH). The selected bit word line cells in the memory array perform corresponding read/write operations based on the word line and bit line potentials. The entire sequence above is thus a complete operation when the row decoder circuit switches from address ADD0 to ADD 1. From the above, the row decoder disclosed by the application has the advantages of simple time sequence operation, low chip cost and the like, and is suitable for being applied to a memory circuit.
Fig. 5a to 5d are schematic diagrams illustrating the implementation of the memory row decoder according to the embodiments of the present application. In one embodiment of the present application, the MRAM circuit 256 address lines are described in detail. As shown in fig. 5a to 5d, the schematic diagram of the present application mainly includes 1 read/write operation selector (controlled by WEN signal), 2 4-16 decoders (selecting decoder 110, pre-decoder 120 combined with main decoder 130), 33 driving modules 150 (selecting decoder 110 requires 16 outputs, main decoder 130 requires 16 outputs, and the read/write operation selector requires 1, 33 total) and 16 word line driving circuits 140. The generation of VCC (preferably VCC level consistent with low voltage device supply level) and VHH circuitry (i.e., one implementation of driver module 150) using op-amps in combination with bandgap reference signals is also shown. The potential VCC and the potential VHH are obtained by converting reference voltages VREF in the memory circuit through operational amplifiers (Operational Amplifier, OPA) of different specifications.
In some embodiments, the low bit word lines ADD0 to ADD3 (the first group of bit address lines 210) decode VSELs 0 to VSEL15, and a part of 16 VSEL signal lines raise a certain high potential VCC to VHH through a potential conversion circuit to control whether the address selection signals (Vj) and VHH are turned on or not; the other 16 VSELs transmit a high Voltage (VCC) to the address signal (Vj) through the driving circuit and the PMOS tube, wherein the selected voltage of the address signal (Vj) is VHH or VCC depends on the WEN signal. When the WEN signal is at a high level (writing operation is performed on the selected cell), the corresponding address signal (Vj) is at a VHH level, and when the WEN signal is at a low level (reading operation is performed on the selected cell), the corresponding address signal (Vj) is at a VCC level (only one signal is at a high level in normal operation, and the potential value is VHH or VCC).
In some embodiments, the high bit word lines ADD 4-ADD 7 (second group of bit address lines 220) decode XSEL 0-XSEL 15, undergo potential conversion and signal conditioning by the potential converter 160 to form control signals F0-F15 (only one signal is low during normal operation), and the delay signals D0-D15 are obtained by the timing module 143 to finally charge the selected cell bit line potential to the potential of the address signal (Vj). Further, the selected cell word line is a VHH potential value during a write operation; the selected cell word line is at VCC level during a read operation.
According to the method, through the change of the component connection structure, all the word line driving circuits are controlled by a single main decoder, the discharge signal control lines are only used for controlling the address selection and signal clearing of the selection decoder and the front decoder, the word line control ends of all the word line driving circuits are controlled by the respective time sequence modules, and the discharge signal control lines are connected to the word line control ends of all the word line driving circuits, so that the circuit scale can be selectively reduced, the information driving capability is reduced on the premise of maintaining the address selection information, and the chip cost is relatively reduced. And secondly, through the delay module, the word line selection signals of all the tri-state gate transmission circuits are obtained by delaying the output signals of the potential converter, the time sequences of the two signals are relatively fixed, the situation that the signals are delayed mutually is avoided, meanwhile, the situation that the prior selected word line is discharged and charged simultaneously is avoided, and the dynamic power consumption of the row decoding circuit can be reduced. Moreover, the unselected word lines greatly reduce the influence of the falling edge of the delay signal on the word lines due to the strong discharging capability of the N-type field effect transistor, thereby increasing the reliability of word line selection and operation. The row decoder disclosed by the application has the advantages of simplicity in operation, low chip cost, high reliability and the like, and is suitable for a memory circuit. .
The terms "in an embodiment" and "in various embodiments" and the like are used repeatedly. This phrase generally does not refer to the same embodiment; but it may also refer to the same embodiment. The terms "comprising," "having," "including," and the like are synonymous, unless the context clearly dictates otherwise.
The foregoing description is only illustrative of the present application and is not intended to be limiting, since the present application is described in terms of specific embodiments, but rather is not intended to be limited to the details of the embodiments disclosed herein, and any and all modifications, equivalent to the above-described embodiments, may be made without departing from the scope of the present application, as long as the equivalent changes and modifications are within the scope of the present application.
Claims (10)
1. A row decoder for a memory, adapted for use in a mram chip architecture, the selected word lines and bit lines being connected by control of the row decoder and column decoder, the row decoder comprising:
the input end of the selection decoder is connected with a first group of bit address lines;
the input end of the pre-decoder is connected with a second group of bit address lines;
a discharge signal control line electrically connected to the control ends of the selection decoder and the front decoder;
the input end of the main decoder is connected with the output end of the front decoder;
the selection decoder, the front decoder and the main decoder are of a multi-to-multi decoder structure;
a plurality of word line driving circuits, each word line driving circuit comprising:
a potential converter connected to an output terminal of the main decoder for converting a low logic level signal suitable for a core device output from the main decoder into a high logic level signal suitable for a peripheral device;
the input ends of the three-state gate transmission circuits are electrically connected with the output end of the selection decoder correspondingly, and the address selection control ends of the three-state gate transmission circuits are connected with the output end of the potential converter;
the input end of the time sequence module is electrically connected with the address selection control ends of the three-state gate transmission circuits, and the output end of the time sequence module is connected with the word line selection control ends of the three-state gate transmission circuits;
the driving module is arranged between the selection decoder and the plurality of word line driving circuits and is used for switching each output voltage of the selection decoder at different potentials according to control information;
the main decoder drives the selected word line driving circuit according to the address selecting signal output by the pre-decoder, and the selected word line driving circuit enables the tri-state gate transmission circuit of the selected word line driving circuit to read or write bit word line data through the output information of the selected decoder and the driving module; the timing module coordinates signal timing delays of the address selection control end and the word line selection control end of the plurality of tri-state gate transmission circuits to be within a delay value.
2. The row decoder of claim 1, wherein the output terminals of the pre-decoder all output low voltages when the discharge signal control line outputs an active control signal, and the main decoder is controlled to make all output terminals output high voltages to pull all word lines low.
3. The row decoder of claim 1, wherein when the discharge signal control line outputs an inactive control signal, the pre-decoder controls the main decoder according to a bit address line signal provided by the second set of bit address lines to drive a corresponding word line driving circuit, and a potential converter of the corresponding word line driving circuit outputs a high potential.
4. The column decoder of claim 1, wherein when the discharge signal control line outputs an inactive control signal, the select decoder outputs an address signal to the plurality of word line driving circuits according to the bit address line signals provided by the first set of bit address lines, and the driving module selectively adjusts the potential of the address signal to be a read operation word line potential or a write operation word line potential.
5. The row decoder of claim 4, wherein said write operation word line potential is higher than said read operation word line potential.
6. The row decoder of claim 1, wherein each tri-state gate transmission circuit includes a signal transmission gate and a word line control transistor, a control terminal of the signal transmission gate is electrically connected to one of the output terminals of the driving module, a control terminal of the signal transmission gate is connected to the input terminal of the timing module, a control terminal of the word line control transistor is connected to the output terminal of the timing module, a drain electrode of the word line control transistor is connected to a corresponding word line, and an output terminal of the signal transmission gate is connected to the drain electrode of the word line control transistor.
7. The row decoder of claim 6, wherein said signal transfer gate is comprised of a P-type field effect transistor and an N-type field effect transistor, said word line control transistor is an N-type field effect transistor, wherein the signals received by the P-type field effect transistor and the N-type field effect transistor of said signal transfer gate are inverted.
8. The row decoder of claim 1, wherein the timing module comprises a nand logic gate and an inverter, two input terminals of the nand logic gate are connected with one output terminal of the potential converter, one of the two input terminals is provided with a delay unit, the output terminal of the nand logic gate is connected with the input terminal of the inverter, and the output terminal of the inverter is connected with the word line selection control terminals of the plurality of tri-state gate transmission circuits; the timing module has an inverting function, so that the corresponding word line discharging capability and voltage signal transmission capability are completed.
9. The row decoder of claim 8, wherein said delay cells are comprised of an even number of inverters.
10. The method for controlling the timing of a row decoder of a memory as claimed in claim 1, comprising:
when address information reaches the row decoder, the output of all potential conversion modules controlled by the selection decoder is pulled down to low potential according to the discharge signal, and meanwhile, the output of all drivers controlled by the front decoder and the main decoder is pulled down to low potential, so that a transmission gate controlled by a control signal is gradually turned off;
after the delay value, charging delay signals corresponding to all address information to high potential signals, thereby discharging all word lines;
when all word lines are discharged, the discharging signals are pulled down, the selection decoder controls the corresponding potential conversion module to output to be pulled up to high potential according to the address signals, meanwhile, the front decoder and the main decoder control the corresponding driver to output to be pulled up to high potential, so that the transmission gates controlled by the control signals are gradually opened, the output signals of the corresponding potential converter modules are transmitted to the corresponding word lines, and the potential of the selected word lines is raised to high potential;
and the selected units in the memory array realize correct configuration of the potential of the word line according to the read/write operation.
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