CN112649667A

CN112649667A - Frequency sweeping device and method for chip and electronic equipment

Info

Publication number: CN112649667A
Application number: CN201910960398.6A
Authority: CN
Inventors: 严献平; 杨鑫
Original assignee: Bitmain Technologies Inc
Current assignee: Bitmain Technologies Inc
Priority date: 2019-10-10
Filing date: 2019-10-10
Publication date: 2021-04-13
Anticipated expiration: 2039-10-10
Also published as: CN112649667B

Abstract

The embodiment of the application discloses a frequency sweeping device and method of a chip and electronic equipment, which can improve the working frequency and computing power of the chip while ensuring the balanced work of multiple chips. The frequency sweeping device of the chip comprises: the circuit board comprises N groups of chips, a plurality of voltage domains and a plurality of voltage domains, wherein each group of chips in the N groups of chips comprises at least one chip, and M, N is a positive integer greater than 1; and the controller is connected with the N groups of chips and used for performing frequency sweep test on the N groups of chips to determine the highest frequency of each chip in the N groups of chips and determining the working frequency of each chip in the N groups of chips according to the highest frequency of each chip in the N groups of chips, wherein the sum of the working frequencies of the chips in at least two voltage domains in the M voltage domains is the same.

Description

Frequency sweeping device and method for chip and electronic equipment

Technical Field

The present application relates to the field of chip technologies, and more particularly, to a frequency sweeping apparatus and method for a chip, and an electronic device.

Background

With the development of information technology, the computational power requirement of a chip for performing data operation processing is continuously and rapidly increased in the fields of Artificial Intelligence (AI), digital certificate processing and the like.

Currently, in some devices dedicated to data processing, a processor uses a plurality of chips to perform calculations, so as to increase the speed of data processing. Generally, a plurality of chips are swept to determine the uniform working frequency. If one of the chips has poor performance, the resulting barrel effect will cause the lower working frequency of other chips, which will affect the computational power of other chips, and thus the system performance of the device.

Therefore, how to solve the problem of the barrel effect caused by the poor performance of the chips during the frequency sweeping process, improve the working frequency and the calculation power of the chips, and ensure the working balance of the chips is a problem to be solved urgently.

Disclosure of Invention

The embodiment of the application provides a frequency sweeping device and method for a chip and electronic equipment, which can improve the working frequency and computational power of the chip while ensuring the balanced work of multiple chips.

In a first aspect, a frequency sweep apparatus for a chip is provided, including: the circuit board comprises N groups of chips, a plurality of voltage domains and a plurality of voltage domains, wherein each group of chips in the N groups of chips comprises at least one chip, and M, N is a positive integer greater than 1; and the controller is connected with the N groups of chips and used for performing frequency sweep test on the N groups of chips to determine the highest frequency of each chip in the N groups of chips and determining the working frequency of each chip in the N groups of chips according to the highest frequency of each chip in the N groups of chips, wherein the sum of the working frequencies of the chips in at least two voltage domains in the M voltage domains is the same.

According to the technical scheme, the highest frequency of each chip in N groups of chips is obtained through frequency sweep testing, the balance of chip operation between different voltage domains is considered on the basis of the highest frequency of each chip, the working frequency of each chip is determined, the sum of the working frequencies of the chips on at least two voltage domains is equal, the working frequency of the whole N groups of chips is improved on the basis of guaranteeing system balance, and therefore the computing power and performance of the whole N groups of chips are improved.

In one possible implementation, the controller is configured to: sorting the highest frequencies of the plurality of chips on each voltage domain in the M voltage domains according to the highest frequency of each chip in the N groups of chips;

and determining the highest frequency of the target chip as the working frequencies of a plurality of chips with the same serial number, wherein the highest frequency of the target chip is the smallest in the highest frequencies of the plurality of chips with the same serial number.

In one possible implementation, N chips are disposed on each of the M voltage domains, and the controller is configured to: sorting the highest frequencies of the N chips on each of the M voltage domains;

and determining the highest frequency of the target chip as the working frequency of the M chips with the same serial number, wherein the highest frequency of the target chip is the smallest in the highest frequencies of the M chips with the same serial number.

In one possible implementation, the controller is configured to: and sorting the highest frequencies of the N chips of each voltage domain in the M voltage domains into 1 to N according to the sizes, wherein the chips with the same highest frequency size are sorted according to the position sequence.

In one possible implementation, each of the N groups of chips includes M chips, and the M chips are respectively located in the M voltage domains.

In the implementation mode, the N chips on each voltage domain belong to N groups respectively, and when the N groups of chips are subjected to frequency sweep test in sequence, the chips on the same voltage domain are not subjected to frequency sweep test at the same time, namely, the chips on the same voltage domain cannot interfere with each other during frequency sweep, so that each highest frequency obtained by determination is more accurate.

In one possible implementation, the N groups of chips are arranged in N rows on the circuit board, and the chips in the M voltage domains are arranged in M rows on the circuit board.

In one possible implementation, the sum of the operating frequencies of the chips of each of the M voltage domains is the same.

In one possible implementation, the controller is configured to: and sequentially carrying out frequency sweep test on the N groups of chips, and determining the highest frequency of each chip in the N groups of chips.

In the implementation mode, the frequency sweep test is sequentially carried out on N groups of chips, the highest frequency of each chip in each group of chips is determined by taking the group as a unit, and compared with the frequency sweep test which is sequentially carried out on each chip in the N groups of chips, the frequency sweep test method can improve the test efficiency and reduce the test time.

In a possible implementation manner, the chips in the M voltage domains located in the same voltage domain are not subjected to the frequency sweep test at the same time.

In one possible implementation, the controller is configured to: and sequentially carrying out frequency sweep test on the N groups of chips according to the position sequence from the a group of chips in the N groups of chips, wherein a is more than or equal to 1 and less than or equal to N, and a is a positive integer.

In one possible implementation, the controller is configured to: for a kth group of chips in the N groups of chips, wherein k is more than or equal to 1 and less than or equal to N, and k is a positive integer, setting the test frequency of the kth group of chips as the ith test frequency in X test frequencies, and sending test data to the kth group of chips, wherein the X test frequencies are sequentially increased in an increasing manner, X is a positive integer greater than 1, i is more than or equal to 2 and less than or equal to X, and i is a positive integer;

and acquiring and judging whether the number of random numbers of W chips in the kth group of chips is within a first threshold range or not so as to determine the highest frequency of the W chips in the kth group of chips, wherein W is a positive integer, the W chips are chips which do not determine the highest frequency in the kth group of chips, and the random numbers are data generated after the W chips receive test data.

In one possible implementation, the controller is configured to: when the number of the random numbers of the W chips is judged to be within a first threshold range and i +1 is not more than X, performing frequency sweep test on the kth group of chips by adopting the i +1 test frequency in the X test frequencies;

judging that the number of the random numbers of the W chips is within a first threshold range, and when i +1 is greater than X, determining that the highest frequency of the W chips is the Xth test frequency in the X test frequencies;

and when the number of the random numbers of the first chip in the W chips is judged to be out of the range of the first threshold value, determining that the highest frequency of the first chip is the (i-1) th test frequency in the X test frequencies, and performing frequency sweep test on the kth group of chips by adopting the (i + 1) th test frequency in the X test frequencies.

In one possible implementation, the controller is further configured to: and setting the test frequency of the chips of the other groups except the kth group of chips in the N groups of chips as the first test frequency in the X test frequencies.

In one possible implementation, the controller is configured to:

for the kth group of chips in the N groups of chips, wherein k is more than or equal to 1 and less than or equal to N, and k is a positive integer, setting the test frequency of the kth group of chips as the jth test frequency in Y test frequencies, and sending test data to the kth group of chips, wherein the Y test frequencies are sequentially decreased progressively, Y is a positive integer more than 1, j is more than or equal to 2 and less than or equal to Y, and j is a positive integer;

In one possible implementation, the controller is configured to: judging that the number of the random numbers of the W chips is out of a first threshold range, and when j +1 is less than Y, performing frequency sweep test on the kth group of chips by adopting the j +1 test frequency in the Y test frequencies;

when the number of the random numbers of the W chips is judged to be out of the range of the first threshold value and j +1 is equal to Y, determining the working frequency of the W chips as the Y-th test frequency in the Y test frequencies;

and when the number of the random numbers of the first chip in the W chips is judged to be within a first threshold range, determining that the working frequency of the first chip is the jth test frequency in the Y test frequencies, and performing frequency sweep test on the kth group of chips by adopting the jth +1 test frequency in the Y test frequencies.

In one possible implementation, the controller is further configured to: and setting the test frequency of the chips of the other groups except the kth group of chips in the N groups of chips as the Yth test frequency in the Y test frequencies.

In a possible implementation manner, the frequency sweeping apparatus further includes: and the memory is used for storing the working frequency of each chip in the N groups of chips.

In one possible implementation, the data lines of the N groups of chips are connected in series.

In a second aspect, a frequency sweeping method for a chip is provided, which includes: testing N groups of chips to determine the highest frequency of each chip in the N groups of chips, wherein the N groups of chips are arranged on M voltage domains of a circuit board, each group of chips in the N groups of chips comprises at least one chip, and M, N is a positive integer greater than 1;

and determining the working frequency of each chip in the N groups of chips according to the highest frequency of each chip in the N groups of chips, wherein the sum of the working frequencies of the chips of at least two voltage domains in the M voltage domains is the same.

In a possible implementation manner, the determining the operating frequency of each chip in the N groups of chips according to the highest frequency of each chip in the N groups of chips includes:

sorting the highest frequencies of the plurality of chips on each of the M voltage domains according to the highest frequency of each chip in the N groups of chips;

In one possible implementation, N chips are disposed on each of the M voltage domains, and the sorting of the highest frequencies of the chips of each of the M voltage domains includes:

sorting the highest frequencies of the N chips of each of the M voltage domains;

the method for determining the highest frequency of the target chip as the working frequencies of a plurality of chips with the same serial number comprises the following steps:

In one possible implementation, the sorting the highest frequencies of the N chips on each of the M voltage domains includes:

and sorting the highest frequencies of the N chips on each voltage domain of the M voltage domains into 1 to N according to the sizes, wherein the chips with the same highest frequency size are sorted according to the position sequence.

In one possible implementation, the performing a frequency sweep test on the N groups of chips to determine the highest frequency of each chip in the N groups of chips includes:

and sequentially carrying out frequency sweep test on the N groups of chips, and determining the highest frequency of each chip in the N groups of chips.

In a possible implementation manner, the sequentially performing the frequency sweep test on the N groups of chips includes:

and sequentially carrying out frequency sweep test on the N groups of chips according to the position sequence from the a group of chips in the N groups of chips, wherein a is more than or equal to 1 and less than or equal to N, and a is a positive integer.

In a possible implementation manner, the sequentially performing the frequency sweep test on the N groups of chips and determining the highest frequency of each chip in the N groups of chips includes:

for the kth group of chips in the N groups of chips, wherein k is more than or equal to 1 and less than or equal to N, and k is a positive integer, setting the test frequency of the kth group of chips as the ith test frequency in the X test frequencies, and sending test data to the kth group of chips, wherein the X test frequencies are sequentially increased, X is a positive integer more than 1, i is more than or equal to 2 and less than or equal to X, and i is a positive integer;

In a possible implementation manner, the obtaining and determining whether the number of random numbers of W chips in the kth group of chips is within a first threshold range to determine the highest frequency of the W chips in the kth group of chips includes:

when the number of the random numbers of the W chips is judged to be within a first threshold range and i +1 is not more than X, performing frequency sweep test on the kth group of chips by adopting the i +1 test frequency in the X test frequencies;

In a possible implementation manner, the sequentially performing the frequency sweep test on the N groups of chips and determining the highest frequency of each chip in the N groups of chips further includes: and setting the test frequency of the chips of the other groups except the kth group of chips in the N groups of chips as the first test frequency in the X test frequencies.

judging that the number of the random numbers of the W chips is out of a first threshold range, and when j +1 is less than Y, performing frequency sweep test on the kth group of chips by adopting the j +1 test frequency in the Y test frequencies;

when the number of the random numbers of at least one chip in the W chips is judged to be out of a first threshold range and j +1 is equal to Y, determining the working frequency of the W chips as the Yth test frequency in the Y test frequencies;

In a possible implementation manner, the sequentially performing the frequency sweep test on the N groups of chips and determining the highest frequency of each chip in the N groups of chips further includes: and setting the test frequency of the chips of the other groups except the kth group of chips in the N groups of chips as the Yth test frequency in the Y test frequencies.

In one possible implementation, the frequency sweeping method further includes: and storing the working frequency of each chip in the N groups of chips.

In a third aspect, an electronic device is provided, including: such as the first aspect or the chip in any possible implementation manner of the first aspect.

In a fourth aspect, a frequency sweeping device for a chip is provided, which includes a processor and a memory, where the memory is used to store a program code, and the processor is used to call the program code to execute the frequency sweeping method in the second aspect or any possible implementation manner of the second aspect.

In a fifth aspect, a computer storage medium is provided for storing program code for performing the frequency sweep method of the second aspect or any possible implementation manner of the second aspect.

Drawings

FIG. 1 is a schematic block diagram of an electronic device to which the present application may be applied;

fig. 2 is a schematic block diagram of a chip frequency sweeping apparatus according to an embodiment of the present application;

FIG. 3 is a schematic flow chart diagram of a chip frequency sweeping method according to an embodiment of the present application;

FIG. 4 is a schematic diagram of operating frequencies of multiple chips on a force computing board according to an embodiment of the present application;

fig. 5 is a schematic structural diagram of a chip frequency sweeping apparatus according to an embodiment of the present application;

FIG. 6 is a schematic block diagram of another chip sweep apparatus according to an embodiment of the present application;

FIG. 7 is a schematic block diagram of another chip sweep apparatus according to an embodiment of the present application;

FIG. 8 is a schematic block diagram of another chip sweep apparatus according to an embodiment of the present application;

FIG. 9 is a schematic flow chart diagram of a chip frequency sweeping method according to an embodiment of the present application;

FIG. 10 is a schematic flow chart diagram of another chip frequency sweeping method according to an embodiment of the present application;

FIG. 11 is a schematic diagram of the highest frequency of N groups of chips according to an embodiment of the present application;

FIG. 12 is a schematic diagram of an ordering of N groups of chips according to an embodiment of the application;

FIG. 13 is a schematic diagram of operating frequencies of N groups of chips according to an embodiment of the present application;

FIG. 14 is a schematic flow chart diagram of a chip frequency sweeping method according to an embodiment of the present application;

FIG. 15 is a schematic flow chart diagram of another chip frequency sweeping method according to an embodiment of the present application;

FIG. 16 is a schematic flow chart diagram of another chip frequency sweeping method according to an embodiment of the present application;

FIG. 17 is a schematic flow chart diagram of another chip frequency sweeping method according to an embodiment of the present application;

FIG. 18 is a schematic flow chart diagram of another chip frequency sweeping method according to an embodiment of the present application;

fig. 19 is a schematic structural diagram of another chip sweep apparatus according to an embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be described below with reference to the accompanying drawings.

It should be understood that the specific examples are provided herein only to assist those skilled in the art in better understanding the embodiments of the present application and are not intended to limit the scope of the embodiments of the present application.

It should also be understood that, in the various embodiments of the present application, the sequence numbers of the processes do not mean the execution sequence, and the execution sequence of the processes should be determined by the functions and the inherent logic of the processes, and should not constitute any limitation to the implementation process of the embodiments of the present application.

It should also be understood that the various embodiments described in this specification can be implemented individually or in combination, and the examples in this application are not limited thereto.

Unless otherwise defined, all technical and scientific terms used in the examples of this application have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the present application is for the purpose of describing particular embodiments only and is not intended to limit the scope of the present application. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

First, a logical structure diagram of an electronic device capable of executing the embodiment of the present application is described. The electronic device may be a processing device of a digital certificate, or may be other electronic devices for performing operation processing on a dedicated service, for example, a computing server, a communication device, a high-performance personal computer, and the like, which is not limited in this embodiment of the present application.

As shown in fig. 1, the electronic device 10 may include a power module 110, a processing module 120, a control module 130, a storage module 140, an interface module 150, and a heat dissipation module 160. It should be understood that the components of electronic device 10 may have fewer or more components than shown, or a different configuration of components. The various components shown in fig. 1 may be implemented in hardware, software, or a combination of hardware and software, including one or more signal processing and/or application specific integrated circuits.

The power module 110 is used for providing power to other modules in the electronic device 10, and may include an AC-to-DC converter (AC-to-DC converter), a DC-to-DC converter (DC-to-DC converter), and a Low Dropout Regulator (LDO) for outputting different DC voltages to meet voltage requirements of different chips and circuits.

The processing module 120 is a calculation processing module for dedicated calculation, which may include a plurality of chips for running calculation. When the electronic module 10 is a processing device of a digital certificate, the processing module 120 may include one or more computation boards (also referred to as computation boards), and a plurality of chips (chips), also referred to as Integrated Circuits (ICs), arranged in an array on the one or more computation boards for performing hash operation to solve the hash value, thereby obtaining the digital certificate.

In the processing module 120, data lines of a plurality of chips are connected in series, data obtained by operations of the plurality of chips are transmitted to the control module 130 through the data lines, in other words, data obtained by operations of the plurality of chips are transmitted to the control module 130 through one data transmission interface, and the operation data of the plurality of chips are sequentially transmitted to the control module 130 through the one data transmission interface, instead of the data lines of each chip being connected to the control module 130 and synchronously transmitted to the control module 130.

In addition, in the processing module 120, the plurality of chips are distributed over a plurality of voltage domains, which are connected in parallel, instead of being distributed over the same voltage domain. By adopting the design mode of the multiple voltage domains, chips on different voltage domains are not influenced mutually, and the working stability and reliability of the multiple chips are improved.

Optionally, the chip on the computing board may be any one of an Application Specific Integrated Circuit (ASIC) chip, a Graphics Processing Unit (GPU) chip, a Central Processing Unit (CPU) chip, and a Field Programmable Gate Array (FPGA) chip, which is not limited in this embodiment.

The control module 130 may be a System on a Chip (SOC) for connecting other modules in the electronic device 10 to ensure the orderly communication and data communication among the modules. The control module 130 may include a Microcontroller (MCU), a Microprocessor (Microprocessor), a Digital Signal Processor (DSP), an Analog-to-Digital converter (ADC), a Digital-to-Analog converter (DAC), an Oscillator (Electronic Oscillator) and a Phase Locked Loop (PLL) for providing a time pulse Signal, and the like.

The control module 130 may generate different clock signals through a clock circuit such as a phase-locked loop, so as to control the plurality of chips in the processing module 120 to operate at different operating frequencies. In addition, the control module 130 may also generate test data through circuits such as a microcontroller and a microprocessor, transmit the test data to a plurality of chips in the processing module 120, receive random data generated by the plurality of chips, and process the random data. In other words, the control module 130 may be used to control the operation of the plurality of chips in the processing module 120 and receive and process data of the plurality of chips.

In addition, the control module 130 may be connected to an external network through a network port, and the control module 130 may be configured through the network port, so as to control the operation of the electronic device 10.

The memory module 140 may include one or more Double Data Rate synchronous dynamic random access memory (DDR SDRAM), flash memory (flash), etc. memory units for storing Data and software programs in operation. Wherein the software program is used to control the operation of the hardware modules in the electronic device 10.

In particular, the software programs in the storage module 140 include an Operating System (OS) for controlling and managing conventional System tasks such as memory management, storage control, and power management, among others, as well as various software components and/or drivers that facilitate communication between various software and hardware, as well as a set of communication instructions, among others. The operating system includes but is not limited to: and embedded operating systems such as Linux, Unix, Windows or Vxworks and the like. The communication instruction set includes software components for processing data received via the interface module 150 to facilitate communication with other devices via the interface module.

The Interface module 150 may include various connection interfaces, such as Universal Serial Bus (USB), Ethernet (ETH), Universal Asynchronous Receiver/Transmitter (uart), Serial Peripheral Interface (SPI), and the like, for connecting various external devices directly or via a network.

In addition, the electronic device 10 further includes a heat dissipation module 160, and the heat dissipation module 160 may be a Fan (Fan), a water cooling system or other devices for dissipating heat from the electronic device 10. The power module 110 is used for supplying power to the heat dissipation module 160, and the control module 130 is used for controlling the heat dissipation module 160 to operate.

In the electronic device 10, the processing speed and the processing capability of the computing task depend on the processing module 120. In particular, in a digital certificate processing device, the system performance of the device depends for the most part on the computing power of the computing board, i.e., the speed at which the computing board computes the hash function output. The computing power of the computing power board is determined by the computing power of a plurality of chips on the computing power board, and the computing power of each chip on the computing power board influences the overall system performance of the equipment. In addition, the calculation power of the chip is closely related to the working frequency of the chip, and the higher the working frequency is, the more times are calculated per second, and the stronger the calculation power of the chip is.

In general, the frequency of operation of a plurality of chips on an algorithm board can be obtained through frequency sweep test. Due to different factors such as manufacturers and manufacturing processes of a plurality of chips, the performance of different chips may be different, that is, the highest operating frequency of different chips is different, and when a chip operates at a frequency exceeding the highest operating frequency, the chip may be abnormal. In the prior art, all chips on a force calculation plate are subjected to unified frequency sweep test, and all chips work under the same working frequency.

Fig. 2 shows a conventional chip sweep apparatus, and as shown in fig. 2, the chip sweep apparatus 200 includes a controller 210, a force computation board 220, and a power supply 230. The computation board 220 is provided with a plurality of chips IC, and the computation board 220 may be one example of the processing module 120, or may be another electrical component that carries a plurality of chips and provides electrical connection for the plurality of chips. The controller 210, which may be one example of the control module 130, is a system chip of the frequency sweeping device 200, or other electrical components with control functions, and may control operations of a plurality of chips on the force computing board 220. The power supply 230 is used to supply power to the electrical devices on the chip sweep apparatus 200, and may be one of the power supply modules described above.

As shown in fig. 2, a plurality of chips are arranged in an X-row Y-column array on an algorithm board 220. Optionally, in one embodiment, Y chips are located in one voltage domain per row, and X voltage domains are distributed on the computing board 220 in X rows, where X and Y are positive integers greater than 1.

Specifically, Y chips in one voltage domain are connected in parallel to supply power by using one voltage domain, and chips in different voltage domains are supplied by using different voltage domains, in other words, chip voltages in different voltage domains do not affect each other, but chip voltages in the same voltage domain affect each other.

Optionally, the voltages of the X voltage domains may be the same or different, and controlling multiple chips by different voltage domains can improve the stability of the force computing board 220, so that the power supply voltage of the entire force computing board is uniform.

In addition, the data lines of the Y chips on one voltage domain are connected in series for transmitting data signals. And the head chip and the tail chip on one voltage domain are respectively connected with the chips on the adjacent voltage domains to transmit data signals. For example, as shown in FIG. 2, the first chip IC of the second row_2,1With the first chip, i.e. IC, of the next row_3,1Connecting the last chip IC of the second row_2,YWith the last chip, i.e. IC, of the previous row_1,YAnd (4) connecting.

When Y chips in a voltage domain are connected in parallel and powered by the same voltage source, if one of the chips has poor performance, the highest operating frequency of the chip is low, and if the controller 210 operates at a frequency higher than the highest operating frequency, the chip is abnormal, and the power supply voltage of the whole voltage domain may be reduced, so that all other chips in the voltage domain cannot operate normally.

For the chip frequency sweeping device 200, the embodiment of the present application provides a chip frequency sweeping method 20, which sweeps to obtain the operating frequencies of a plurality of chips on the force calculation board 220. Alternatively, the execution subject of the frequency sweeping method 20 may be the controller 210 described above.

Fig. 3 shows a flow chart of the chip sweep method 20.

S210: setting the frequencies of a plurality of chips on the force calculation plate as an ith test frequency F_i。

Specifically, the controller sets the test working frequency of a plurality of chips on the force calculation board to the ith test frequency F_iThe ith test frequency F_iFor W test frequencies F₁～F_wThe ith test frequency of the test points is increased from small to large, W is a positive integer greater than 1, i is greater than or equal to 1 and is less than or equal to W, i isA positive integer.

S220: test data (pattern) is sent to the plurality of chips.

Specifically, the controller sends one or more test data to a plurality of chips, each of the plurality of chips receives the same one or more test data and performs an operation on the one or more test data, and in the process, the plurality of chips send the result of the operation to the controller 210, wherein the operation result may be a random number (nonce) generated by the chip for the one or more test data or operation data such as a hash value, and the random number is a random number of a random number in the hash operation and ranges from 0 to 2³²And other numerical ranges, which are not limited by the embodiments of the present application. And performing multiple Hash operations on the test data to obtain multiple random numbers, wherein the larger the number of the random numbers generated in unit time is, the stronger the computing power of the chip is, namely, the higher the computing power of the computing power board is.

S230: and receiving and judging whether the number of the random numbers generated by the plurality of chips is within a threshold value range.

Specifically, when the chip works normally, the number of random numbers generated in the working process of the chip is relatively large in a unit time, and when the chip works abnormally, the number of random numbers generated in the working process of the chip is relatively small in the unit time. Therefore, a threshold range can be set for the whole of the plurality of chips, and when the number of random numbers generated by the plurality of chips is within the threshold range, the calculation power of the plurality of chips at this time can meet the requirement. Alternatively, a threshold range may be set for each of the plurality of chips, and it may be determined whether the number of random numbers generated by each chip is within the threshold range, and if the number of random numbers is within the threshold range, it may indicate that the chip is operating normally, and if the number of random numbers is outside the threshold range, it may indicate that the chip is operating abnormally.

In addition, the random numbers generated by the plurality of chips are transmitted to the controller through the data lines connected in series, the controller receives the number of the random numbers output by each chip in the plurality of chips, and the number of the random numbers output by each chip in the plurality of chips can be judged whether to be within the threshold range or not.

S241: if the number of the random numbers is in the threshold range, adding 1 to i, and adopting the (i + 1) th test frequency F_i+1And carrying out frequency sweep test on a plurality of chips on the force calculation plate.

Specifically, when the number of random numbers output by each of the plurality of chips is within a threshold range, each chip works normally, or when the number of random numbers output by the whole plurality of chips is within the threshold range, the computing power of the computing board meets the requirement, and at this time, the controller sets the test working frequency of the plurality of chips on the computing board to be the (i + 1) th test frequency F_i+1The i +1 th test frequency F_i+1＞F_iUsing the i +1 th test frequency F_i+1The sweep test is performed on a plurality of chips on the force calculation board, and the process may refer to steps S210 to S230.

S242: if the number of the random numbers is out of the threshold range, determining the working frequency of the chips as the i-1 test frequency F_i-1。

Specifically, when the number of random numbers output by any one of the plurality of chips is out of the threshold range or the number of random numbers output by the whole plurality of chips is out of the threshold range, ending the frequency sweep test, and determining the working frequency of the plurality of chips on the force computing board as the i-1 test frequency F_i-1. That is, after the sweep test is finished, in the normal working process of the chips on the force calculation board, the working frequency of the chips is F_i-1。

It should be understood that, regarding the arrangement of the voltage domains on the force computing board 220 in fig. 2, in another embodiment, each column of X chips may be located on one voltage domain, and Y voltage domains are longitudinally distributed on the force computing board 220. The frequency sweep method 20 described above is also applicable to the force calculation board in this embodiment, and will not be described here.

Because a plurality of chips in the same voltage domain on the computation board use one voltage source in parallel, if only one chip is abnormal in the same voltage domain, all the chips in the voltage domain may work abnormally, which causes a large influence. Therefore, during the frequency sweepIn the process, if the frequency F is tested_iIf the frequency of a chip exceeds the highest frequency of the chip, all chips in a voltage domain where the abnormal chip is located may be abnormal, the number of random numbers generated by the chips in the voltage domain is reduced, and at this time, the random numbers of the whole plurality of chips may not reach the threshold range; or, during the frequency sweep, only one chip is at the test frequency F_iThe lower working is abnormal, the random number is not in the threshold range, and the working frequency of all chips on the force calculation board is less than the test frequency F_i。

FIG. 4 shows a schematic diagram of the operating frequency of multiple chips on an exemplary computing force board.

As shown in FIG. 4, the computing board has 6 rows and 10 columns of chips, wherein the chip IC of the 2 nd row and the 3 rd column_2,3When a multi-chip on the force computing board is subjected to frequency sweep test for a chip with poor performance on the force computing board, an IC_2,3And working abnormally at the test frequency of over 250MHz, wherein the working frequencies of 60 chips on the force calculation plate obtained according to the frequency sweep method 20 are all 250 MHz.

In summary, when the controller 210 performs the frequency sweep test on the plurality of chips on the computation force plate 220 by using the frequency sweep method 20, the finally determined unified operating frequency of the plurality of chips is the normal operating frequency of the worst-performance chip among the plurality of chips, and none of the other chips reaches the highest operating frequency of itself, that is, the optimal operating state is not reached. In other words, a chip with poor performance may form a barrel effect, so that the frequency sweeping method 20 cannot be used to determine the highest operating frequency of each chip on the force computing board, so that the force computing board reaches an optimal operating state, thereby affecting the performance of the entire system.

Based on this, the embodiments of the present application provide a frequency sweeping method and a frequency sweeping apparatus for a chip, which determine the highest frequency of the chip by performing frequency sweeping tests on a plurality of chips, reduce the influence of a chip with poor performance on other chips, avoid the chip from generating a barrel effect, and determine the operating frequency according to the highest frequency of the chip on the basis of ensuring the work balance of the plurality of chips, thereby improving the computational power and system performance of the plurality of chips.

Fig. 5 shows a schematic diagram of a chip frequency sweeping apparatus provided in an embodiment of the present application.

As shown in fig. 5, the chip sweep apparatus 300 includes:

n groups of chips 320 disposed on M voltage domains of the circuit board, wherein each of the N groups of chips 320 includes at least one chip, M, N is a positive integer greater than 1;

and the controller 310 is connected to the N groups of chips 320, and configured to perform a frequency sweep test on the N groups of chips 320 to determine a highest frequency of each chip in the N groups of chips 320, and determine an operating frequency of each chip in the N groups of chips 320 according to the highest frequency of each chip in the N groups of chips 320, where a sum of the operating frequencies of the chips in at least two voltage domains of the M voltage domains is the same.

Optionally, in this embodiment of the present application, the chips in the N groups of chips 320 may be the same as the chips in the processing module 120 in fig. 1, and may be any one of an ASIC chip, a GPU chip, a CPU chip, or an FPGA chip, and configured to perform data operation to implement various types of task data processing, such as various types of data processing of audio, video, image, signal, and digital.

Alternatively, as shown in FIG. 5, the M voltage domains V₁～V_MThe N groups of chips 320 may be arranged on the circuit board in N rows and N columns, and the N groups of chip ICs₁～IC_NM voltage domains V, as indicated by the dashed boxes in FIG. 5₁～V_MAs shown by the solid line box in fig. 5. Optionally, the M voltage domains may also be longitudinally arranged on the circuit board in M rows, and the N groups of chips may also be transversely arranged on the circuit board in N rows, which is not limited in this application. Hereinafter, the N groups of chips 320 are illustrated as being arranged in N rows in a longitudinal direction, and the technical solutions related to the transverse arrangement mode may refer to the longitudinal arrangement mode, which is not described herein again.

Optionally, the number of chips on each of the M voltage domains on the circuit board is equal.

In the circuit board shown in fig. 5, N groups of chips 320 include M times N (M × N) chips, each group of chips in the N groups of chips includes M chips, the M chips are respectively located on M voltage domains, N chips are arranged on each voltage domain in the M voltage domains, and the N chips respectively belong to different groups of chips. In other words, in the circuit board shown in fig. 5, different chips in each of the N sets of chips 320 are respectively located on different voltage domains.

Alternatively, as shown in FIG. 6, N sets of chip ICs₁～IC_a×NArranged in a longitudinal direction of a x N rows, each of the N groups of chips comprises a rows of chips, a is an integer greater than 1, and M voltage domains V₁～V_MAre arranged in M rows transversely. Specifically, each of the N groups of chips includes a × M chips respectively located on M voltage domains, and a × N chips are disposed on each of the M voltage domains, where M, N is a positive integer greater than 1.

Alternatively, as shown in FIG. 7, N sets of chip ICs₁～IC_NArranged in N rows and M voltage domains V₁～V_b×MThe chips are transversely arranged in b multiplied by M rows, each voltage domain in the M voltage domains is provided with b rows of chips, and b is an integer larger than 1. Specifically, each of the N groups of chips includes b × M chips respectively located on M voltage domains, and b × N chips are disposed on each of the M voltage domains, where M, N is a positive integer greater than 1.

In other words, in the frequency sweeping devices shown in fig. 6 and 7, part of the chips in each of the N groups of chips are located on the same voltage domain.

Similar to fig. 2, a plurality of chips located in the same voltage domain are connected in parallel and powered by the same power supply, and data lines of the plurality of chips in the N groups of chips are connected in series to transmit data signals.

Optionally, the number of chips in each of the M voltage domains on the circuit board may also be unequal.

For example, as shown in fig. 8, N groups of chips 320 are disposed on M voltage domains, where M, N is a positive integer greater than 1. Of M voltage domains, voltage domain V₁～V_M-1The number of the chips is the same, each chip has N chips, and the voltage domain V_MThe number of the upper chips is less than N,alternatively, there are only N-1 or less. In the embodiment of the present application, the circuit board is used for carrying the N groups of chips 320 and electrically connecting the N groups of chips 320.

It should be understood that the Circuit Board includes, but is not limited to, a Printed Circuit Board (PCB), a Flexible Printed Circuit Board (PFC), or a software integration Board (Soft and hard combination Board), which is not limited in the embodiments of the present application.

It should also be understood that, in the processing device of the digital certificate, the combination of the circuit board and the N groups of chips may also be referred to as an algorithm board, and the circuit board and the N groups of chips in the embodiment of the present application are not limited to the algorithm board in the processing device of the digital certificate, but may be a circuit board and N groups of chips in any scene, which is not limited in the embodiment of the present application.

Alternatively, the controller 310 may be one example of the control module 130 in fig. 1, a system chip of the frequency sweeping device 300, or other electrical components with control functions, and may control the N groups of chips 320 to operate.

Specifically, in this embodiment of the present application, when each group of chips in the N groups of chips 320 includes one chip, the controller 310 may be configured to perform a frequency sweep test on each chip, and obtain a highest frequency and an operating frequency of each chip, when each group of chips in the N groups of chips 320 includes a plurality of chips, the controller 310 may be configured to perform a frequency sweep test on the plurality of chips, determine the highest frequency of the plurality of chips in the same group, determine an operating frequency of each chip in the N groups of chips according to the highest frequency of each chip in the N groups of chips, and locate the plurality of chips in the same group in a plurality of different voltage domains, or locate part in the same voltage domain, and locate part in different voltage domains, and the sum of the operating frequencies of the chips located in the same voltage domain is equal.

In other words, the controller 310 does not perform frequency sweep test on all chips in the N groups of chips 320 at the same time to obtain a uniform operating frequency for all chips, but performs frequency sweep test on each chip in the N groups of chips, the highest frequencies of different chips in the N groups of chips may be the same or different, and the frequency sweep process of each chip is not affected by other chips, so that the frequency sweep test of a chip with poor performance in the N groups of chips does not affect the frequency sweep test of other chips, in other words, when performing frequency sweep test on other chips, the highest frequency obtained by the frequency sweep test of other chips is not lower due to the influence of the chip with poor performance. On the basis of the highest frequency of each chip, the balance of chip work among different voltage domains is considered, the working frequency of each chip is determined, and the sum of the working frequencies of the chips in different voltage domains is equal, so that the working frequency of the whole N groups of chips, and the computing power and performance of the whole N groups of chips are improved on the basis of ensuring the balance of a system.

Specifically, in this case, the controller 310 may perform the frequency sweep test on the N groups of chips by using the chip frequency sweep method 30.

Optionally, fig. 9 shows a schematic flow chart diagram of a chip frequency sweeping method 30.

S300: a frequency sweep test is performed on the N sets of chips to determine the highest frequency of each of the N sets of chips.

Optionally, the frequency sweep test may be performed on each chip in the N groups of chips in sequence, that is, after the frequency sweep test of the first chip is completed to determine the highest frequency of the first chip, the frequency sweep test may be performed on the second chip to determine the highest frequency of the second chip, until the frequency sweep test of all chips in the N groups of chips is completed to obtain the highest frequencies of all chips. In this embodiment, the chip order of the frequency sweep test is not limited in this embodiment.

In this case, when any one of the N groups of chips, for example, the first chip, is subjected to the frequency sweep test, the operating frequencies of the chips other than the first chip are the same, and the other chips all operate normally.

Optionally, the frequency sweep test may be performed on each group of chips in the N groups of chips in sequence to determine to obtain the highest frequency of each chip in each group of chips, for example, after the frequency sweep test is performed on a first group of chips in the N groups of chips to obtain the highest frequency of each chip in the first group of chips, the frequency sweep test is performed on a second group of chips in the N groups of chips to obtain the highest frequency of each chip in the second group of chips. By adopting the method, the frequency sweeping process of the multiple chips can be simplified, the time of frequency sweeping test is reduced, and the efficiency of frequency sweeping test is improved, which will be described in detail below.

S400: and determining the working frequency of each chip in the N groups of chips according to the highest frequency of each chip in the N groups of chips, wherein the sum of the working frequencies of the chips of at least two voltage domains in the M voltage domains is the same, and M, N is a positive integer greater than 1.

And after determining the highest frequency of each chip in the N groups of chips, determining the working frequency of each chip in the N groups of chips according to the condition of the sum of the working frequencies of the chips of at least two voltage domains in the M voltage domains, wherein the working frequency of each chip is less than or equal to the highest frequency of the chip.

Optionally, the highest frequencies of the plurality of chips in each of the M voltage domains are sorted according to the highest frequency of each chip in the N groups of chips, and the number of chips in each of the M voltage domains may be equal or different.

When the number of chips in each of the M voltage domains is not equal, for example, as in the chip sweep apparatus shown in FIG. 8, the highest frequencies of the chips in the M voltage domains are sorted, and the voltage domain V is₁～V_M-1The chip sequence on each voltage domain is 1-N, and the voltage domain V_MThe chips in the M voltage domains are sequenced into 1-N-1, the highest frequency of a target chip in the chips with the same serial number in the M voltage domains is taken as the working frequency of the chip with the same serial number, and the highest frequency of the target chip in the chips with the same serial number is the smallest. For example, the highest frequency of the first target chip is the smallest among the chips with the serial number of "1", and the highest frequency of the first target chip is set as the operating frequency of the chips with the serial number of "1"; similarly, among other chips with the same serial number, the target chip with the highest frequency is the smallest.

In the embodiment of the present application, after the operating frequency of each chip is determined by the above method, the voltage domain V is obtained₁～V_M-1Each inThe sum of the working frequencies of the chips on each voltage domain is equal, and the voltage domain V_MThe sum of the operating frequencies of the chips on the voltage domain is not equal to the sum of the operating frequencies of the chips on the other voltage domain. At this time, although the system performance of the chip frequency sweeping device is not optimal, the working frequency can be determined according to the highest frequency of the chip on the basis of the working balance of most chips, so that the calculation power and the system performance of a plurality of chips are improved.

Next, a specific frequency sweeping method in the case where the number of chips in each of the M voltage domains is equal will be described in detail with reference to fig. 10 to 18. In particular, FIG. 10 shows a schematic flow diagram of a particular chip sweep method 30. The chip frequency sweeping method is suitable for the chip frequency sweeping device shown in FIG. 5.

As shown in fig. 10, the step S400 may specifically include:

s410: the highest frequencies of the N chips of each of the M voltage domains are ranked.

S420: and determining the highest frequency of the target chip as the working frequency of the M chips with the same serial number, wherein the highest frequency of the target chip is the smallest in the highest frequencies of the M chips with the same serial number.

Optionally, in step S410, the highest frequencies of the N chips in each of the M voltage domains are sorted into 1 to N according to size, wherein the chips with the same highest frequency size are sorted according to the position order.

For example, fig. 11 shows a maximum frequency diagram of an example of N groups of chips.

As shown in fig. 11, N groups of chips 320 are arranged on the circuit board in 6 rows and 10 columns, each row of chips is disposed on a voltage domain, and includes 6 voltage domains, each voltage domain has 10 chips, and the highest frequency of each chip in the N groups of chips is shown in the figure, wherein the unit of the highest frequency is MHz.

The chips in each voltage domain in the 6 voltage domains in fig. 11 are sorted according to the highest frequency, wherein the chips with the same highest frequency are sorted according to the sorting order, and the chips in each voltage domain are sorted in sequence according to the sorting rule, so as to obtain the sorting schematic diagram shown in fig. 12.

As shown in fig. 11 and 12, the first voltage domain V₁In the 10 chips above, the highest frequencies of the first 8 chips from left to right are all 320MHz, and the highest frequencies of the 9 th chip and the 10 th chip are 310MHz, so that the first 8 chips are sorted from left to right into 1 to 8, and then the last 2 chips are sorted from left to right into 9 to 10.

Optionally, here, the first 8 chips may also be sorted into 1 to 8 according to the arrangement order from right to left, or may also be sorted into x to x +7, where x is any integer, or is sorted into letters a to h; correspondingly, the last 2 chips are sorted from 9 to 10, or x +8 to x +9, or letters i to j in the order from right to left. It should be understood that, in the embodiment of the present application, the arrangement rule adopted by each voltage domain is the same, the chip arrangement serial number in each voltage domain is not repeated, but the sequencing range of the chips is the same. The embodiment of the present application does not limit the specific arrangement rule.

And after the highest frequency of the chips in each voltage domain is ranked according to the same ranking rule, determining the working frequency of the chips with the same sequence number.

For example, as shown in fig. 11 and 12, there are 6 chips with the same serial number in the N groups of chips, and the chips are respectively located in 6 voltage domains. For the 6 chips numbered "5", see the shaded portions in FIGS. 11 and 12, where the chip with the lowest frequency is the chip IC of the second row and the second column_2,2The chip is a target chip of a plurality of chips with serial number "5", the highest frequency of the chip is 310MHz, the highest frequency of other 5 chips is 320MHz, and the operating frequencies of the 6 chips with serial number "5" are all determined as the highest frequency of the target chip, namely 310 MHz.

According to the method, the working frequency is determined for other chips with the same serial number, and fig. 13 shows the working frequency schematic diagram of N groups of chips. As shown in fig. 13, the sum of the operating frequencies of the 10 chips in each voltage domain is the same, and the operating frequency of each chip in the N groups of chips does not exceed the highest frequency, so that the whole system operates in a balanced manner.

Comparing fig. 13 with fig. 4, the working frequencies of most chips on the circuit board in fig. 13 are all greater than 250MHz, and on the premise of ensuring the balanced work of the chips on each voltage domain on the circuit board, the working frequencies of the chips are greatly improved, the calculation power of the chips is improved, and thus the performances of the chips and the whole system are optimized.

It should be understood that, with the chip frequency sweeping device shown in fig. 6 and 7, the highest frequencies of a × N chips or b × N chips in each of the M voltage domains may also be sorted by a method similar to the above method, and the highest frequency of the target chip is determined as the operating frequency of the M chips with the same serial number, where the highest frequency of the target chip is the smallest among the highest frequencies of the M chips with the same serial number. For specific embodiments, reference may be made to the above description, which is not repeated herein.

Optionally, in step S300, a frequency sweep test may be performed on the N groups of chips in sequence to determine the highest frequency of each chip in the N groups of chips.

In the chip sweep apparatus 300 shown in fig. 5, each of the N groups of chips 320 includes M chips, and the M chips are respectively located in different voltage domains, whereas in the chip sweep apparatus 300 shown in fig. 6 and 7, each of the N groups of chips 320 includes a × M chips or b × M chips, wherein some of the chips in each group are located in the same voltage domain.

Because chips in the same voltage domain interfere with each other during the frequency sweep test, optionally, the chip frequency sweep device shown in fig. 5 is used to perform the frequency sweep test on only one chip of the N groups of chips each time, and the frequency sweep test is performed when N chips in the same voltage domain are different, in which case, the performance of the chip frequency sweep device 300 is optimal.

The following describes a detailed frequency sweeping method for the frequency sweeping device in fig. 5, and the frequency sweeping methods of the frequency sweeping devices in fig. 6 and fig. 7 may refer to related descriptions, which are not repeated herein.

Optionally, fig. 14 shows a schematic flow chart diagram of a chip frequency sweeping method 30.

As shown in fig. 14, the step S300 may specifically include the following steps.

S310: and sequentially carrying out frequency sweep test on the N groups of chips, wherein N is a positive integer greater than 1.

Optionally, in the frequency sweeping apparatus 300 shown in fig. 5, each group of chips includes M chips, where the M chips are respectively located in M voltage domains, and M is a positive integer greater than 1.

S320: the highest frequency of each chip in each group of chips is determined.

Optionally, in the process of sequentially performing the frequency sweep test on each group of chips in the N groups of chips, the frequency sweep test may be performed on the N groups of chips in any order, for example, the frequency sweep test is performed on the even groups of chips sequentially, and then the frequency sweep test is performed on the odd groups of chips sequentially. Or any other sequence, the frequency sweep test of each group of chips in the N groups of chips is completed in sequence, and the specific frequency sweep test sequence is not specifically limited in the embodiment of the application.

Optionally, in the process of sequentially performing the frequency sweep test on each group of chips in the N groups of chips according to the position order, the a-th group of chip ICs in the N groups of chips_aAfter the sweep frequency test is finished, determining the highest frequency of each chip in the a group of chips, and then carrying out IC (integrated circuit) test on the a +1 group of chips_a+1Or a-1 th group chip IC_a-1And performing frequency sweep test to determine the highest frequency of each chip in the a +1 th group of chips or the a-1 th group of chips. Wherein a is more than or equal to 1 and less than or equal to N, and a is a positive integer.

Optionally, the frequency sweep test may be performed from a first group of chips in the N groups of chips until the frequency sweep test on the nth group of chips is completed, or the frequency sweep test may be performed from the nth group of chips in the N groups of chips until the frequency sweep test on the first group of chips is completed; the frequency sweep test may also be performed from any one of the N groups of chips, for example, the frequency sweep test is performed from the a-th group of chips, and after the frequency sweep test is completed on the N-th group of chips, the frequency sweep test is performed on the first group of chips until the frequency sweep test on the a-1-th group of chips is completed.

Optionally, at oneIn a possible embodiment, X test frequencies F are used for each of the N groups of chips₁，F₂，……，F_XAnd performing frequency sweep test, wherein the X test frequencies are sequentially increased, and X is a positive integer greater than 1.

It should be noted here that the first test frequency F of the X test frequencies₁Lower, each chip in the N groups of chips is at the first test frequency F₁All work normally under the condition.

In the embodiment of the present application, a process of performing a frequency sweep test on any one group of chips in the N groups of chips, for example, a kth group of chips to determine a highest frequency of each chip in the kth group of chips, is described in detail below with reference to fig. 15 and 16, where k is greater than or equal to 1 and less than or equal to N, and k is a positive integer.

Fig. 15 shows a schematic flow diagram of a chip sweep method 30.

As shown in fig. 15, the steps S310 and S320 may specifically include the following steps.

S311: setting the test frequency of the kth group of chips as the ith test frequency F in the X test frequencies_iWherein i is more than or equal to 2 and less than or equal to X, and i is a positive integer.

Specifically, the controller 310 controls the operation frequency of the kth chip group to be the ith test frequency F_i. Optionally, a controller 310 is connected to the clock line of each chip in the kth group of chips, the controller 310 generating the test frequency F with the ith frequency_iClock signal CLK_iAnd the clock signal CLK is transmitted via a clock line_iThe clock signals of each chip in the kth group of chips are CLK_i。

S312: and sending test data to the kth group of chips.

All chips in the k group work at a clock signal CLK_iThe controller 310 then sends the same test data to each chip in the kth group of chips. Specifically, after the controller 310 generates the test data, the test data is transmitted to each chip of the kth group of chips through the input signal line. After each chip receives the test data, it will calculate to generate multiple random numbersAnd other operational data.

Optionally, the test data and the random number in this step are the same as the test data and the random number described in step S220 in fig. 3, and related features may refer to the above description, which is not repeated herein.

S321: acquiring and judging whether the number of random numbers of W chips in a kth group of chips is within a first threshold range; wherein, W is a positive integer, W chips are chips with undetermined highest frequency in the kth group of chips, and the random number is data generated after the W chips receive the test data.

Specifically, the random number or other operation data generated by each chip may be sent to the controller 310 through an output signal line, and the controller 310 receives the random number or other operation data, determines the random number or other operation data of the W chips in the kth group, for which the highest frequency is not determined, and determines whether the random number or other operation data of the W chips is within the threshold range.

It should be noted that, when the frequency sweep test is performed on the kth chip group using the ith test frequency, if the highest frequency is determined for each chip in the kth chip group, in other words, W is equal to 0, the frequency sweep of the kth chip group is ended.

S322: and determining the highest frequency of the W chips according to the judgment result.

Specifically, the operating frequencies of the W chips are determined based on the above-described results of determining whether the number of random numbers or other operation data is within the threshold range.

Optionally, the sweep test is performed on the kth group of chips according to the arrangement sequence of the X test frequencies. After the frequency sweep test is performed on the kth group of chips by using the ith test frequency, the frequency sweep test is performed on the kth group of chips by using the test frequency greater than the ith test frequency, for example, the (i + 1) th test frequency.

Fig. 16 shows a schematic flow diagram of a specific chip sweep method 30.

As shown in fig. 16, in the chip sweep method 30, the steps S321 and S322 may specifically include the following steps.

S3210: and acquiring the number of random numbers of the kth group of chips.

Optionally, the number of random numbers of each chip of the kth group of chips is obtained.

Optionally, the number of random numbers of each of the W chips in the kth group of chips may also be obtained.

Specifically, the controller 310 receives each chip of the kth group of chips or each chip of the W chips at the ith test frequency F_iAnd (4) generating random numbers, and acquiring the number of the random numbers of each chip in the kth group of chips or each chip in the W chips.

S3211: judging whether the number of the random numbers of each chip in the W chips is within a first threshold range and i +1 is less than or equal to X;

s3221: and performing frequency sweep test on the kth group of chips by using the (i + 1) th test frequency in the X test frequencies.

S3212: judging whether the number of the random numbers of each chip in the W chips is within a first threshold range and when i +1 is larger than X;

s3222: and determining the highest frequency of the W chips as the Xth test frequency in the X test frequencies.

S3213: judging whether the number of the random numbers of a first chip in the W chips is out of a first threshold range;

s3223: and determining the highest frequency of the first chip as the (i-1) th test frequency in the X test frequencies.

Then, step S3221 is continuously performed: and performing frequency sweep test on the kth group of chips by using the (i + 1) th test frequency in the X test frequencies.

Specifically, the method obtains the ith test frequency F of each chip in the W chip_iAnd judging the number of the random numbers of each chip after the number of the random numbers.

When the number of the random numbers of each of the W chips is within a first threshold range, it indicates that each of the W chips normally works at the ith test frequency, and in this case, when i +1 is not more than X, that is, the i +1 th test frequency is the last test frequency F_XOr has not yet reached F_XAnd in the process, the frequency sweep test can be carried out on the kth group of chips by adopting the (i + 1) th test frequency, and whether the W chips normally work at the (i + 1) th test frequency is tested.

Similarly, when the W chips normally work at the (i + 1) th test frequency, the frequency sweep test is continuously carried out on the kth group of chips by adopting the (i + 2) th test frequency, and the frequency sweep test is sequentially carried out until the Xth test frequency F of the last test frequency is adopted_XAnd carrying out frequency sweep test on the kth group of chips. The subsequent method for performing frequency sweep test on the kth group of chips by using the (i + 1) th test frequency or even the xth test frequency is the same as the frequency sweep method 30, and is not described herein again.

Particularly, when the ith test frequency is the xth test frequency of the last test frequency, i.e. i +1 > X, the frequency sweep test is ended, and the highest frequency of the W chips is determined as the xth test frequency.

The above explains the case that the number of random numbers of each of the W chips is within the first threshold range, and relatively, when the number of random numbers of any one of the W chips, for example, the first chip is outside the first threshold range, it is said that the first chip operates abnormally at the ith test frequency, and the highest frequency of the first chip does not reach the ith test frequency.

In the embodiment of the application, the W chips are determined to be at the i-1 st test frequency F_i-1On the basis of normal working, the ith test frequency F is adopted_iPerforming frequency sweep test, wherein when the first chip of the W chips is at the ith test frequency F_iWorking abnormally, when working normally under the (i-1) th test frequency, determining the highest frequency of the first chip as the (i-1) th test frequency F_i-1。

Optionally, in the frequency sweep method 30, when performing the frequency sweep test on the kth group of chips in the N groups of chips, the test frequencies of the other groups of chips except the kth group of chips in the N groups of chips are set to be the same frequency. Optionally, the test frequency of the other groups of chips is set to be the first test frequency F1 in the X test frequencies, and each chip in the N groups of chips can normally operate at the test frequency F1, so that the test result is more accurate when the frequency sweep test is performed on the kth group of chips in the nth group of chips under the condition that the normal operation of the N groups of chips is ensured.

It should be appreciated that in the frequency sweep method 30 of the embodiment of the present application, the frequency sweep test can be performed from the second test frequency F during the frequency sweep test of the k sets of chips₂The frequency sweep test may be started from any one test frequency after the second test frequency, which is not limited in the embodiment of the present application.

It should also be understood that, when the number of random numbers of each of the W chips is determined, there may be a case where the numbers of random numbers of the plurality of the W chips are all outside the first threshold range, and the highest frequencies of the plurality of chips are determined at the same time.

It should be further understood that, after the frequency sweep test is performed on the kth group of chips by using the ith test frequency, if the highest frequency of the first chip is determined, in the process of performing the frequency sweep test on the kth group of chips by using the i +1 test frequencies, the first chip does not belong to the chip with the undetermined highest frequency, and the number of the random numbers of the first chip does not need to be obtained.

In addition, in the frequency sweep method 30 of the present application, a frequency sweep test is performed on the kth group of chips in the N groups of chips as an example, and the frequency sweep test method of other groups of chips in the N groups of chips may be the same as or different from the frequency sweep test method of the kth group of chips, which is not limited in the embodiment of the present application.

Optionally, in another possible implementation, Y test frequencies F are used for each of the N groups of chips₁，F₂，……，F_YAnd carrying out frequency sweep test, wherein the Y test frequencies are sequentially decreased, and Y is a positive integer greater than 1.

It should be noted here that the Y-th test frequency F of the Y test frequencies_YLower, each chip in the N groups of chips is at the Yth test frequency F_YAll work normally under the condition.

In the embodiment of the present application, a process of performing a frequency sweep test on any one of the N groups of chips, for example, the kth group of chips, is described in detail below with reference to fig. 17 and 18, where k is greater than or equal to 1 and less than or equal to N, and k is a positive integer.

Fig. 17 shows a schematic flow diagram of another chip sweep method 30.

As shown in fig. 17, the steps S310 and S320 may specifically include:

s313: and setting the test frequency of the kth group of chips as the jth test frequency Fj in the Y test frequencies, wherein j is more than or equal to 2 and less than or equal to Y, and j is a positive integer.

S314: and sending test data to the kth group of chips.

S323: acquiring and judging whether the number of random numbers of W chips in a kth group of chips is within a first threshold range; wherein, W is a positive integer, W chips are chips with undetermined highest frequency in the kth group of chips, and the random number is data generated after the W chips receive the test data.

S324: and determining the highest frequency of W chips in the kth group of chips according to the judgment result.

Specifically, the operating frequency of the kth group of chips is determined based on the above-described result of determining whether the number of random numbers or other operation data is within the threshold range.

Optionally, the steps S313 to S324 are similar to the steps S311 to S322 in fig. 14, and the related scheme may refer to the above description, which is not described herein again.

Optionally, the sweep test is performed on the kth group of chips according to the arrangement sequence of the Y test frequencies. After the jth test frequency is adopted to perform frequency sweep test on the kth group of chips, the test frequency lower than the jth test frequency, for example, the j +1 th test frequency, is adopted to perform frequency sweep test on the kth group of chips.

Fig. 18 shows a schematic flow diagram of a specific chip sweep method 30.

As shown in fig. 18, in the chip sweep method 30, the steps S323 and S324 may specifically include the following steps.

S3230: and acquiring the number of random numbers of the kth group of chips.

S3231: judging whether the number of the random numbers of each chip in the W chips is out of a first threshold range and j +1 is less than Y;

s3241: and performing frequency sweep test on the kth group of chips by adopting the j +1 th test frequency in the Y test frequencies.

S3232: judging whether the number of the random numbers of each of the W chips is out of a first threshold range and j +1 is equal to Y;

s3242: and determining the highest frequency of the W chips as the Yth test frequency in the Y test frequencies.

S3233: judging whether the number of random numbers of a first chip in the W chips is within a first threshold value range;

s3243: and determining the highest frequency of the first chip as the jth test frequency in the Y test frequencies.

Then, execution continues to step S3241: and performing frequency sweep test on the kth group of chips by adopting the j +1 th test frequency in the Y test frequencies.

Specifically, the j test frequency F of each of the W chips is obtained_jAnd judging the number of the random numbers of each chip after the number of the random numbers.

When the number of the random numbers of each of the W chips is out of the first threshold range, the W chips are indicated to work abnormally under the jth test frequency, and the highest frequency of the W chips does not reach the jth test frequency.

In this case, when j +1 < Y, i.e., the jth test frequency is greater than the Y-1 test frequency F_Y-1When testing the frequency, the frequency sweep test needs to be carried out on the kth group of chips by adopting the j +1 th test frequency, and whether the j +1 th test frequency is the highest frequency of the W chips is tested.

Similarly, when the W chips still can not work normally under the j +1 th test frequency, the frequency sweep test is continuously carried out on the kth group of chips by adopting the j +2 th test frequency, and the frequency sweep test is carried out in sequence until the Y-1 st test frequency F is adopted_Y-1And carrying out frequency sweep test on the kth group of chips. The subsequent frequency sweep test method for the kth chip set by using the (j + 1) th test frequency or even the (Y-1) th test frequency is the same as the frequency sweep method 30, and is not described herein again.

Particularly, when it isj test frequencies are the Y-1 test frequency F_Y-1When j +1 is Y, if the W chips are at the Y-1 test frequency F_Y-1When the chip still can not work normally, the sweep test is finished, and the highest frequency of the W chips is determined as the first test frequency F₁。

When the number of the random numbers of the first chip in the W chips is within a first threshold range, the first chip works normally under the jth test frequency, and the highest frequency of the first chip reaches the jth test frequency.

In the embodiment of the application, the test frequency F of the j-1 th chip is determined when the W chips are_j-1On the basis of lower working abnormity, adopting the jth test frequency F_jPerforming frequency sweep test, wherein when the first chip of the W chips is at the j-1 th test frequency F_j-1Lower operating anomaly at jth test frequency F_jWhen the lower work is normal, determining the highest frequency of the first chip as the jth test frequency F_j。

It should be understood that in the frequency sweep method of the embodiment of the present application, during the frequency sweep test of the k groups of chips, the 1 st test frequency F can be obtained_YThe frequency sweep test is started, and the test may also be started from any test frequency after the 1 st test frequency, which is not limited in the embodiment of the present application.

It should be further understood that, after the frequency sweep test is performed on the kth group of chips by using the jth test frequency, if the highest frequency of the first chip is determined, in the process of performing the frequency sweep test on the kth group of chips by using the j +1 test frequencies, the first chip does not belong to the chip with the undetermined highest frequency, and the number of the random numbers of the first chip does not need to be obtained.

It should also be understood that, when the number of random numbers of each of the W chips is determined, there may be a case where the numbers of random numbers of a plurality of the W chips are all within the first threshold range, and then the highest frequencies of the plurality of chips are determined at the same time.

Optionally, in the frequency sweep method 30, when performing the frequency sweep test on the kth group of chips in the N groups of chips, the test frequencies of the other groups of chips except the kth group of chips in the N groups of chips are set to be the same frequency.

Optionally, the test frequency of the other groups of chips is set to the Yth test frequency F in the Y test frequencies_YSince each chip in the N groups of chips is at the test frequency F_YTherefore, under the condition of ensuring the normal work of the N groups of chips, the frequency sweep test is carried out on the kth group of chips in the Nth group of chips, and the test result is more accurate.

Alternatively, fig. 19 shows a schematic block diagram of another chip sweep apparatus 300.

As shown in fig. 19, the chip sweep apparatus 300 further includes:

and a memory 330, wherein the memory 330 is used for storing the operating frequency of each of the N groups of chips 320, where N is a positive integer greater than 1.

Specifically, the memory 330 may be an example of the storage module 140 in fig. 1.

Optionally, the memory 330 may be used to store computer-executable instructions. The controller 310 is used to access the memory 330 and execute the computer-executable instructions to perform the operations of the chip sweep method according to the embodiment of the present application.

Specifically, the controller 310 sequentially performs a frequency sweep test on the N groups of chips 320, determines the operating frequency of each chip, and then sends the operating frequency of each chip to the memory 330, and the memory 330 stores the operating frequency. After the sweep test is completed, the controller 310 may read the operating frequency of each chip in the N sets of chips 320 from the memory 330 and control the N sets of chips 320 to operate according to the operating frequency.

Alternatively, the memory 330 may be two devices independent from the controller 310, or may also be a storage unit in the controller 310, or may also be a storage unit disposed on a circuit board on which the N groups of chips 320 are disposed, which is not limited in this embodiment of the application.

As shown in fig. 19, the chip sweep apparatus 300 may further include:

and the power supply 340, wherein the power supply 340 is used for supplying power to the chip frequency sweeping device 300.

Specifically, the power supply 340 may supply power to the controller 310, the N sets of chips 320, and the memory 330 for different devices and voltage requirements, where N is a positive integer greater than 1, in other words, the power supply 340 may include various voltage conversion circuits, such as an ac/dc conversion circuit or a dc/dc conversion circuit, etc., to generate multiple different voltages and connect to different devices and circuits on the chip sweep apparatus 300.

Alternatively, the power source 340 is a constant power module, which may be a constant dc or ac source module, and the controller 310, the circuit board where the N groups of chips 320 are located, and the memory 330 all include a voltage conversion circuit, which can convert the voltage of the power source 340 into a suitable device voltage to meet the operating requirement of the frequency sweeping apparatus 300.

It should be understood that the power source 340 may be a power source in the chip frequency sweeping device 300, or an external power source of the chip frequency sweeping device 300, which is not limited in this embodiment.

The embodiment of the application also provides electronic equipment, and the electronic equipment can comprise the device for sweeping the frequency of the chip in the various embodiments of the application.

The embodiment of the invention also provides a frequency sweeping device of the chip, which comprises a processor and a memory, wherein the memory is used for storing the program code, and the processor is used for calling the program code to execute the frequency sweeping method of the method embodiment.

Embodiments of the present invention also provide a computer storage medium having a computer program stored thereon, where the computer program, when executed by a computer, causes the computer to execute the method of the above method embodiments.

Embodiments of the present invention also provide a computer program product comprising instructions, which when executed by a computer, cause the computer to perform the method of the above method embodiments.

In the above embodiments, all or part of the implementation may be realized by software, hardware, firmware or any other combination. When implemented in software, may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When loaded and executed on a computer, cause the processes or functions described in accordance with the embodiments of the invention to occur, in whole or in part. The computer may be a general purpose computer, a special purpose computer, a network of computers, or other programmable device. The computer instructions may be stored on a computer readable storage medium or transmitted from one computer readable storage medium to another, for example, from one website, computer, server, or data center to another website, computer, server, or data center via wire (e.g., coaxial cable, fiber optic, Digital Subscriber Line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device, such as a server, a data center, etc., that incorporates one or more of the available media. The usable medium may be a magnetic medium (e.g., a floppy disk, a hard disk, a magnetic tape), an optical medium (e.g., a Digital Video Disk (DVD)), or a semiconductor medium (e.g., a Solid State Disk (SSD)), among others.

Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.

In the embodiments provided in the present invention, it should be understood that the disclosed system, apparatus and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the units is only one logical division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit.

The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.

Claims

1. A frequency sweeping device of a chip is characterized by comprising:

the circuit board comprises N groups of chips, a plurality of voltage domains and a plurality of voltage domains, wherein each group of chips in the N groups of chips comprises at least one chip, M is more than 1, N is more than or equal to 1, and M, N is a positive integer;

and the controller is connected with the N groups of chips and is used for performing frequency sweep test on the N groups of chips to determine the highest frequency of each chip in the N groups of chips and determining the working frequency of each chip in the N groups of chips according to the highest frequency of each chip in the N groups of chips, wherein the sum of the working frequencies of the chips in at least two voltage domains in the M voltage domains is the same.

2. A sweeping device as claimed in claim 1, wherein the controller is configured to:

sorting the highest frequencies of the plurality of chips on each voltage domain in the M voltage domains according to the highest frequency of each chip in the N groups of chips;

determining the highest frequency of a target chip as the working frequencies of a plurality of chips with the same serial number, wherein the highest frequency of the target chip is the smallest in the highest frequencies of the plurality of chips with the same serial number.

3. A sweeping device according to claim 2, wherein there are N chips provided on each of the M voltage domains, the controller being configured to:

sorting the highest frequencies of the N chips on each of the M voltage domains;

4. A sweeping device according to claim 3, wherein the controller is configured to:

and sorting the highest frequencies of the N chips of each voltage domain in the M voltage domains into 1 to N according to the sizes, wherein the chips with the same highest frequency are sorted according to the position sequence.

5. A sweeping device according to any one of claims 1 to 4, wherein each of the N sets of chips includes M chips, the M chips being respectively located in the M voltage domains.

6. A swept frequency device according to any one of claims 1-5, wherein the N groups of chips are arranged in N columns on the circuit board, and the chips on the M voltage domains are arranged in M rows on the circuit board.

7. A sweeping device according to any one of claims 1 to 6, wherein the controller is configured to:

8. A frequency sweeping device according to claim 7, wherein chips in the same voltage domain in the M voltage domains are not subjected to frequency sweeping testing at the same time.

9. A sweeping device according to claim 7 or 8, wherein the controller is configured to:

10. A sweeping device according to any one of claims 7 to 9, wherein the controller is configured to:

for a kth group of chips in the N groups of chips, wherein k is more than or equal to 1 and less than or equal to N, and k is a positive integer, setting the test frequency of the kth group of chips as the ith test frequency in X test frequencies, and sending test data to the kth group of chips, wherein the X test frequencies are sequentially increased in an increasing manner, X is a positive integer greater than 1, i is more than or equal to 2 and less than or equal to X, and i is a positive integer;

11. A sweeping device as claimed in claim 10, wherein the controller is configured to:

12. A sweeping device according to claim 10 or 11, wherein the controller is further configured to:

and setting the test frequency of the chips of the other groups except the kth group of chips in the N groups of chips as the first test frequency in the X test frequencies.

13. A sweeping device according to any one of claims 7 to 9, wherein the controller is configured to:

for a kth group of chips in the N groups of chips, wherein k is more than or equal to 1 and less than or equal to N, and k is a positive integer, setting the test frequency of the kth group of chips as a jth test frequency in Y test frequencies, and sending test data to the kth group of chips, wherein the Y test frequencies are sequentially decreased progressively, Y is a positive integer more than 1, j is more than or equal to 2 and less than or equal to Y, and j is a positive integer;

14. A sweeping device as claimed in claim 13, wherein the controller is configured to:

judging that the number of the random numbers of the W chips is out of a first threshold range, and when j +1 is smaller than Y, performing frequency sweep test on the kth group of chips by adopting the j +1 test frequency in the Y test frequencies;

when the number of the random numbers of the W chips is judged to be out of a first threshold range and j +1 is equal to Y, determining that the working frequency of the W chips is the Yth test frequency in the Y test frequencies;

15. A sweeping device according to claim 13 or 14, wherein the controller is further configured to:

and setting the test frequency of the chips of the other groups except the kth group of chips in the N groups of chips as the Yth test frequency in the Y test frequencies.

16. A sweeping device according to any one of claims 1 to 15, further comprising: and the memory is used for storing the working frequency of each chip in the N groups of chips.

17. A sweeping device according to any one of claims 1 to 16, wherein the data lines of the N groups of chips are connected in series.

18. A frequency sweeping method of a chip is characterized by comprising the following steps:

performing frequency sweep test on N groups of chips to determine the highest frequency of each chip in the N groups of chips, wherein the N groups of chips are arranged on M voltage domains of a circuit board, each group of chips in the N groups of chips comprises at least one chip, M is more than 1, N is more than or equal to 1, and M, N is a positive integer;

19. A frequency sweeping method as claimed in claim 18, wherein said determining the operating frequency of each chip in the N groups of chips based on the highest frequency of each chip in the N groups of chips comprises:

sorting the highest frequencies of the plurality of chips on each of the M voltage domains according to the highest frequency of each of the N groups of chips;

20. A frequency sweeping method as claimed in claim 19, wherein N chips are provided on each of the M voltage domains, and the sorting of the highest frequencies of the plurality of chips for each of the M voltage domains comprises:

the determining the highest frequency of the target chip as the working frequencies of a plurality of chips with the same serial number comprises:

21. A frequency sweeping method as claimed in claim 20, wherein said sorting the highest frequencies of the N chips on each of the M voltage domains comprises:

and sorting the highest frequencies of the N chips on each voltage domain of the M voltage domains into 1 to N according to the sizes, wherein the chips with the same highest frequency are sorted according to the position sequence.

22. A frequency sweeping method according to any one of claims 18 to 21, wherein each of the N groups of chips includes M chips, the M chips being respectively located in the M voltage domains.

23. A frequency sweeping method according to claim 22, wherein the N groups of chips are arranged in N columns on the circuit board, and the chips in the M voltage domains are arranged in M rows on the circuit board.

24. A frequency sweeping method according to any one of claims 18 to 23, wherein the performing frequency sweeping tests on N groups of chips to determine the highest frequency of each chip in the N groups of chips comprises:

25. A frequency sweeping method according to claim 24, wherein chips in the same voltage domain in the M voltage domains are not subjected to frequency sweeping testing simultaneously.

26. A frequency sweeping method according to claim 24 or 25, wherein the sequentially performing frequency sweeping tests on the N groups of chips comprises:

27. A frequency sweeping method according to any one of claims 24 to 26, wherein said sequentially performing frequency sweeping tests on said N groups of chips and determining the highest frequency of each chip in said N groups of chips comprises:

for a kth group of chips in the N groups of chips, wherein k is more than or equal to 1 and less than or equal to N, and k is a positive integer, setting the test frequency of the kth group of chips as the ith test frequency in the X test frequencies, and sending test data to the kth group of chips, wherein the X test frequencies are sequentially increased in an increasing manner, X is a positive integer greater than 1, i is more than or equal to 2 and less than or equal to X, and i is a positive integer;

28. A sweeping method according to claim 27, wherein the obtaining and judging whether the number of random numbers of W chips in the kth group of chips is within a first threshold range to determine the highest frequency of W chips in the kth group of chips comprises:

29. A frequency sweeping method according to claim 27 or 28, wherein the sequentially performing frequency sweeping tests on the N groups of chips and determining the highest frequency of each chip in the N groups of chips further comprises:

30. A frequency sweeping method according to any one of claims 24 to 26, wherein said sequentially performing frequency sweeping tests on said N groups of chips and determining the highest frequency of each chip in said N groups of chips comprises:

31. A sweeping method according to claim 30, wherein the obtaining and judging whether the number of random numbers of W chips in the kth group of chips is within a first threshold range to determine the highest frequency of W chips in the kth group of chips comprises:

32. A frequency sweeping method according to claim 30 or 31, wherein the sequentially performing frequency sweeping tests on the N groups of chips and determining the highest frequency of each chip in the N groups of chips further comprises:

33. A frequency sweeping method according to any one of claims 18 to 32, further comprising:

and storing the working frequency of each chip in the N groups of chips.

34. A sweeping method according to any one of claims 18 to 33, wherein the data lines of the N groups of chips are connected in series.

35. An electronic device, comprising:

a frequency sweeping apparatus for a chip as claimed in any one of claims 1 to 17.

36. A frequency sweeping apparatus for a chip, comprising a processor and a memory, the memory being configured to store program code, the processor being configured to invoke the program code to perform the frequency sweeping method of any one of claims 18 to 34.

37. A computer readable storage medium for storing program code for performing the frequency sweeping method of any one of claims 18 to 34.