CN112644180B - Chip starting method and device, storage medium and consumable chip - Google Patents
Chip starting method and device, storage medium and consumable chip Download PDFInfo
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- CN112644180B CN112644180B CN202011495015.1A CN202011495015A CN112644180B CN 112644180 B CN112644180 B CN 112644180B CN 202011495015 A CN202011495015 A CN 202011495015A CN 112644180 B CN112644180 B CN 112644180B
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B41—PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
- B41J—TYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
- B41J2/00—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed
- B41J2/005—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by bringing liquid or particles selectively into contact with a printing material
- B41J2/01—Ink jet
- B41J2/17—Ink jet characterised by ink handling
- B41J2/175—Ink supply systems ; Circuit parts therefor
- B41J2/17503—Ink cartridges
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B41—PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
- B41J—TYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
- B41J29/00—Details of, or accessories for, typewriters or selective printing mechanisms not otherwise provided for
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Abstract
The invention discloses a chip starting method, a device, a storage medium and a consumable chip, and relates to a main processing integrated circuit and a co-processing integrated circuit in a chip, wherein the main processing integrated circuit and the co-processing integrated circuit are connected in parallel, and the method comprises the following steps: monitoring the starting condition of the main processing integrated circuit through the co-processing integrated circuit; judging whether to adjust the level of a power supply circuit of the main processing integrated circuit according to the starting condition of the main processing integrated circuit; if so, the level of the power supply circuit is adjusted through the co-processing integrated circuit until the main processing integrated circuit is started. Therefore, the chip error report caused by the fact that the main processing integrated circuit misses the request communication with the external terminal due to the limitation of the starting speed is avoided, and the use cost of the chip is effectively reduced.
Description
Technical Field
The invention relates to the technical field of chip starting, in particular to a chip starting method, a chip starting device, a storage medium and a consumable chip.
Background
An imaging cartridge for use in a printer includes a consumable chip that can store imaging cartridge information. Generally, after the toner or ink of the imaging box is used, the imaging box and the consumable chips on the imaging box are discarded together, which causes unnecessary waste.
To prevent this waste, replacement chips have been introduced to replace consumable chips on used imaging cartridges, and the imaging cartridges are then filled with ink or toner for reuse or sold by installing replacement chips in replacement cartridges. Memory devices such as ROM, electrically erasable programmable read only memory EEPROM, static random access memory SRAM, or other suitable non-volatile memory devices are typically provided in the surrogate chip to store imaging cartridge information. The cartridge information may include a remaining amount of consumables, a version number, a commodity model, a brand, a serial number, and the like.
With the continuous development of printers, the requirement on the starting speed of the chip is higher and higher, the substitute chip needs to be updated synchronously with the technical update of the consumable chip, and if the substitute chip does not respond to the printer within the set time of printing starting, the printer considers that the substitute chip is an unavailable chip, so that the substitute chip easily misses the communication with the printer, the printer cannot detect the chip of the imaging box, an error report condition occurs, and the printing cost is increased.
Disclosure of Invention
The invention provides a chip starting method, a chip starting device, a storage medium and a consumable chip, and solves the technical problems that in the prior art, because the chip cannot be started smoothly within required starting time, the chip easily misses communication with an external terminal, and the chip error reporting condition occurs, so that the use cost of the chip is increased.
The invention provides a chip starting method, which relates to a main processing integrated circuit and a co-processing integrated circuit in a chip, wherein the main processing integrated circuit and the co-processing integrated circuit are connected in parallel, and the method comprises the following steps:
monitoring the starting condition of the main processing integrated circuit through the co-processing integrated circuit;
judging whether to adjust the level of a power supply circuit of the main processing integrated circuit according to the starting condition of the main processing integrated circuit;
and if so, adjusting the level of the power supply circuit through the co-processing integrated circuit until the main processing integrated circuit is started.
Optionally, the step of determining whether to adjust a level of a power supply circuit of the main processing integrated circuit according to a start-up condition of the main processing integrated circuit includes:
if the main processing integrated circuit is not started, judging that the level of a power supply circuit of the main processing integrated circuit is adjusted through the co-processing integrated circuit;
and if the main processing integrated circuit is started, closing the co-processing integrated circuit.
Optionally, the step of adjusting, by the co-processing integrated circuit, the level of the power supply circuit until the main processing integrated circuit is started up includes:
pulling down, by the co-processing integrated circuit, a level of the power supply circuit to a low level;
and keeping the low level of the power supply circuit through the co-processing integrated circuit until the main processing integrated circuit is started.
Optionally, after the main processing integrated circuit is started, the method further includes:
when the main processing integrated circuit receives a read request, a serial number corresponding to the read request is returned through the main processing integrated circuit;
after the main processing integrated circuit sends a serial number, receiving, by the main processing integrated circuit, an instruction as to whether the main processing integrated circuit is available.
The invention also provides a chip starting device, which is applied to a consumable chip, wherein the consumable chip comprises a main processing integrated circuit and a co-processing integrated circuit which are connected in parallel, and the device comprises:
the starting condition monitoring module is used for monitoring the starting condition of the main processing integrated circuit through the co-processing integrated circuit;
the adjustment execution judging module is used for judging whether to adjust the level of a power supply circuit of the main processing integrated circuit according to the starting condition of the main processing integrated circuit;
and the level adjusting module is used for adjusting the level of the power supply circuit through the co-processing integrated circuit if the level adjusting module is yes until the main processing integrated circuit is started.
Optionally, the adjustment execution determining module includes:
the first judgment submodule is used for judging that the level of a power supply circuit of the main processing integrated circuit is adjusted through the co-processing integrated circuit if the main processing integrated circuit is not started;
and the second judgment submodule is used for closing the co-processing integrated circuit if the main processing integrated circuit is started.
Optionally, the level adjustment module includes:
the level pull-down submodule is used for pulling down the level of the power supply circuit to a low level through the co-processing integrated circuit;
and the low level holding submodule is used for holding the low level of the power supply circuit through the co-processing integrated circuit until the main processing integrated circuit finishes starting.
Optionally, the apparatus further comprises:
a serial number returning module, configured to return, by the main processing integrated circuit, request information corresponding to the read request when the main processing integrated circuit receives the read request;
and the availability judging module is used for receiving an instruction whether the main processing integrated circuit is available or not through the main processing integrated circuit after the main processing integrated circuit sends the request information.
The invention also provides a computer-readable storage medium, on which a computer program is stored, which, when executed by the processor, implements a chip start-up method as defined in any one of the above.
The invention also provides a consumable chip which comprises the chip starting device or is started by the memory chip by adopting the chip starting method.
According to the technical scheme, the invention has the following advantages:
the method monitors the starting condition of the main processing integrated circuit in real time through the co-processing integrated circuit, judges whether to adjust the level of the power supply circuit of the main processing integrated circuit according to the starting condition of the main processing integrated circuit, and adjusts the level of the power supply circuit through the co-processing integrated circuit if the level of the power supply circuit is adjusted until the main processing integrated circuit is started. Therefore, the chip error report caused by the fact that the main processing integrated circuit misses the request communication with the external terminal due to the limitation of the starting speed is avoided, and the use cost of the chip is effectively reduced.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without inventive exercise.
Fig. 1 is a flowchart illustrating steps of a chip starting method according to an embodiment of the present invention;
fig. 2 is a flowchart illustrating steps of a chip starting method according to a second embodiment of the present invention;
fig. 3 is a flowchart illustrating steps of a method for verifying a start-up of a chip according to a third embodiment of the present invention;
FIG. 4 is a connection diagram of internal hardware of an imaging device and a consumable chip thereof according to an embodiment of the present invention;
fig. 5 is a block diagram of a chip starting apparatus according to an embodiment of the present invention.
Detailed Description
The embodiment of the invention provides a chip starting method and device, a storage medium and a consumable chip, which are used for solving the technical problems that in the prior art, because the chip cannot be started smoothly within the required starting time, the chip easily misses the communication with an external terminal, the error report condition of the chip occurs, and the use cost of the chip is increased.
In order to make the objects, features and advantages of the present invention more obvious and understandable, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the embodiments described below are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1, fig. 1 is a flowchart illustrating a chip starting method according to an embodiment of the invention.
The invention provides a chip starting method, which relates to a main processing integrated circuit and a co-processing integrated circuit in a chip, wherein the main processing integrated circuit and the co-processing integrated circuit are connected in parallel, and the method comprises the following steps:
an Integrated Circuit (IC) is a type of microelectronic device or component. The transistor, the resistor, the capacitor, the inductor and other elements and wires required in a circuit are interconnected together by adopting a certain process, are manufactured on a small or a plurality of small semiconductor wafers or medium substrates, and are then packaged in a tube shell to form a micro structure with the required circuit function; all the elements are structurally integrated, so that the electronic elements are greatly miniaturized, low in power consumption, intelligent and high in reliability. It is denoted by the letter "IC" in the circuit.
In the embodiment of the invention, the chip comprises a main processing integrated circuit and a co-processing integrated circuit, wherein the main processing integrated circuit is used for communicating with other terminals so as to process corresponding data requests; the co-processing integrated circuit is used for monitoring the starting condition of the main processing integrated circuit in real time, and adjusting the power supply level of the main processing integrated circuit based on the starting condition so as to ensure that the main processing integrated circuit can respond to other terminals in time and process corresponding data requests.
in the process of monitoring the starting condition by the co-processing integrated circuit, whether to execute the step of adjusting the level of the power supply circuit of the main processing integrated circuit can be judged based on the difference of the starting condition of the main processing integrated circuit. For example, the co-processing integrated circuit may listen for a situation where the main processing integrated circuit has started booting but the boot up work is not completed.
And 103, if so, adjusting the level of the power supply circuit through the co-processing integrated circuit until the main processing integrated circuit is started.
In a specific implementation, the main processing integrated circuit may be connected to a power supply circuit or a bus, and the co-processing integrated circuit and the main processing integrated circuit are connected in parallel, so that the power supply circuit or the bus connected to the main processing integrated circuit may be adjusted by the co-processing integrated circuit to adjust the level of the power supply circuit. For example, if the main processing integrated circuit is in a state where startup has already been started but the startup is not completed, an electrical signal may be transmitted on the power supply circuit or the bus, and at this time, a high level may appear on the power supply circuit or the bus at some time point, and a low level may appear in the remaining time period. The high level may be represented by an electrical signal 1 and the high level may be represented by an electrical signal 0. Therefore, the level change of the power supply circuit or the bus can be represented by 01. For example: the level at which the level on the power supply circuit or bus is not adjusted for a certain period of time may be 11001101101 … …. After adjustment, the product can be 111111111 11111111111 … … or 00000000000 … …. And if the main processing integrated circuit is started but the starting work is not finished, adjusting the level of the level on the circuit or the bus by the co-processing integrated circuit according to the actual situation until the main processing integrated circuit is started.
In the embodiment of the invention, the startup condition of the main processing integrated circuit is monitored in real time through the co-processing integrated circuit, whether the level of the power supply circuit of the main processing integrated circuit is adjusted or not is judged according to the startup condition of the main processing integrated circuit, and if so, the level of the power supply circuit is adjusted through the co-processing integrated circuit until the main processing integrated circuit is started. Therefore, the chip error report caused by the fact that the main processing integrated circuit misses the request communication with the external terminal due to the limitation of the starting speed is avoided, and the use cost of the chip is effectively reduced.
Referring to fig. 2, fig. 2 is a flowchart illustrating a chip starting method according to a second embodiment of the present invention.
The invention provides a chip starting method, which relates to a main processing integrated circuit and a co-processing integrated circuit in a chip, wherein the main processing integrated circuit and the co-processing integrated circuit are connected in parallel, and the method comprises the following steps:
in the embodiment of the present invention, the specific implementation process of step 201 is similar to that of step 101, and is not described herein again.
in one example of the present invention, the step 202 may include the following sub-steps:
if the main processing integrated circuit is not started, judging that the level of a power supply circuit of the main processing integrated circuit is adjusted through the co-processing integrated circuit;
and if the main processing integrated circuit is started, closing the co-processing integrated circuit.
In a specific implementation, a certain time is required for the main processing integrated circuit to start, and if the main processing integrated circuit is not started, but the external terminal sends a read request again, the main processing integrated circuit cannot respond to the read request.
Therefore, when the main processing integrated circuit is not started, the level of the power supply circuit of the main processing integrated circuit is judged to be adjusted through the co-processing integrated circuit, so that the response pause of the main processing integrated circuit is realized; and if the main processing integrated circuit is started, the co-processing integrated circuit is closed so as to recover the level of the power supply circuit and start the communication of the main processing integrated circuit.
in the embodiment of the invention, if the level of the power supply circuit of the main processing integrated circuit is adjusted by the co-processing integrated circuit, the level of the power supply circuit is directly reduced to a low level by the co-processing integrated circuit, so that the main processing integrated circuit can be started continuously, and meanwhile, an external terminal cannot respond to the main processing integrated circuit. The pull-down level may refer to pulling down a high level to a low level, and holding the low level. For example, the electric signal at the high level time point may be changed to 0, and the electric signal at the low level time point may be maintained to 0. Some time in the above example after the power supply circuit or bus upper level is pulled low becomes 00000000000 … ….
And step 204, keeping the low level of the power supply circuit through the co-processing integrated circuit until the main processing integrated circuit is started.
After the co-processing integrated circuit pulls down the level of the power supply circuit to a low level, the low level of the power supply circuit can be kept, and the main processing integrated circuit is ensured not to miss subsequent responses until the main processing integrated circuit is started.
Further, after the main processing integrated circuit is started, the method may further include the following steps:
when the main processing integrated circuit receives a read request, returning request information corresponding to the read request through the main processing integrated circuit;
after the main processing integrated circuit sends the request information, receiving an instruction whether the main processing integrated circuit is available or not through the main processing integrated circuit.
In a specific implementation, after the main processing integrated circuit is started, a subsequent verification process is required to ensure that the main processing integrated circuit can be used.
In the process, if the main processing integrated circuit receives the read request, the request information corresponding to the read request, such as the serial number, the chip information, the verification code information and the like, is returned, after the request information is returned, the request terminal to send the read request verifies whether the request information meets the condition, and sends an instruction for whether the main processing integrated circuit is available to the main processing integrated circuit by taking the condition as a standard, so that the verification process is completed.
Alternatively, the external terminal communicating with the chip to which the main processing integrated circuit belongs may be an imaging device such as a printer, and the specific terminal type is not limited in this embodiment of the present invention.
In the embodiment of the invention, the startup condition of the main processing integrated circuit is monitored in real time through the co-processing integrated circuit, whether the level of the power supply circuit of the main processing integrated circuit is adjusted or not is judged according to the startup condition of the main processing integrated circuit, and if so, the level of the power supply circuit is adjusted through the co-processing integrated circuit until the main processing integrated circuit is started. Therefore, the chip error report caused by the fact that the main processing integrated circuit misses the request communication with the external terminal due to the limitation of the starting speed is avoided, and the use cost of the chip is effectively reduced.
Referring to fig. 3, fig. 3 is a flowchart illustrating a method for verifying a chip start according to a third embodiment of the present invention.
The invention provides a chip start-up verification method, which relates to an imaging device and a consumable chip connected with the imaging device through a bus, wherein the consumable chip comprises a main processing integrated circuit and a co-processing integrated circuit which are connected in parallel, and the method comprises the following steps:
in the embodiment of the invention, when the imaging device is started, the co-processing integrated circuit is firstly awakened to monitor the starting conditions of the imaging device and the main processing integrated circuit in real time, so that the bus level can be adjusted according to the respective starting conditions.
Referring to fig. 4, fig. 4 shows a connection diagram of an imaging device and internal hardware of a consumable chip according to the present invention.
Including an imaging device 401, and a main IC402 and a co-processing IC403 connected in parallel with the imaging device.
in one example of the invention, the bus level may be pulled low and held when the co-processing integrated circuit listens that the imaging device was successfully booted, but the main processing integrated circuit was not successfully booted. At this time, after the imaging device detects that the level of the bus is pulled low, the subsequent start-up verification process is not further performed. Even if the imaging device sends subsequent signals such as a read instruction, the imaging device considers that the starting is not finished because the bus level is pulled low, and therefore the data corresponding to the reply read instruction of the main integrated circuit cannot be acquired until the main processing integrated circuit is started successfully.
And when the auxiliary processing integrated circuit monitors that the main processing integrated circuit is successfully started, the auxiliary processing integrated circuit is closed to enter a dormant state, and the level of the bus is restored to a normal level.
Optionally, step 304 may include the following sub-steps S1-S3:
s1, when the level of the bus is normal level, sending a serial number reading request to the main processing integrated circuit through the imaging device;
in an embodiment of the present invention, when the level of the bus is restored to the normal level, a serial number read request is sent to the main processing integrated circuit by the image forming apparatus to verify whether the serial number of the main processing integrated circuit is correct.
S2, executing a check code verification process according to the serial number returned by the main processing integrated circuit through the imaging equipment;
in the embodiment of the invention, the imaging device receives the serial number returned by the main processing integrated circuit in response to the serial number reading request, and the verification process of the check code is executed.
Optionally, the imaging device may further verify whether the returned serial number is correct, and if the serial number is incorrect, determine that the main processing integrated circuit is unavailable.
In another example of the present invention, the main processing integrated circuit may return a corresponding random value at the same time as the serial number, wherein the random value may be determined according to whether the chip has a random value in production.
Further, step S2 may include the following sub-steps:
calculating a corresponding first verification code according to a first secret key determined by the imaging equipment according to the serial number and sending the first verification code to the main processing integrated circuit;
receiving a second verification code returned by the main processing integrated circuit through the imaging device; the second verification code is generated according to a pre-stored second secret key after the main processing integrated circuit verifies that the first verification code is legal;
judging whether the second verification code is correct or not according to a comparison result of the first verification code and the second verification code through the imaging equipment;
and if the second verification code is correct, determining that the verification process of the check code is finished.
In a specific implementation, the imaging device determines a corresponding first key from a preset key library based on the serial number, calculates a corresponding first verification code according to the first key, and sends the first verification code to the main processing integrated circuit; the main processing integrated circuit calculates a second verification code according to a pre-stored second secret key, and judges that the first verification code is correct by comparing whether the first verification code and the second verification code are the same or not, and returns the second verification code to the imaging equipment through the main processing integrated circuit if the first verification code and the second verification code are the same; and the imaging equipment determines that the second verification code is correct and the verification process of the verification code is completed by comparing whether the first verification code is the same as the returned second verification code or not and if the first verification code is the same as the returned second verification code.
The first verification code and the second verification code may be generated by a cryptographic hash algorithm, such as MD5 (message digest algorithm 5) or SHA-1 (secure hash algorithm), for example, which is not limited by the embodiment of the present invention.
And S3, after the check code verification process is completed, executing a chip information verification process on the main processing integrated circuit through the imaging equipment, and judging whether the main processing integrated circuit is available.
Further, step S3 may include the following sub-steps:
after the verification process of the check code is completed, sending a chip information reading request to the main processing integrated circuit through the imaging equipment;
receiving chip information returned by the main processing integrated circuit responding to the chip information reading request through the imaging equipment;
judging whether the chip information is legal or not through the imaging equipment;
if the chip information is legal, the main processing integrated circuit is judged to be available;
and if the chip information is illegal, judging that the main processing integrated circuit is unavailable.
In an optional embodiment of the present invention, after the check code verification process is completed, the imaging device may further send a chip information reading request to the main processing integrated circuit, and determine whether the chip information is legal according to the returned chip information, and if so, determine that the main processing integrated circuit is available; if not, the main processing integrated circuit is judged to be unavailable.
In one example of the present invention, the image forming apparatus may further modify the remaining amount of consumables in the main processing integrated circuit to be 100% to 90% if 10% of consumables (ink or toner) are completely consumed in the main processing integrated circuit according to the counted number of times of usage. And when the residual amount of the consumable material is close to zero, locking the consumable chip. For example, writing other code such as "full used" or "VOID" ("invalid") or similar instructions of the non-use status flag in the main processing integrated circuit implements locking of the consumable chip.
After the main processing integrated circuit is used, the non-use mark can be erased, and the residual quantity of consumables in the main processing integrated circuit is recovered to 100 percent, so that the effect of recycling is achieved. Or only the new main processing integrated circuit is replaced, so that the effect that the co-processing integrated circuit can be repeatedly used is achieved.
In the embodiment of the invention, when a user inputs a starting request to start the imaging device, the starting conditions of the imaging device and the main processing integrated circuit are monitored in real time through the co-processing integrated circuit, if the main processing integrated circuit is not started successfully and the imaging device is started successfully, the level of a bus can be adjusted through the co-processing integrated circuit, and when the level of the bus is normal level, the imaging device executes a starting verification process on the main processing integrated circuit to judge whether the main processing integrated circuit is available, so that the technical problem that in the prior art, because a consumable chip does not respond to the printer within the set time of printing starting, a substitute chip easily misses the communication with the printer, the printer cannot detect the chip of an imaging box, the error reporting condition occurs, and the printing cost is increased is solved, and the main processing integrated circuit of the consumable chip can respond to the printer within the set time is effectively ensured, unnecessary error reporting is avoided, and the printing cost is reduced.
Referring to fig. 5, fig. 5 is a block diagram of a chip starting device according to a fourth embodiment of the present invention.
The chip starting device provided by the embodiment of the invention is applied to a consumable chip, the consumable chip comprises a main processing integrated circuit and a co-processing integrated circuit which are connected in parallel, and the device comprises:
a start-up condition monitoring module 501, configured to monitor a start-up condition of the main processing integrated circuit through the co-processing integrated circuit;
an adjustment execution judging module 502, configured to judge whether to adjust a level of a power supply circuit of the main processing integrated circuit according to a start condition of the main processing integrated circuit;
and a level adjusting module 503, configured to adjust, if yes, the level of the power supply circuit through the co-processing integrated circuit until the main processing integrated circuit is started.
Optionally, the adjustment execution determining module 502 includes:
the first judgment submodule is used for judging that the level of a power supply circuit of the main processing integrated circuit is adjusted through the co-processing integrated circuit if the main processing integrated circuit is not started;
and the second judgment submodule is used for closing the co-processing integrated circuit if the main processing integrated circuit is started.
Optionally, the level adjustment module 503 includes:
the level pull-down submodule is used for pulling down the level of the power supply circuit to a low level through the co-processing integrated circuit;
and the low level holding submodule is used for holding the low level of the power supply circuit through the co-processing integrated circuit until the main processing integrated circuit finishes starting.
Optionally, the apparatus further comprises:
a serial number returning module, configured to return, by the main processing integrated circuit, request information corresponding to the read request when the main processing integrated circuit receives the read request;
and the availability judging module is used for receiving an instruction whether the main processing integrated circuit is available or not through the main processing integrated circuit after the main processing integrated circuit sends the request information.
The embodiment of the present invention further provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by the processor, the chip starting method according to any of the above embodiments is implemented.
The embodiment of the invention also provides a consumable chip, which comprises the chip starting device in any one of the above embodiments or is started by the memory chip by adopting the chip starting method in any one of the above embodiments.
It is clear to those skilled in the art that, for convenience and brevity of description, the specific working processes of the above-described apparatuses and units may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.
In the embodiments provided in the present invention, it should be understood that the disclosed apparatus and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the units is only one logical division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.
The integrated unit, if implemented in the form of a software functional unit and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention may be embodied in the form of a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.
The above-mentioned embodiments are only used for illustrating the technical solutions of the present invention, and not for limiting the same; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (10)
1. A chip start-up method involving a main processing integrated circuit and a co-processing integrated circuit in a chip, the main processing integrated circuit and the co-processing integrated circuit being connected in parallel, the method comprising:
monitoring the starting condition of the main processing integrated circuit through the co-processing integrated circuit;
judging whether to adjust the level of a power supply circuit of the main processing integrated circuit according to the starting condition of the main processing integrated circuit;
and if so, adjusting the level of the power supply circuit through the co-processing integrated circuit until the main processing integrated circuit is started.
2. The chip start-up method according to claim 1, wherein the step of determining whether to adjust the level of the power supply circuit of the main processing integrated circuit according to the start-up condition of the main processing integrated circuit comprises:
if the main processing integrated circuit is not started, judging that the level of a power supply circuit of the main processing integrated circuit is adjusted through the co-processing integrated circuit;
and if the main processing integrated circuit is started, closing the co-processing integrated circuit.
3. The chip start-up method according to claim 1 or 2, wherein the step of adjusting the power supply circuit level by the co-processing integrated circuit until the main processing integrated circuit is started up includes:
pulling down, by the co-processing integrated circuit, a level of the power supply circuit to a low level;
and keeping the low level of the power supply circuit through the co-processing integrated circuit until the main processing integrated circuit is started.
4. The chip start-up method of claim 1, wherein after the main processing integrated circuit is started up, the method further comprises:
when the main processing integrated circuit receives a read request, a serial number corresponding to the read request is returned through the main processing integrated circuit;
receiving, by the primary processing integrated circuit, an instruction for whether the primary processing integrated circuit is available after the primary processing integrated circuit returns the serial number.
5. A chip starting device is applied to a consumable chip, the consumable chip comprises a main processing integrated circuit and a co-processing integrated circuit which are connected in parallel, and the device comprises:
the starting condition monitoring module is used for monitoring the starting condition of the main processing integrated circuit through the co-processing integrated circuit;
the adjustment execution judging module is used for judging whether to adjust the level of a power supply circuit of the main processing integrated circuit according to the starting condition of the main processing integrated circuit;
and the level adjusting module is used for adjusting the level of the power supply circuit through the co-processing integrated circuit if the level adjusting module is yes until the main processing integrated circuit is started.
6. The chip starting device according to claim 5, wherein the adjustment execution judging module comprises:
the first judgment submodule is used for judging that the level of a power supply circuit of the main processing integrated circuit is adjusted through the co-processing integrated circuit if the main processing integrated circuit is not started;
and the second judgment submodule is used for closing the co-processing integrated circuit if the main processing integrated circuit is started.
7. The chip start-up device according to claim 5 or 6, wherein the level adjustment module comprises:
the level pull-down submodule is used for pulling down the level of the power supply circuit to a low level through the co-processing integrated circuit;
and the low level holding submodule is used for holding the low level of the power supply circuit through the co-processing integrated circuit until the main processing integrated circuit finishes starting.
8. The chip start-up apparatus of claim 5, further comprising:
a serial number returning module, configured to return, by the main processing integrated circuit, request information corresponding to the read request when the main processing integrated circuit receives the read request;
and the availability judging module is used for receiving an instruction whether the main processing integrated circuit is available or not through the main processing integrated circuit after the main processing integrated circuit sends the request information.
9. A computer-readable storage medium having stored thereon a computer program, characterized in that: the computer program, when executed by a processor, implements the chip start-up method of any of claims 1-4.
10. A consumable chip, comprising: the chip starting device of any one of claims 5 to 8 is included or the chip starting method of any one of claims 1 to 4 is used for starting.
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