CN112639952A - Scanning driving unit, scanning driving circuit, array substrate and display device - Google Patents
Scanning driving unit, scanning driving circuit, array substrate and display device Download PDFInfo
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- CN112639952A CN112639952A CN201880094111.XA CN201880094111A CN112639952A CN 112639952 A CN112639952 A CN 112639952A CN 201880094111 A CN201880094111 A CN 201880094111A CN 112639952 A CN112639952 A CN 112639952A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
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- Crystallography & Structural Chemistry (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The invention discloses a scanning driving unit (10), a scanning driving circuit (100), an array substrate (AY) and a display device. The scanning driving unit (10) is provided with an upper pull control unit (11) for receiving a starting voltage (STV) to control a pull-up node (PU) to be in a high reference voltage state, correspondingly, a received clock signal (CK) is transmitted to a scanning output end (OUT) through a pull-up output unit (12) to be output as a scanning signal, a pull-down control unit (13) controls the pull-up node (PU) to be in a low reference voltage state and controls a pull-down node (PD) to be in the high reference voltage state after a scanning period, the pull-down control unit (14) controls the scanning output end (OUT) to be pulled down to a low reference voltage and stops outputting the scanning signal when the pull-down node (PD) is in the low reference voltage state, and meanwhile, a drift correction unit (15) controls the pull-up node (PU) to be in the low reference voltage state according to a drift correction signal.
Description
The invention relates to the field of display driving, in particular to a scanning driving technology in image display.
In the process of displaying images on the display panel, the scanning driving circuit is required to provide scanning signals to drive the pixel array arranged in the image display area in cooperation with the data driving circuit to provide image data. In recent years, in order to improve the integration of the display panel, the scan driving circuit and the pixel Array are fabricated on an Array substrate, which is also called a gate driver Array (GOA) circuit.
The plurality of scan driving units in the GOA circuit are usually designed in a cascade manner to sequentially output shifted scan signals to the pixel array. However, the scan driving unit must be stopped immediately after outputting the scan signal in one scan period so that other scan lines can normally receive the scan signal. However, in the actual working process of the GOA circuit, the threshold voltage of the transistor in the GOA circuit may drift, and then the scan driving unit may not stop outputting the scan signal in time in the non-scan period, so that the plurality of scan lines may be scanned at the same time, and the pixel array may not load the image data correctly, which may cause troubles for correct display of the image.
Disclosure of Invention
To solve the foregoing problems, a scan driving unit capable of preventing a scan signal from being inaccurately output due to a threshold shift of a transistor in the scan driving unit is provided.
Furthermore, a scan driving circuit, an array substrate and a display device are provided, wherein the scan driving circuit is used as the scan driving unit.
The embodiment of the invention discloses a scanning driving unit, which comprises:
a pull-up control unit for receiving a start voltage and transmitting the start voltage to a pull-up node within one scan period to control the pull-up node to be in a high reference voltage state;
the pull-up output unit is electrically connected with the pull-up node, and transmits the received clock signal to the scanning output end to be output as a scanning signal when the pull-up node is in a high reference voltage state;
a pull-down control unit electrically connected to a pull-down node and the pull-up node, for controlling the pull-up node to be in a low reference voltage state and controlling the pull-down node to be in a high reference voltage state after a scanning period;
the pull-down unit is electrically connected to the pull-down node and the scanning output end and used for controlling the scanning output end to pull down to a low reference voltage and stopping outputting the scanning signal when the pull-down node is in a low reference voltage state;
and the drift correction unit is electrically connected with the pull-up node and used for controlling the pull-up node to be in a low reference voltage state according to the drift correction signal after one scanning period.
The embodiment of the invention discloses a scanning driving circuit comprising a plurality of mutually cascaded scanning driving units.
The embodiment of the invention discloses an array substrate comprising a plurality of mutually cascaded scanning driving units.
The embodiment of the invention discloses a display device comprising the array substrate.
Compared with the prior art, the drift correction unit in the scanning drive unit is directly and electrically connected to the pull-up node, so that when the pull-down node cannot timely and accurately control the pull-up node to be in the low reference voltage state to stop outputting the scanning signal when the scanning drive unit is in the non-scanning period, the pull-up node is quickly and accurately pulled down to the low reference voltage state, the scanning drive units are prevented from simultaneously outputting the scanning signal to a plurality of scanning lines, and the accuracy of image display is ensured.
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to these drawings without inventive labor.
FIG. 1 is a schematic diagram of a layout structure of a scan driving circuit according to an embodiment of the present invention;
FIG. 2 is a schematic circuit structure of the scan driving unit shown in FIG. 1;
fig. 3 is a timing diagram illustrating the operation of the scan driving circuit shown in fig. 1-2.
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The circuit structure and the operation process of the scan driving circuit and the scan driving unit will be described in detail below with reference to the accompanying drawings.
The transistors used in all embodiments of the present invention are all N-type Thin Film Transistors (TFTs) manufactured by an Indium Gallium Zinc Oxide (IGZO) process. Of course, in other modified embodiments, the tft may also be P-type, and the invention is not limited thereto.
Please refer to fig. 1, which is a schematic layout structure diagram of a scan driving circuit 100 according to an embodiment of the present invention.
As shown in fig. 1, the scan driving circuit 100 according to the embodiment of the present invention is used to provide a scan pulse signal to the pixel matrix 200.
The scan driving circuit 100 includes a plurality of scan driving units 10 cascaded to each other such that the scan driving units 10 sequentially supply scan signals to a plurality of scan lines (not identified) in the pixel array 200 after the cascade. Each of the scan driving units 10 outputs a scan signal of one scan period to a scan line connected thereto in one frame image.
In this embodiment, the scan driving units 10 are respectively disposed at two opposite sides of the pixel array 200,
the scanning driving units 10 corresponding to odd-numbered and even-numbered scan lines are respectively located at two opposite sides of the pixel array 200, for example, the scanning driving units GOA1, GOA3, GOA5, GOA7 … …, GOA (2N-3), GOA2N-1, GOA (2N +1), … … corresponding to the scan lines in the odd-numbered scan lines are located at the right of the pixel array 200; the scanning driving units GOA2, GOA4, GOA6, GOA8 … …, GOA (2N-2), GOA (2N +2), and GOA (2N +2) … … corresponding to the even-numbered scanning lines are located on the left side of the pixel array 200.
Each scan driving unit 10 includes a driving enable terminal EN, a clock signal terminal CLK, a reset terminal TRST (see fig. 2), a first reference power terminal VDD odd (see fig. 2), a second reference power terminal VDD even (see fig. 2), and a scan output terminal OUT. When the scanning driving units are cascaded with each other, the scanning driving units corresponding to the odd-numbered scanning lines are cascaded with each other in sequence, and the scanning driving units corresponding to the even-numbered scanning lines are cascaded with each other in sequence. That is, for the plurality of scan driving units 10 on the left, the driving enable terminal EN of the GOA1 receives the start voltage STV, and the scan output terminal OUT is electrically connected to the driving enable terminal EN of the GOA2 while being connected to the first scan line, and so on. Correspondingly, for the right scan driving units 10, the driving enable terminal EN of the GOA2 receives the start voltage STV, and the scan output terminal OUT is connected to the first scan line and is also electrically connected to the driving enable terminal EN of the GOA 2.
Meanwhile, each adjacent 8 scan driving units 10 are a group which respectively receive the adjacent scan clock signals CK1-CK8 for 8 scan periods. In this embodiment, the scan driving circuit 100, the corresponding scan line and the pixel array 200 are disposed in the array substrate AY. The pixel array 200 is disposed in an image display region (not labeled) of the array substrate, the scan driving circuit 100 is disposed in a non-image display region, and the scan lines extend from the image display region to the non-image display region to connect the scan driving circuit 100 and the pixel array 200. In this embodiment, the scan driving circuit 100 is directly fabricated on the array substrate AY by using the GOA technology.
In addition, the array substrate AY may be applied to a display device (not identified), for example, a liquid crystal display, an organic electroluminescent display, and the like.
Specifically, please refer to fig. 2, which is a schematic circuit diagram of any one of the scan driving units 10 shown in fig. 1.
As shown in fig. 2, the scan driving unit 10 includes a pull-up control unit 11, a pull-up output unit 12, a pull-down control unit 13, a pull-down unit 14, a drift correction unit 15, and a reset unit 16.
The pull-up control unit 11 is configured to receive a start voltage STV from the driving enable terminal EN, and transmit the start voltage STV to the pull-up node PU in a scanning period to control the pull-up node PU to be in a high reference voltage state.
The pull-up output unit 12 is electrically connected to the pull-up node PU, and transmits the clock signal CK received from the clock signal terminal CLK to the scan output terminal OUT as a scan signal output when the pull-up node PU is in a high reference voltage state.
And a pull-down control unit 13 electrically connected to the pull-down node PD and the pull-up node PU, and configured to control the pull-up node PU to be in a low reference voltage state and the pull-down node PD to be in a high reference voltage state after one scanning period.
In this embodiment, it should be noted that the high-voltage reference state is that the voltage of the node is high voltage and is sufficient to drive the corresponding transistor to be in a conducting state, and may be denoted as VGH, and the low-voltage reference state is that the voltage of the node is low voltage and is insufficient to maintain the transistor in the conducting state, and may be denoted as VGL; the ground reference voltage is another low voltage equal to or lower than the low reference voltage at the node, and may be denoted as LVGL, where LVGL ≦ VGL, for example, where LVGL may be set to-5V, -7V, or-9V. In this embodiment, the low reference voltage VGL is the same as the ground reference voltage LVGL, i.e., LVGL ═ VGL.
The pull-down unit 14 is electrically connected to the pull-down node PD and the scan output terminal OUT, and configured to control the scan output terminal OUT to be pulled down to a low voltage and stop outputting the scan signal when the pull-down node PD is in a low reference voltage state.
And a drift correction unit 15 electrically connected to the pull-up node PU, for outputting a drift correction signal CS after a scanning period to control the pull-up node PU to be in a low reference voltage state. The drift correction unit 15 can rapidly and accurately pull down the pull-up node PU to the low reference voltage state when the pull-down node PD cannot timely and accurately control the pull-up node to be in the low reference voltage state to stop outputting the scanning signal when the scanning driving unit 10 is in the non-scanning period, so as to prevent a plurality of scanning driving units from simultaneously outputting the scanning signal to a plurality of scanning lines, and ensure the accuracy of image display.
The drift correction signal CS may be an externally provided clock signal, or may be a scan signal output by a scan driving unit adjacent to the clock signal in a next scan period. For example, if the current scan driving unit is the scan driving unit GOA1, the drift correction signal CS may be a scan signal output by the scan driving unit GOA 3.
The reset unit 16 is electrically connected to the pull-up node PU, and is configured to control the pull-up node PU to be at a ground reference voltage according to the reset signal TRST, and when the scan driving circuit 100 is reset integrally, the pull-up output units 12 in all the scan driving units 10 are accurately controlled to stop outputting the scan driving signal.
More specifically, as shown in fig. 2:
the pull-up control unit 11 includes a first transistor M1, a gate and a drain of the first transistor M1 are electrically connected to the driving enable terminal EN, and a source of the first transistor M1 is electrically connected to the pull-up node PU.
The pull-up output unit 12 includes a third transistor M3 and a first capacitor C1, a gate of the third transistor M3 is electrically connected to the pull-up node PU, a drain of the third transistor M3 is electrically connected to a clock signal terminal CLK for receiving the clock signal CK, and a source of the third transistor M3 is electrically connected to the scan output terminal OUT. The first capacitor C1 is electrically connected between the pull-up node PU and the scan output terminal OUT.
The pull-down control unit 13 includes a second transistor M2, a fourth transistor M4, a seventh transistor M7, and an eighth transistor M8.
The gate and the drain of the second transistor M2 are electrically connected to the first reference power source VDD odd, and the source of the second transistor M2 is electrically connected to the pull-down node PD.
A gate of the fourth transistor M4 is electrically connected to the pull-down node PD, a drain of the fourth transistor M4 is electrically connected to the pull-up node PU, and a source of the fourth transistor M4 is electrically connected to the ground reference voltage LVGL.
A gate of the seventh transistor M7 is electrically connected to the pull-up node PU, a drain of the seventh transistor M7 is electrically connected to the pull-down node PD, and a source of the seventh transistor M7 is electrically connected to the ground reference voltage LVGL.
A gate of the eighth transistor M8 is electrically connected to the driving enable terminal EN, a drain of the eighth transistor M8 is electrically connected to the pull-down node PD, and a source of the eighth transistor M8 is electrically connected to the ground reference terminal LVGL.
The pull-down unit 14 includes a pull-down transistor M14, a gate of the pull-down transistor M14 is electrically connected to the pull-down node PD, a drain of the pull-down transistor M14 is electrically connected to the scan output terminal OUT, and a source of the pull-down transistor 14 is electrically connected to the low reference voltage VGL.
Preferably, the scan driving unit 10 further includes an auxiliary pull-down control unit 13 ', an auxiliary pull-down unit 14 ' and an auxiliary pull-down node PD '. The auxiliary pull-down control unit 13 ', the auxiliary pull-down unit 14 ' and the auxiliary pull-down node PD ' are all in an operating state alternately with the pull-down control unit 13, the pull-down unit 14 and the pull-down node PD in a scanning period of an adjacent frame image. For example, at the time of the ith frame image display scanning, the pull-down control unit 13, the pull-down unit 14, and the pull-down node PD are in an operating state, and the auxiliary pull-down control unit 13 ', the auxiliary pull-down unit 14 ', and the auxiliary pull-down node PD ' are in a non-operating state; when the (i +1) th frame image is displayed and scanned, the pull-down control unit 13, the pull-down unit 14 and the pull-down node PD are in a non-working state, and the auxiliary pull-down control unit 13 ', the auxiliary pull-down unit 14 ' and the auxiliary pull-down node PD ' are in a working state, where i is a natural number.
Specifically, the auxiliary pull-down control unit 13 ' includes a second symmetric transistor M2 ', a fourth symmetric transistor M4 ', a seventh symmetric transistor M7 ', and an eighth symmetric transistor M8 '.
The gate and the drain of the second symmetric transistor M2 ' are electrically connected to the second reference power source VDD Even, and the source of the second symmetric transistor M2 ' is electrically connected to the auxiliary pull-down node PD '.
The gate of the fourth symmetric transistor M4 'is electrically connected to the auxiliary pull-down node PD', the drain of the fourth symmetric transistor M4 'is electrically connected to the pull-up node PU, and the source of the fourth symmetric transistor M4' is electrically connected to the ground reference voltage LVGL.
The gate of the seventh symmetric transistor M7 'is electrically connected to the pull-up node PU, the drain of the seventh symmetric transistor M7' is electrically connected to the auxiliary pull-down node PD ', and the source of the seventh symmetric transistor M7' is electrically connected to the ground reference voltage LVGL.
The gate of the eighth symmetric transistor M8 ' is electrically connected to the driving enable EN, the drain of the eighth symmetric transistor M8 ' is electrically connected to the auxiliary pull-down node PD ', and the source of the eighth symmetric transistor is electrically connected to the ground reference voltage LVGL.
The auxiliary pull-down unit 14 'includes a pull-down symmetrical transistor M14', a gate of the pull-down symmetrical transistor M14 'is electrically connected to the auxiliary pull-down node PD', a drain of the pull-down auxiliary transistor M14 'is electrically connected to the scan output terminal OUT, and a source of the pull-down symmetrical transistor M14' is electrically connected to the low reference voltage VGL.
The drift correction unit 15 includes a correction transistor M15, a gate of the correction transistor M15 receives a drift correction signal CS, a drain of the correction transistor M15 is electrically connected to the pull-up node PU, and a source of the correction transistor M15 is electrically connected to a ground reference voltage LVGL.
The reset unit 16 includes a reset transistor M20, a gate of the reset transistor M20 is electrically connected to the reset terminal TRST to receive a reset signal, a drain of the reset transistor M20 is electrically connected to the pull-up node PU, and a source of the reset transistor M20 is electrically connected to a ground reference voltage.
Preferably, in order to facilitate the control and adjustment of the operating characteristics of each scan driving unit 100, the back gates of the second transistor M2, the second symmetric transistor M2', the reset transistor M20 and the drift correction transistor M15 are further electrically connected to the adjustment reference terminal LS, and the adjustment voltage provided by the adjustment reference terminal is adjusted according to the channel characteristics of the transistors, so as to ensure that the transistors can accurately operate at the predetermined threshold voltage.
Please refer to fig. 3, which is a timing diagram illustrating the operation of the scan driving circuit 100 shown in fig. 1-2. Wherein the symbols in the figures represent the corresponding signals received in figures 1-2. In this embodiment, the operation of the scan driving unit GOA1 sorted at the first position is taken as an example.
Here, for the first frame image scanning period 1stFrame, the GOA1 receives the clock signal CK1 and the start voltage STV, then the first transistor M1 in the pull-up unit 11 is turned on, so as to pull up the voltage of the pull-up node PU to the high reference voltage, at the same time, the first capacitor C1 also starts to charge and further raise the voltage of the pull-up node PU, when the voltage of the pull-up node PU is higher than the threshold voltage Vth (not identified) of the third transistor M3, the third transistor M3 is turned on, the clock signal CK1 is transmitted to the scan output terminal OUT through the turned-on third transistor M3, and CK1 at this time is output as the scan signal.
The start voltage STV controls the eighth transistor M8 to be turned on, thereby transmitting the ground reference voltage to the pull-down node PD, controlling the pull-down transistor in the pull-down unit 14 to be in a turned-off state.
When the scan period of the start voltage STV and the clock signal CK1 is reached, the first transistor M1 is turned off, the pull-down control unit 13 is in an operating state, the eighth transistor M8 is turned off, but the 2 nd transistor M2 is turned on under the control of the first reference voltage VDD Odd and pulls the pull-down node PD high to be in a high reference voltage state, the corresponding fourth transistor M4 and the pull-down transistor M14 in the pull-down unit 14 are turned on, the scan output terminal OUT is in a low voltage state to stop outputting the scan signal, and the pull-up node PU is in a ground reference voltage state to turn off the third transistor M3 to stop transmitting the clock signal CK1 to the scan output terminal OUT.
Meanwhile, the scan output terminal of the scan driving unit GOA2 has already outputted the scan signal, so as to control the correction transistor M15 of the drift correction unit 15 to be in a conducting state, and further accurately and instantly pull down the pull-up node PU to the ground reference voltage.
In addition, for the second frame image scanning period 2stFrame, after the start voltage STV and the scanning period in the clock signal CK1 are reached, the pull-down auxiliary control unit 13 ' is in an operating state, the second reference voltage VDD Even is provided to the pull-down auxiliary control unit 13 ', the pull-up node PU is controlled to be in a low reference voltage state by the pull-down auxiliary unit 14 ', and the scan output terminal OUT stops outputting the scan signal, as in the operation of each transistor in the pull-down control unit 13.
The pull-down control unit 13 and the pull-down auxiliary control unit 13 'are alternately in an operating state at the time of display of an adjacent frame image, so that it is possible to prevent the performance of the transistor from being affected by the pull-down control unit 13 or the pull-down auxiliary control unit 13' being in an operating state for a long time.
It should be noted that the operation of the other scan driving units is the same as that of the GOA1, and therefore, the description thereof is omitted.
The principles and embodiments of the present invention have been described herein using specific examples, which are provided only to assist in understanding the core concepts of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.
Claims (12)
- A scan driving unit, comprising:a pull-up control unit for receiving a start voltage and transmitting the start voltage to a pull-up node within one scan period to control the pull-up node to be in a high reference voltage state;the pull-up output unit is electrically connected with the pull-up node, and transmits the received clock signal to the scanning output end to be output as a scanning signal when the pull-up node is in a high reference voltage state;a pull-down control unit electrically connected to a pull-down node and the pull-up node, for controlling the pull-up node to be in a low reference voltage state and controlling the pull-down node to be in a high reference voltage state after a scanning period;the pull-down unit is electrically connected to the pull-down node and the scanning output end and used for controlling the scanning output end to pull down to a low reference voltage and stopping outputting the scanning signal when the pull-down node is in a low reference voltage state;and the drift correction unit is electrically connected with the pull-up node and used for controlling the pull-up node to be in a low reference voltage state according to the drift correction signal after the scanning period.
- The scan driving unit according to claim 1, wherein the drift correction unit comprises a correction transistor, a gate of the correction transistor receives the drift correction signal, a drain of the correction transistor is electrically connected to the pull-up node, and a source of the correction transistor is electrically connected to a ground reference voltage.
- The scan driving unit according to claim 2, wherein the pull-up control unit comprises a first transistor, a gate and a drain of the first transistor are electrically connected to a driving enable terminal, the driving enable terminal is configured to receive the start-up voltage, and a source of the first transistor is electrically connected to the pull-up node.
- The scan driving unit as claimed in claim 3, wherein the pull-up output unit comprises a third transistor and a first capacitor, a gate of the third transistor is electrically connected to the pull-up node, a drain of the third transistor is electrically connected to a clock signal terminal for receiving the clock signal, a source of the third transistor is electrically connected to the scan output terminal, and the first capacitor is electrically connected between the pull-up node and the scan output terminal.
- The scan driving unit according to claim 4, further comprising a reset unit electrically connected to the pull-up node for controlling the pull-up node to be in the low reference voltage state when receiving a reset signal.
- The scan driving unit according to claim 5, wherein the reset unit comprises a reset transistor, a gate of the reset transistor receives a reset signal, a drain of the reset transistor is electrically connected to the pull-up node, and a source of the reset transistor receives a ground reference voltage.
- The scan driving unit according to claim 4, wherein the pull-down control unit comprises a second transistor, a fourth transistor, a seventh transistor and an eighth transistor, a gate and a drain of the second transistor are electrically connected to a first reference power source, a source of the second transistor is electrically connected to the pull-down node, a gate of the fourth transistor is electrically connected to the pull-down node, a drain of the fourth transistor is electrically connected to the pull-up node, a source of the fourth transistor is electrically connected to a ground reference voltage, a gate of the seventh transistor is electrically connected to the pull-up node, a drain of the seventh transistor is electrically connected to the pull-down node, a source of the seventh transistor is electrically connected to the ground reference voltage, a gate of the eighth transistor is electrically connected to the driving enable terminal, and a drain of the eighth transistor is electrically connected to the pull-down node, a source of the eighth transistor is electrically connected to the ground reference terminal;the pull-down unit comprises a pull-down transistor, the grid electrode of the pull-down transistor is electrically connected with the pull-down node, the drain electrode of the pull-down transistor is electrically connected with the scanning output end, and the source electrode of the pull-down transistor receives the low reference voltage.
- The scan driving unit of claim 7, further comprising an auxiliary pull-down control unit, an auxiliary pull-down unit, and an auxiliary pull-down node, wherein the auxiliary pull-down control unit and the pull-down control unit are alternately in an active state during a scan period of an adjacent frame image, and the auxiliary pull-down node is correspondingly controlled to be at the high reference voltage or the low reference voltage when the auxiliary pull-down control unit is in the active state; the auxiliary pull-down unit and the pull-down unit are alternately in a working state in a scanning period of an adjacent frame image, and the auxiliary pull-down unit controls the scanning output end to be at the low reference voltage when the auxiliary pull-down node is at the high reference voltage.
- The scan driving unit of claim 8, wherein the auxiliary pull-down control unit comprises a second symmetric transistor, a fourth symmetric transistor, a seventh symmetric transistor and an eighth symmetric transistor, wherein a gate and a drain of the second symmetric transistor are electrically connected to a second reference power source, and a source of the second symmetric transistor is electrically connected to the auxiliary pull-down node; a gate of the fourth symmetric transistor is electrically connected to the auxiliary pull-down node, a drain of the fourth symmetric transistor is electrically connected to the pull-up node, and a source of the fourth symmetric transistor is electrically connected to the ground reference voltage; a gate of the seventh symmetric transistor is electrically connected to the pull-up node, a drain of the seventh symmetric transistor is electrically connected to the auxiliary pull-down node, and a source of the seventh symmetric transistor is electrically connected to the ground reference voltage; a gate of the eighth symmetric transistor is electrically connected to the drive enable terminal, a drain of the eighth symmetric transistor is electrically connected to the auxiliary pull-down node, and a source of the eighth symmetric transistor is electrically connected to the ground reference voltage;the auxiliary pull-down unit comprises pull-down symmetrical transistors, the grid electrodes of the pull-down symmetrical transistors are electrically connected with the auxiliary pull-down nodes, the drain electrodes of the pull-down symmetrical transistors are electrically connected with the scanning output end, and the source electrodes of the pull-down symmetrical transistors are electrically connected with the low reference voltage.
- A scan driving circuit comprising a plurality of scan driving units according to any one of claims 1 to 9 cascaded with each other.
- An array substrate comprising a plurality of scan driving units according to any one of claims 1 to 9 cascaded to each other.
- A display device comprising the array substrate according to claim 11.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/CN2018/108351 WO2020062027A1 (en) | 2018-09-28 | 2018-09-28 | Scanning drive unit, scanning drive circuit, array substrate, and display device |
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| Publication Number | Publication Date |
|---|---|
| CN112639952A true CN112639952A (en) | 2021-04-09 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201880094111.XA Pending CN112639952A (en) | 2018-09-28 | 2018-09-28 | Scanning driving unit, scanning driving circuit, array substrate and display device |
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| Country | Link |
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| CN (1) | CN112639952A (en) |
| WO (1) | WO2020062027A1 (en) |
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| CN113593465B (en) * | 2021-08-06 | 2023-12-12 | 北京京东方显示技术有限公司 | Voltage compensation module, grid driving circuit, driving method of grid driving circuit and display substrate |
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| WO2020062027A1 (en) | 2020-04-02 |
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