CN112636175A - Preparation method of semiconductor device - Google Patents
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- CN112636175A CN112636175A CN202011533023.0A CN202011533023A CN112636175A CN 112636175 A CN112636175 A CN 112636175A CN 202011533023 A CN202011533023 A CN 202011533023A CN 112636175 A CN112636175 A CN 112636175A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 44
- 238000002360 preparation method Methods 0.000 title abstract description 5
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- 239000010410 layer Substances 0.000 claims abstract description 194
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- 238000000034 method Methods 0.000 claims abstract description 30
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- 238000005530 etching Methods 0.000 claims description 33
- 238000004519 manufacturing process Methods 0.000 claims description 16
- 238000005253 cladding Methods 0.000 claims description 13
- 238000005468 ion implantation Methods 0.000 claims description 6
- 230000008569 process Effects 0.000 abstract description 10
- 238000006243 chemical reaction Methods 0.000 abstract description 5
- 238000009792 diffusion process Methods 0.000 abstract description 5
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- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/20—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers
- H01S5/2004—Confining in the direction perpendicular to the layer structure
- H01S5/2009—Confining in the direction perpendicular to the layer structure by using electron barrier layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/20—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers
- H01S5/2004—Confining in the direction perpendicular to the layer structure
- H01S5/2018—Optical confinement, e.g. absorbing-, reflecting- or waveguide-layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/20—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers
- H01S5/22—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers having a ridge or stripe structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/30—Structure or shape of the active region; Materials used for the active region
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S2304/00—Special growth methods for semiconductor lasers
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Abstract
The invention provides a preparation method of a semiconductor device, which relates to the technical field of semiconductors and comprises the following steps: the device comprises a substrate layer, wherein a first epitaxial growth layer and a second epitaxial growth layer are arranged on the same layer of the substrate layer, the first epitaxial growth layer and the second epitaxial growth layer are current blocking layers, the part of the substrate layer between the first epitaxial growth layer and the second epitaxial growth layer is a channel area, the first epitaxial growth layer, the second epitaxial growth layer and the top surface of the channel area are located on the same plane, and the plane is parallel to the bottom surface of the substrate layer. The current blocking effect of the first epitaxial growth layer and the second epitaxial growth layer enables the diffusion area of the current and the flowing path of the current to be effectively controlled, and therefore the electro-optic conversion efficiency of the device is improved. Meanwhile, when the smooth functional layer is formed, the smooth substrate layer can be directly grown to form the smooth functional layer without additional process treatment, and the reliability of the device is effectively improved.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a preparation method of a semiconductor device.
Background
Semiconductor devices are lasers using semiconductor materials as working substances, and have the advantages of being small and exquisite, efficient, long in service life, easy to integrate and the like, so that the semiconductor devices are widely applied to the fields of imaging, communication, machining and the like. However, with the advancement of technology, there is a higher demand for semiconductor devices.
The existing semiconductor device generally adopts a laminated semiconductor device epitaxial structure, but the on-state current is not effectively controlled, so that the electro-optic conversion efficiency is lower.
Disclosure of Invention
The present invention is directed to a method for manufacturing a semiconductor device, so as to solve the problem of low electro-optic conversion efficiency of the conventional semiconductor device due to current diffusion.
In order to achieve the above purpose, the embodiment of the present invention adopts the following technical solutions:
in one aspect of the embodiments of the present invention, a method for manufacturing a semiconductor device is provided, where the method includes: forming a first current blocking area and a second current blocking area on the substrate layer, wherein the part of the substrate layer between the first current blocking area and the second current blocking area is a channel area, the first current blocking area, the second current blocking area and the top surface of the channel area are positioned on the same plane, and the plane is parallel to the bottom surface of the substrate layer; and forming a leveling functional layer on the substrate layer on which the first current blocking region, the channel region and the second current blocking region are formed.
Optionally, the forming a planarization functional layer on the substrate layer on which the first current blocking region, the channel region, and the second current blocking region are formed includes: a flat lower cladding layer, a lower limiting layer, a quantum well, an upper limiting layer, an upper cladding layer and an ohmic contact layer are sequentially formed on a substrate layer on which a first current blocking region, a channel region and a second current blocking region are formed.
Optionally, forming a first current blocking region and a second current blocking region in the substrate layer, where a portion of the substrate layer between the first current blocking region and the second current blocking region is a channel region, includes: and forming a first current blocking area and a second current blocking area which are spaced and positioned at two sides of the channel area on the substrate layer.
Optionally, forming a first current blocking region and a second current blocking region in the substrate layer, where a portion of the substrate layer between the first current blocking region and the second current blocking region is a channel region, includes: and forming a first current blocking region and a second current blocking region on the substrate layer, wherein the first current blocking region and the second current blocking region are arranged on the periphery of the channel region and are connected with each other.
Optionally, forming the first current blocking region and the second current blocking region on the substrate layer includes: a first current blocking region and a second current blocking region are respectively formed on the substrate layer by ion implantation.
Optionally, the doping depth of the first current blocking region and the second current blocking region is greater than 100 nm.
Optionally, the forming of the first current blocking region and the second current blocking region on the substrate layer includes: etching the substrate layer to form a first etching groove and a second etching groove which are adjacent, wherein a mesa structure is arranged between the first etching groove and the second etching groove; epitaxially growing a current barrier layer on the substrate layer; and carrying out surface planarization treatment on the current blocking layer to expose the mesa structure, wherein the part of the current blocking layer, which is positioned in the first etching groove after the surface planarization treatment, is a first current blocking area, the part of the current blocking layer, which is positioned in the second etching groove after the surface planarization treatment, is a second current blocking area, and the mesa structure, which is positioned between the first current blocking area and the second current blocking area, is a channel area.
Optionally, the thickness of the channel region is greater than or equal to 20 nm.
Optionally, a width of the channel region along the direction from the first current blocking region to the second current blocking region is greater than 0.1 μm.
Optionally, the channel region is an N-type region, and the first current blocking region and the second current blocking region are P-type layers; or, the channel region is a P-type region, and the first current blocking region and the second current blocking region are N-type layers.
The beneficial effects of the invention include:
the invention provides a preparation method of a semiconductor device, which comprises the following steps: the device comprises a substrate layer, wherein a first epitaxial growth layer and a second epitaxial growth layer are arranged on the same layer of the substrate layer, the first epitaxial growth layer and the second epitaxial growth layer are current blocking layers, the part of the substrate layer between the first epitaxial growth layer and the second epitaxial growth layer is a channel area, the first epitaxial growth layer, the second epitaxial growth layer and the top surface of the channel area are located on the same plane, and the plane is parallel to the bottom surface of the substrate layer. The current blocking effect of the first epitaxial growth layer and the second epitaxial growth layer enables the diffusion area of the current and the flowing path of the current to be effectively controlled, and therefore the electro-optic conversion efficiency of the device is improved. Meanwhile, when the smooth functional layer is formed, the smooth substrate layer can be directly grown to form the smooth functional layer without additional process treatment, and the reliability of the device is effectively improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.
Fig. 1 is a schematic structural diagram of a semiconductor device according to an embodiment of the present invention;
fig. 2 is a schematic flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention;
fig. 3 is a second flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention;
fig. 4 is a third schematic flow chart of a manufacturing method of a semiconductor device according to an embodiment of the present invention;
fig. 5 is one of schematic structural diagrams of a substrate layer of a semiconductor device according to an embodiment of the present invention;
fig. 6 is a second schematic structural diagram of a substrate layer of a semiconductor device according to an embodiment of the present invention;
FIG. 7 is an enlarged view of a portion of area A of FIG. 5;
FIG. 8 is an enlarged view of a portion of area B of FIG. 5;
fig. 9 is a third schematic structural diagram of a substrate layer of a semiconductor device according to an embodiment of the present invention;
fig. 10 is a fourth schematic structural diagram of a substrate layer of a semiconductor device according to an embodiment of the present invention;
fig. 11 is a fifth schematic structural diagram of a substrate layer of a semiconductor device according to an embodiment of the present invention.
Icon: 100-a substrate layer; 110-a channel region; 111-the top surface of the channel region; 112-the sides of the channel region; 210 — a first current blocking region; 211-first etch trenches; 220-a second current blocking region; 221-a second etching groove; 300-upper cladding; 400-flattening the lower cladding; 510-a lower confinement layer; 520-quantum well; 530-upper confinement layer; 600-ohmic contact layer; 700-conductive layer.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. The components of embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. It should be noted that, in the case of no conflict, various features in the embodiments of the present invention may be combined with each other, and the combined embodiments are still within the scope of the present invention.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.
In the description of the present invention, it should be noted that the terms "first", "second", "third", and the like are used only for distinguishing the description, and are not intended to indicate or imply relative importance.
In the description of the present invention, it should also be noted that, unless otherwise explicitly stated or limited, the terms "disposed," "connected," and "connected" are to be construed broadly and may be, for example, directly connected, indirectly connected through intervening media, or interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
In one aspect of the embodiments of the present invention, a method for manufacturing a semiconductor device is provided, where the method includes: forming a first current blocking area 210 and a second current blocking area 220 on the substrate layer 100, wherein the channel area 110 is a part of the substrate layer 100 between the first current blocking area 210 and the second current blocking area 220, the first current blocking area 210 and the second current blocking area 220 are located on the same plane with the top surface 111 of the channel area, and the plane is parallel to the bottom surface of the substrate layer 100; a planarization functional layer is formed on the substrate layer 100 where the first current blocking region 210, the channel region 110, and the second current blocking region 220 are formed.
By way of example, by improving the hierarchical structure of the semiconductor device, the diffusion region of the current and the flowing path of the current are effectively controlled, and the overall performance of the semiconductor device is further improved, as shown in fig. 2, the improved structure can be schematically prepared by the following method:
s010: a first current blocking region 210 and a second current blocking region 220 are formed in the substrate layer 100, and a portion of the substrate layer 100 between the first current blocking region 210 and the second current blocking region 220 is the channel region 110.
As shown in fig. 1, the first current blocking region 210 and the second current blocking region 220 are formed on the substrate layer 100, that is, the first current blocking region 210 and the second current blocking region 220 are formed in the same layer. The portion of the substrate layer 100 between the first current blocking area 210 and the second current blocking area 220 can be used as the channel area 110, so that when an external voltage is applied to the semiconductor device and a current flows through the substrate layer 100, under the current blocking effect of the first current blocking area 210 and the second current blocking area 220, the current does not flow through the positions of the first current blocking area 210 and the second current blocking area 220 around the channel area 110, but flows through the channel area 110 more intensively, so that the path of the current on the substrate layer 100 can be effectively controlled. In actual implementation, the positions, areas or equivalent resistances of the first current blocking region 210 and the second current blocking region 220 on the substrate layer 100 may be reasonably set according to requirements, so that the position and area of the channel region 110 formed along with the first current blocking region 210 and the second current blocking region 220 are on a preset current path. The first current blocking region 210 and the second current blocking region 220 can also control the diffusion of current, so that the current is more concentrated, the electro-optic conversion efficiency of the device is further improved, and when the semiconductor device is a semiconductor laser, the semiconductor laser can have a lower laser threshold.
In addition, the top surface of the first current blocking region 210, the top surface 111 of the channel region, and the top surface of the second current blocking region 220 formed on the substrate layer 100 are all in the same plane, which may be parallel to the substrate plane, so that a functional layer formed on the substrate subsequently may be directly formed in a whole layer, thereby avoiding the need for additional process treatment on the functional layer due to the concave-convex surface of the substrate layer 100, and effectively improving the reliability of the device. For example, when the substrate layer 100 is made of GaAs and the functional layer is made of AlGaAs, the substrate layer 100 may be processed by the present embodiment and then the AlGaAs functional layer may be epitaxially grown, so as to avoid the defect caused by oxidation of Al in the AlGaAs material during the processing process when the AlGaAs functional layer is processed. The first current blocking region 210 and the second current blocking region 220 may be formed using an equivalent reverse biased diode, a dielectric material, or the like. When forming a reverse biased diode, the first current blocking region 210 may be a reverse biased diode directly formed along the current flowing direction, or may be formed by matching with the substrate layer 100, or may be formed by matching with another layer (which may be a functional layer or a matching layer separately disposed) formed on the first current blocking region 210, and the second current blocking region 220 is similar to the first current blocking region.
S020: a planarization functional layer is formed on the substrate layer 100 where the first current blocking region 210, the channel region 110, and the second current blocking region 220 are formed.
After the substrate layer 100 in S010 in which the current blocking region and the channel region 110 are formed is completed, a flat functional layer may be formed on the substrate layer 100. The method for forming the upper waveguide layer can be performed in an epitaxial growth mode, and because the surface of the substrate layer 100 is relatively flat, when the functional layer is formed, the flat functional layer can be directly formed by growth without additional process treatment, so that the reliability of the device is effectively improved.
Alternatively, as shown in fig. 3, forming a planarization functional layer on the substrate layer 100 formed with the first current blocking region 210, the channel region 110, and the second current blocking region 220 includes:
s021: a planarized lower cladding layer 400, a lower confinement layer 510, a quantum well 520, an upper confinement layer 530, an upper cladding layer 300, and an ohmic contact layer 600 are sequentially formed on the substrate layer 100 where the first current blocking region 210, the channel region 110, and the second current blocking region 220 are formed.
Illustratively, as shown in fig. 3, the functional layers may include a lower cladding layer 400, a lower confinement layer 510, a quantum well 520, an upper confinement layer 530, an upper cladding layer 300, and an ohmic contact layer 600. In addition, a conductive layer 700 may be further disposed on the ohmic contact layer 600 to further complete the functional layer.
The substrate layer 100 may be configured as an N-type substrate or a P-type substrate according to the conductivity type, and the N-type substrate will be schematically described as an example below:
when the substrate layer 100 is an N-type substrate (the corresponding channel region 110 is also an N-type region), the first current blocking region 210 and the second current blocking region 220 are P-type regions, and at this time, the planarization lower cladding layer 400 may be set as an N-type planarization lower cladding layer 400 (or an N-type matching layer may be separately set), so that a reverse PN junction may be formed by matching the N-type planarization lower cladding layer 400 with the P-type first current blocking region 210 or the P-type second current blocking region 220, and an NPN structure may be formed in a vertical direction, so that the first current blocking region 210 and the second current blocking region 220 may correspondingly form a current blocking region. The P-type layer doping atoms grown include: C. zn, etc.
Optionally, the forming a first current blocking region 210 and a second current blocking region 220 on the substrate layer 100, and a portion of the substrate layer 100 between the first current blocking region 210 and the second current blocking region 220 being the channel region 110 includes: a first current blocking region 210 and a second current blocking region 220 spaced apart on both sides of the channel region 110 are formed on the substrate layer 100.
For example, when the first current blocking region 210 and the second current blocking region 220 are formed, the upper end and the lower end of the channel region 110 may directly extend to the upper end and the lower end of the substrate, as shown in fig. 9, when the substrate layer 100 is viewed from the top, the channel region 110 is located between the first current blocking region 210 and the second current blocking region 220, and the channel region 110 separates the first current blocking region 210 from the second current blocking region 220, so that the first current blocking region 210 and the second current blocking region 220 are spaced apart from each other at two sides of the channel region 110.
Optionally, the forming a first current blocking region 210 and a second current blocking region 220 on the substrate layer 100, and a portion of the substrate layer 100 between the first current blocking region 210 and the second current blocking region 220 being the channel region 110 includes: a first current blocking region 210 and a second current blocking region 220, which are disposed around the periphery of the channel region 110 and connected to each other, are formed on the substrate layer 100.
For example, the upper and lower ends of channel region 110 may not directly extend to the upper and lower ends of the substrate, as shown in fig. 10, when viewed from the top of substrate layer 100, channel region 110 is located between first current blocking region 210 and second current blocking region 220, and first current blocking region 210 and second current blocking region 220 are connected at the upper and lower ends of channel region 110, and in this case, the current channel of substrate layer 100 is only channel region 110 surrounded in the middle.
In another embodiment, one of the upper and lower ends of the channel region 110 may be one end directly extending to the substrate layer 100, the other of the upper and lower ends of the channel region 110 may not directly extend to the other end of the substrate layer 100, when viewed from the top of the substrate layer 100, the channel region 110 is located between the first current blocking region 210 and the second current blocking region 220, and the first current blocking region 210 and the second current blocking region 220 are connected at one end of the channel region 110 and disconnected at the other end.
Alternatively, forming the first current blocking region 210 and the second current blocking region 220 on the substrate layer 100 includes: the first current blocking region 210 and the second current blocking region 220 are respectively formed on the substrate layer 100 by ion implantation.
Optionally, the doping depth of the first current blocking region 210 and the second current blocking region 220 is greater than 100 nm.
For example, as shown in fig. 1, the first current blocking region 210 and the second current blocking region 220 may be formed on the substrate layer 100 by ion implantation, which may be formed by coating a photoresist on the substrate, exposing, developing, and etching, so that the patterned photoresist covers only the top surface of the channel region 110, forming the first current blocking region 210 and the second current blocking region 220 in the regions not covered by the patterned photoresist (which may or may not be connected), and then removing the photoresist to form the substrate layer 100 that is flat and has the first current blocking region 210, the channel region 110, and the second current blocking region 220. The depth of the ion implantation (doping), i.e. in a direction perpendicular to the plane of the substrate layer 100, may be more than 100 nm. The current barrier layer is realized by ion implantation and can be H, He, O, N, F and other ions.
Optionally, forming the first current blocking region 210 and the second current blocking region 220 on the substrate layer 100 includes: etching the substrate layer 100 to form a first etching groove 211 and a second etching groove 221 which are adjacent, wherein a mesa structure is arranged between the first etching groove 211 and the second etching groove 221; epitaxially growing a current blocking layer on the substrate layer 100; the current blocking layer is subjected to surface planarization to expose the mesa structure, a portion of the current blocking layer, which is located in the first etching groove 211 after the surface planarization, is a first current blocking region 210, a portion of the current blocking layer, which is located in the second etching groove 221 after the surface planarization, is a second current blocking region 220, and the mesa structure, which is located between the first current blocking region 210 and the second current blocking region 220, is a channel region 110.
For example, in S010, when the first current blocking region 210 and the second current blocking region 220 are formed by epitaxial growth, as shown in fig. 4, the following steps may be performed for schematically:
s011: the substrate layer 100 is etched to form a first etching groove 211 and a second etching groove 221 which are adjacent to each other, and a mesa structure is formed between the first etching groove 211 and the second etching groove 221.
Referring to fig. 5, the substrate layer 100 is etched to form two adjacent first etching trenches 211 and second etching trenches 221 and a mesa structure between the first etching trenches 211 and the second etching trenches 221.
S012: a current blocking layer is epitaxially grown on the substrate layer 100.
And then, epitaxially growing a current blocking layer on the whole etched substrate layer 100, wherein the material of the current blocking layer can be a P-type material, an N-type material or a dielectric material. The thickness of the grown current blocking layer may be less than the thickness of the mesa structure. All thicknesses in this application refer to values in a direction perpendicular to the plane of the substrate.
S013: the current blocking layer is subjected to surface planarization to expose the mesa structure, a portion of the current blocking layer, which is located in the first etching groove 211 after the surface planarization, is a first current blocking region 210, a portion of the current blocking layer, which is located in the second etching groove 221 after the surface planarization, is a second current blocking region 220, and the mesa structure, which is located between the first current blocking region 210 and the second current blocking region 220, is a channel region 110.
As shown in fig. 6, the surface of the current blocking layer is planarized, so that the top surface of the substrate layer 100 is relatively flat, and the planarization process may be a polishing process, such as introducing a CMP process, i.e., a chemical mechanical polishing process, which can make the polished whole wafer have a micron-level flatness of less than 1 nm. Meanwhile, the method can also assist wet etching, thereby reducing the surface dislocation density to a certain degree (EPD is less than 1000/cm)2). Thereby reducing the defects of the subsequent epitaxial growth material and improving the quality of the material.
In the surface planarization process, the mesa structure needs to be exposed so that the mesa structure as the channel region 110 can make good contact with the lower planarization clad layer 400. The first current blocking region 210, the second current blocking region 220, and the top surface 111 of the channel region may all be located on the same plane through the surface planarization process.
Optionally, the thickness of the channel region 110 is greater than or equal to 20 nm.
For example, as shown in fig. 8, the thickness H of the channel region 110 (i.e., the thickness of the mesa structure subjected to the surface planarization process) may be equal to or greater than 20nm, and further may be equal to or greater than 100 nm. The higher the thickness of the channel region 110, the better the current effect.
Optionally, the width of the channel region 110 in the direction from the first current blocking region 210 to the second current blocking region 220 is greater than 0.1 μm.
For example, the width W of the channel region 110 may be the maximum distance from the first current blocking region 210 to the second current blocking region 220 in the lateral direction as shown in fig. 9, and the width W of the channel region 110 may be 0.1 to 500 μm, and further may be 5 to 200 μm, and may be appropriately selected according to the size of the device and the implementation capability of the lithography machine when specifically configured.
Optionally, the channel region 110 is an N-type region, and the first current blocking region 210 and the second current blocking region 220 are P-type layers; alternatively, the channel region 110 is a P-type region, and the first and second current blocking regions 210 and 220 are N-type layers.
Illustratively, as shown in fig. 7, the included angle a between the side surface 112 of the channel region and the top surface 111 of the channel region is an obtuse angle, so that the mesa structure forms a trapezoid structure, which can facilitate the growth of the subsequent epitaxial growth layer. In other embodiments, the angle between the side surface 112 of the channel region and the top surface 111 of the channel region may be acute, right-angled, or the like.
Optionally, the orthographic projection shape of the channel region 110 on the substrate layer 100 is one of a rectangle, a triangle and a trapezoid. The shape of the channel region 110 in the orthographic projection of the substrate layer 100 may also be a gradual pattern from one end to the other, such as a triangle, a trapezoid, etc., and when the pattern is a gradual pattern, the gradual angle may be less than 10 degrees. As shown in fig. 11, the orthographic shape of the channel region 110 on the substrate layer 100 is trapezoidal.
Optionally, the substrate layer structure comprises a plurality of substrate layers 100 formed with a first current blocking region 210, a channel region 110 and a second current blocking region 220, the plurality of substrate layers 100 are arranged in an array, and when the semiconductor device is a semiconductor laser, a bar of the laser can be matched.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (10)
1. A method of fabricating a semiconductor device, the method comprising:
forming a first current blocking area and a second current blocking area on a substrate layer, wherein the part of the substrate layer between the first current blocking area and the second current blocking area is a channel area, the first current blocking area, the second current blocking area and the top surface of the channel area are positioned on the same plane, and the plane is parallel to the bottom surface of the substrate layer;
forming a planarization functional layer on the substrate layer on which the first current blocking region, the channel region, and the second current blocking region are formed.
2. The method for manufacturing a semiconductor device according to claim 1, wherein the forming of a planarizing functional layer on the substrate layer where the first current blocking region, the channel region, and the second current blocking region are formed comprises:
and sequentially forming a flat lower cladding layer, a lower limiting layer, a quantum well, an upper limiting layer, an upper cladding layer and an ohmic contact layer on the substrate layer on which the first current blocking region, the channel region and the second current blocking region are formed.
3. The method for manufacturing a semiconductor device according to claim 1, wherein the forming of the first current blocking region and the second current blocking region in the substrate layer, a portion of the substrate layer between the first current blocking region and the second current blocking region being a channel region comprises:
and forming the first current blocking area and the second current blocking area on the substrate layer at intervals on two sides of the channel area.
4. The method for manufacturing a semiconductor device according to claim 1, wherein the forming of the first current blocking region and the second current blocking region in the substrate layer, a portion of the substrate layer between the first current blocking region and the second current blocking region being a channel region comprises:
and forming the first current blocking region and the second current blocking region on the substrate layer, wherein the first current blocking region and the second current blocking region are arranged around the periphery of the channel region and are connected with each other.
5. The method for manufacturing a semiconductor device according to claim 1, wherein the forming of the first current blocking region and the second current blocking region on the substrate layer comprises:
and respectively forming the first current blocking region and the second current blocking region on the substrate layer by ion implantation.
6. The method for manufacturing a semiconductor device according to claim 5, wherein a doping depth of the first current blocking region and the second current blocking region is greater than 100 nm.
7. The method for manufacturing a semiconductor device according to claim 1, wherein the forming of the first current blocking region and the second current blocking region in the substrate layer comprises:
etching the substrate layer to form a first etching groove and a second etching groove which are adjacent, wherein a mesa structure is arranged between the first etching groove and the second etching groove;
epitaxially growing a current blocking layer on the substrate layer;
and performing surface planarization treatment on the current blocking layer to expose the mesa structure, wherein the part of the current blocking layer, which is positioned in the first etching groove after the surface planarization treatment, is the first current blocking area, the part of the current blocking layer, which is positioned in the second etching groove after the surface planarization treatment, is the second current blocking area, and the mesa structure, which is positioned between the first current blocking area and the second current blocking area, is the channel area.
8. The method for manufacturing a semiconductor device according to any one of claims 1 to 7, wherein a thickness of the channel region is 20nm or more.
9. The method for manufacturing a semiconductor device according to any one of claims 1 to 7, wherein a width of the channel region in a direction from the first current blocking region to the second current blocking region is greater than 0.1 μm.
10. The method for manufacturing a semiconductor device according to any one of claims 1 to 7, wherein the channel region is an N-type region, and the first current blocking region and the second current blocking region are P-type layers; or, the channel region is a P-type region, and the first current blocking region and the second current blocking region are N-type layers.
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| CN115207775A (en) * | 2022-09-15 | 2022-10-18 | 日照市艾锐光电科技有限公司 | Semiconductor laser based on channel waveguide substrate and preparation method thereof |
| US20230104488A1 (en) * | 2021-10-06 | 2023-04-06 | Ii-Vi Delaware, Inc. | Control Of Current Spread In Semiconductor Laser Devices |
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