CN112614839A - Memory structure, three-dimensional memory and manufacturing method thereof - Google Patents

Memory structure, three-dimensional memory and manufacturing method thereof Download PDF

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CN112614839A
CN112614839A CN202011466326.5A CN202011466326A CN112614839A CN 112614839 A CN112614839 A CN 112614839A CN 202011466326 A CN202011466326 A CN 202011466326A CN 112614839 A CN112614839 A CN 112614839A
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substrate
stack
dimensional memory
isolation
stack structure
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CN112614839B (en
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张坤
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Yangtze Memory Technologies Co Ltd
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Yangtze Memory Technologies Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/10—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/10—EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region

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Abstract

The invention provides a storage structure, a three-dimensional memory and a manufacturing method thereof.A grid line separating groove for dividing two adjacent block structures is removed, only the grid line separating groove for dividing the interior of the block structure is reserved, a part is reserved when a pseudo grid layer is removed, the reserved pseudo grid layer forms an isolation structure, and different block structures can be isolated in a partitioned mode through the isolation structure; the reserved pseudo gate layer connects the adjacent block structures together, so that the structure is more stable, the support to the stack structure is increased, and the yield of devices is improved; the grid line separating grooves between the block structures are omitted, so that the etching workload of the grid line separating grooves is reduced, the thermal process is reduced, the change and the warping of the stress of the substrate are reduced, and the film forming quality is improved; the grid line separating groove between the block structures is omitted, the occupied area of the grid line separating groove is reduced, the area of a chip is saved on the basis of the same storage capacity, and the high-density and structure miniaturization design of a device is facilitated.

Description

Memory structure, three-dimensional memory and manufacturing method thereof
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a storage structure, a three-dimensional memory and a manufacturing method thereof.
Background
The three-dimensional memory is a technology for stacking data units, can realize the stacking of 32 layers or more of data units at present, overcomes the limitation of the practical expansion limit of a plane memory, further improves the storage capacity, reduces the storage cost of each data bit, and reduces the energy consumption.
However, the steps of the manufacturing process of the three-dimensional memory are complicated, almost all the steps involve heating, cooling and other thermal processes, each thermal process can cause the change of the internal stress of the substrate, and the change of the stress of the substrate can cause the substrate to warp to different degrees, thereby affecting the film forming quality and the yield of subsequent devices; in addition, in the formation process of the three-dimensional memory, with the increase of the number of stacked layers, the risk of unstable structure and even collapse can be faced in the device manufacturing process, and the yield is seriously affected. The demand for memory capacity and cost considerations typically increase the number of stacked layers, which in turn leads to unstable structures and substrate warpage, which is a conflict between memory capacity and structural stability and substrate warpage.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, it is an object of the present invention to provide a method for manufacturing a three-dimensional memory with improved separation structure between memory blocks, so as to solve the above-mentioned technical problems.
To achieve the above and other related objects, the present invention provides, in a first aspect, a method for manufacturing a three-dimensional memory, comprising the steps of:
providing a first substrate;
forming a stack structure on the first substrate, the stack structure including a stack of alternating first dielectric layers and dummy gate layers, and the stack structure including a step region and a core region adjacently disposed along a first direction, the stack structure further including a plurality of block structures adjacently disposed along a second direction;
forming a plurality of grid line separation grooves penetrating through the stack structure along a third direction in the block structure, wherein the grid line separation grooves are intermittently distributed in the step area and the core area along the first direction;
removing the dummy gate layer along the gate line separation groove, reserving a part of the dummy gate layer in an edge area of the block structure, and forming an isolation structure with the first dielectric layer to divide the stack structure into a plurality of the block structures;
wherein, in a stack plane of the stack structure, the second direction is perpendicular to the first direction, and the third direction is perpendicular to both the second direction and the first direction.
Optionally, after forming the stack structure and before forming the gate line separation groove, the method for manufacturing the three-dimensional memory further includes:
forming a step structure in the step region, the step structure comprising a plurality of steps;
forming a second dielectric layer covering the step structure and the core region;
a conductive channel structure is formed in the core region.
Optionally, the plurality of gate line separating grooves are arranged at intervals in the second direction according to a first pitch and a second pitch which are alternately arranged, the dummy gate layer is divided into a plurality of dummy gate segments with lengths of the first pitch and the second pitch in the second direction, and the first pitch is smaller than the second pitch.
Optionally, after forming the gate line separation groove and before etching to remove the dummy gate layer, the method for manufacturing the three-dimensional memory further includes:
forming a top isolation structure, wherein the top isolation structure and the isolation structure divide the stack structure into a plurality of the block structures.
Optionally, the step of forming the top insulating structure comprises:
etching the stack structure to form a plurality of isolation grooves, wherein the isolation grooves extend in the step area and the core area along the first direction, the isolation grooves are arranged at intervals in the second direction, and the projection of each isolation groove on the stack structure along the third direction is positioned in the middle of the dummy gate section with the length of the dummy gate section being the second distance;
and filling the isolation groove to form the top isolation structure.
Optionally, the isolation trench penetrates through the plurality of first dielectric layers and the plurality of dummy gate layers on the top of the stack structure.
Optionally, when the dummy gate layer is etched and removed along the gate line separation groove, in the second direction, the dummy gate segments with the length of the first interval are completely removed, and the dummy gate segments with the length of the second interval have a certain width.
Optionally, the method for manufacturing the three-dimensional memory further comprises the steps of:
along the grid line separation groove, replacing the removal part of the dummy grid layer to form a grid layer;
and filling the grid line separation groove to form a grid line separation structure.
Optionally, the method for manufacturing the three-dimensional memory further includes:
forming first conductive plugs and second conductive plugs, wherein the first conductive plugs and the second conductive plugs are arranged in the second dielectric layer, the first conductive plugs penetrate through the second dielectric layer and are connected with the steps in a one-to-one correspondence mode, and the second conductive plugs penetrate through the second dielectric layer to the substrate;
and forming a first bonding contact part, wherein the first bonding contact part leads out the first conductive plug, the second conductive plug and the conductive channel structure.
Optionally, the method for manufacturing the three-dimensional memory further includes:
forming a drive control structure, wherein the drive control structure comprises a second substrate, a drive circuit and a second bonding contact part, the drive circuit and the second bonding contact part are arranged on the front surface of the second substrate, and the drive circuit is led out of the second bonding contact part; bonding the second bonding contact with the first bonding contact.
Optionally, the method for manufacturing the three-dimensional memory further comprises the steps of:
picking up a well region of the first substrate from a backside of the first substrate;
and forming an external bonding pad of the three-dimensional memory on the back surface of the first substrate.
Optionally, the method for manufacturing the three-dimensional memory further comprises the steps of:
picking up a well region of the first substrate from a backside of the first substrate;
and forming an external bonding pad of the three-dimensional memory on the back surface of the second substrate.
Optionally, the method for manufacturing the three-dimensional memory further comprises the steps of:
picking up a well region of the first substrate from a front side of the first substrate and electrically connecting the well region with the drive control structure;
and forming an external bonding pad of the three-dimensional memory on the back surface of the first substrate.
Optionally, the method for manufacturing the three-dimensional memory further comprises the steps of:
picking up a well region of the first substrate from a front side of the first substrate and electrically connecting the well region with the drive control structure;
and forming an external bonding pad of the three-dimensional memory on the back surface of the second substrate.
To achieve the above and other related objects, the present invention further provides a memory structure, comprising:
a first substrate comprising a front side and a back side disposed opposite to each other;
a stack structure disposed on a front surface of the first substrate, including a stack of alternating first dielectric layers and gate layers, and including a step region and a core region adjacently disposed along a first direction;
the conductive channel structure is arranged in the core region and vertically penetrates through the stack structure along a third direction;
dividing the stack structure into a plurality of isolation structures of block structures, vertically penetrating the stack structure along the third direction, and extending in the step area and the core area along the first direction;
wherein, in a stack plane of the stack structure, the second direction is perpendicular to the first direction, and the third direction is perpendicular to both the second direction and the first direction.
Optionally, the memory structure further includes a gate line separation structure disposed in the block structure, the gate line separation structure vertically penetrates through the stack structure along the third direction, and the gate line separation structure is intermittently distributed in the step area and the core area along the first direction.
Optionally, the isolation structure comprises:
and stacking a plurality of first dielectric layers and dummy gate layers which are alternately arranged.
Optionally, the storage structure further comprises:
and the top isolation structure and the isolation structure divide the stack structure into a plurality of block structures.
Optionally, the top isolation structure extends through the plurality of first dielectric layers and the plurality of gate layers on top of the stack structure.
To achieve the above and other related objects, there is also provided a three-dimensional memory including:
the storage structure comprises a first substrate, a stack structure and a first bonding contact part, wherein the stack structure is arranged on the front surface of the first substrate, and the first bonding contact part is arranged on the stack structure;
the driving control structure comprises a second substrate, a driving circuit and a second bonding contact part, wherein the driving circuit and the second bonding contact part are arranged on the front surface of the second substrate, and the driving circuit is led out of the second bonding contact part;
a bonding interface between the first bonding contact and the second bonding contact, the first bonding contact contacting the second bonding contact at the bonding cross-section, forming an electrical connection between the storage structure and the drive control structure;
wherein the memory structure further comprises an isolation structure and a gate line separation structure; the isolation structure vertically penetrates through the stack structure to divide the stack structure into different block structures; the grid line separation structure vertically penetrates through the stack structure and divides the inside of the block structure.
Optionally, the stack structure comprises a first dielectric layer and a gate layer stacked alternately, and the isolation structure comprises:
and stacking a plurality of first dielectric layers and dummy gate layers which are alternately arranged.
Optionally, the storage structure further includes a top isolation structure disposed within the stack structure and on the isolation structure.
Optionally, the three-dimensional memory further comprises:
the well region pickup area is formed on the back surface of the first substrate; and
and the external connection bonding pad is formed on the back surface of the first substrate.
Optionally, the three-dimensional memory further comprises:
the well region pickup area is formed on the back surface of the first substrate; and
and the external connection bonding pad is formed on the back surface of the second substrate.
Optionally, the three-dimensional memory further comprises:
the well region pickup area is formed on the front surface of the first substrate; and
and the external connection bonding pad is formed on the back surface of the first substrate.
Optionally, the three-dimensional memory further comprises:
the well region pickup area is formed on the front surface of the first substrate; and
and the external connection bonding pad is formed on the back surface of the second substrate.
As described above, the memory structure, the three-dimensional memory and the manufacturing method thereof provided by the invention have at least the following advantages:
when the dummy gate layer is removed along the gate line separation groove in an etching mode, in the second direction, a part of the dummy gate layer is reserved in the edge area of the block structure, an isolation structure is formed by the reserved dummy gate layer and the first dielectric layer of the corresponding stack, and different block structures can be isolated in a partitioned mode through the isolation structure; the reserved pseudo gate layer connects the adjacent block structures together, so that the structure is more stable, the support to the stack structure is increased, and the yield of devices is improved; the grid line separating grooves between the block structures are omitted, so that the etching workload of the grid line separating grooves is reduced, the thermal process is reduced, the change of the stress of the substrate is reduced, the warping of the substrate is reduced, the film forming quality is improved, and the yield of devices is further improved; in addition, the grid line separating grooves between the block structures are omitted, the occupied area of the grid line separating grooves is reduced, the chip area is saved on the basis of the same storage capacity, and the high-density and structure miniaturization design of the device is facilitated.
Drawings
Fig. 1-2 are schematic structural diagrams of a three-dimensional memory.
FIG. 3 is a schematic diagram illustrating a method for fabricating a memory structure according to an embodiment of the invention.
Fig. 4-20 are process flow diagrams illustrating a method of fabricating a memory structure according to one embodiment of the invention.
Fig. 21-26 are process flow diagrams illustrating a method for fabricating a three-dimensional memory according to a second embodiment of the invention.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 1 to 26. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated. The structures, proportions, sizes, and other dimensions shown in the drawings and described in the specification are for understanding and reading the present disclosure, and are not intended to limit the scope of the present disclosure, which is defined in the claims, and are not essential to the art, and any structural modifications, changes in proportions, or adjustments in size, which do not affect the efficacy and attainment of the same are intended to fall within the scope of the present disclosure. In addition, the terms "upper", "middle", "first" and "second" used in the present specification are for clarity of description, and are not intended to limit the scope of the present invention, and the relative relationship between the terms and the relative positions may be changed or adjusted without substantial technical change.
The inventor researches and discovers that: in the manufacturing process of the current three-dimensional memory, as shown in fig. 1 and fig. 2, a gate line separation groove GLS is usually formed, a dummy gate layer in the stack structure 2 is removed and replaced to form a gate layer, and finally, the gate line separation groove GLS is filled to form a common source of a Block structure Block, and the memory structure is divided into different Block structures Block, or the inside of the Block structure Block is divided into a plurality of sub-blocks to separate the electrical connections of the different sub-blocks; in the method, more grid line separating grooves GLS are required to be formed, and in the process of removing the pseudo grid layer through the grid line separating grooves GLS, the supporting and supporting of the stack structure 2 are fragile, so that the phenomena of collapse, collapse and the like of the structure are easily caused, and the yield of devices is further influenced; in addition, the more gate line separating grooves GLS increase the burden of the etching process, so that the stack structure 2 is subjected to more thermal processes, which may cause more stress problems, and increase the warpage or bending degree of the substrate 1, which finally results in that the substrate 1 cannot be subjected to subsequent processes in a machine.
Based on this, the invention provides a manufacturing method of a three-dimensional memory, which comprises the following steps: the grid line separating grooves GLS for separating different Block structures are removed, only the grid line separating grooves GLS for separating the interior of the Block structures are reserved, and a dummy gate layer with a certain width is remained between every two adjacent Block structures by using the fact that the etching distance is limited when the dummy gate layer is removed through etching of the grid line separating grooves GLS, so that the integrity of a stack structure is strengthened and the structural support of a device is enhanced while the physical isolation between every two adjacent Block structures is realized.
The present invention will be described in detail below by way of specific embodiments with reference to the accompanying drawings.
Example one
An embodiment of the present invention provides a method for manufacturing a three-dimensional memory, as shown in fig. 3, the method includes:
s1, providing a first substrate 10;
s2, forming a stack structure 2 on the first substrate 1, the stack structure 2 including a stack of alternating first dielectric layers 21 and dummy gate layers 22, and the stack structure 2 including a step region 2A and a core region 2B adjacently disposed along a first direction (i.e., positive X-axis direction), the stack structure 2 further including a plurality of Block structures Block adjacently disposed along a second direction (i.e., positive Y-axis direction);
s3, forming a plurality of grid line separation grooves GLS penetrating the stack structure 2 along a third direction (i.e. a Z-axis negative direction) inside the Block structure Block, where the grid line separation grooves GLS are intermittently distributed in the step region 2A and the core region 2B along the first direction;
s4, separating the trenches GLS along the gate lines, removing the dummy gate layer 22, leaving a portion of the dummy gate layer 22 in the edge region of the Block structure Block, and forming an isolation structure with the first dielectric layer 21 to divide the stack structure 2 into a plurality of Block structures Block;
wherein, in the stacking plane (i.e. XY plane) of the stack structure 2, the second direction is perpendicular to the first direction, and the third direction is perpendicular to both the second direction and the first direction.
In detail, as shown in fig. 4, in step S1, the first substrate 10 has a front surface 10a and a back surface 10b disposed oppositely, and a well region (not shown in the figure) is formed in the first substrate 10; the first substrate 10 may be a single crystal silicon substrate, a Ge substrate, a SiGe substrate, an SOI substrate, a GOI substrate, or the like, and an appropriate semiconductor material may be selected according to actual requirements of the device, which is not limited herein.
In more detail, as shown in fig. 4, the first substrate 10 is a composite layer structure, and includes a first semiconductor layer 101, a second semiconductor layer 102, and a third semiconductor layer 103, which are sequentially stacked from bottom to top. The third semiconductor layer 103 is a sacrificial layer and is replaced later.
In detail, as shown in fig. 5, in step S2, a plurality of stacked alternating first dielectric layers 21 and dummy gate layers 22 are formed on the first substrate 10, resulting in a stacked structure 2, i.e. the stacked structure 2 includes a plurality of stacked alternating first dielectric layers 21 and dummy gate layers 22, and the number of stacked layers of the first dielectric layers 21 and the dummy gate layers 22 can be flexibly designed according to the situation. Wherein one first dielectric layer 21 and an adjacent dummy gate layer 22 form a composite layer, i.e. the stack structure 2 comprises multiple composite layers.
In more detail, as shown in fig. 5, in step S2, along the first direction, the stack structure 2 includes a step area 2A and a core area 2B; it is understood that there may be various situations in the positional relationship between the stepped region 2A and the core region 2B in the first direction, such as the presence of one core region 2B on both sides of the stepped region 2A, or the presence of one stepped region 2A on both sides of the core region 2B.
Alternatively, as shown in fig. 6 to 8, after the stack structure 2 is formed and before the gate line separation groove GLS is formed, the method for manufacturing the three-dimensional memory device further includes the steps of:
stp1, as shown in fig. 6, a step structure 3 is formed in the step region 2A, the step structure 3 including a plurality of steps 3 a;
stp2, as shown in fig. 7, forming a second dielectric layer 23, the second dielectric layer 23 covering the step structure 3 and the core region 2B;
stp3, as shown in fig. 8, a conductive channel structure 4 is formed in the core region 2B.
In detail, as shown in fig. 6, in step Stp1, step region 2A is etched, step structure 3 is formed in step region 2A, step structure 3 includes a plurality of steps 3a extending in sequence along a first direction, and each step 3a includes a first dielectric layer 21 and a dummy gate layer 22.
In detail, as shown in fig. 7, in step Stp2, the second dielectric layer 23 is formed, and the second dielectric layer 23 covers the step structure 3 and the core region 2B to protect the step structure 3 formed by etching.
In detail, as shown in fig. 8, in step Stp3, the step region 2A is etched, and the conductive channel structure 4 is formed in the core region 2B by etching to form a channel hole and then depositing and filling the channel hole step by step, and the specific structure and formation process of the conductive channel structure 4 may refer to the prior art and are not described herein again.
In detail, as shown in fig. 9 to 10, in step S3, a plurality of gate line separation grooves GLS are formed inside the Block structure Block to penetrate through the stack structure 2 in the third direction, the gate line separation grooves GLS are intermittently distributed in the step region 2A and the core region 2B along the first direction (not shown in the figure), and the plurality of gate line separation grooves GLS are alternately arranged in the second direction (i.e., the positive direction of the Y axis) at a first pitch D1 and a second pitch D2, and the dummy gate layer 22 is divided into a plurality of dummy gate segments having a length of the first pitch D1 and a length of the second pitch D2 in the second direction, wherein the first pitch D1 is smaller than the second pitch D2.
The first distance D1 (or the second distance D2) refers to a distance between two adjacent gate line separation grooves GLS in the second direction.
In detail, as shown in fig. 11 to 15, after forming the gate line separation groove GLS and before etching to remove the dummy gate layer 22, the method for manufacturing the three-dimensional memory further includes the steps of:
stp4, as shown in fig. 11, the third semiconductor layer 103 is etched away along the gate line separation grooves GLS;
stp5, as shown in fig. 12, the peripheral dielectric layer of the conducting channel structure 4 at the position of the third semiconductor layer 103 is etched and removed along the gate line separating groove GLS to expose the channel layer of the conducting channel structure 4;
stp6, as shown in fig. 13, a fourth semiconductor layer 104 is formed at a position where the third semiconductor layer 103 is located along the gate line separation trench GLS to form a common source structure of the memory array;
stp7, as shown in fig. 14, etching the stack structure 2 to form a plurality of isolation trenches T, where the isolation trenches T extend in the step region 2A and the core region 2B along the first direction, the isolation trenches T are arranged at intervals in the second direction, and a projection of each isolation trench T on the stack structure 2 is located in a middle of a dummy gate segment with a length of the second interval D2;
stp8, as shown in FIG. 15, fills the isolation trench T to form the top isolation structure 5.
In more detail, as shown in fig. 14, in step Stp7, isolation trenches T are disposed within the stack structure 2 and penetrate through the first dielectric layers 21 and the dummy gate layers 22 at the top of the stack structure 2.
In more detail, as shown in fig. 15, in step Stp8, the isolation trenches T are filled with a dielectric material to form the isolation structure 5.
In detail, as shown in fig. 9 and 16, when the dummy gate layer 22 is etched and removed along the gate line separating groove GLS in step S4, the dummy gate segments having the length of the first distance D1 are completely removed in the second direction, and the etching distance is limited due to the larger second distance D2, and a certain width is remained at the middle position of the dummy gate segments having the length of the second distance D2.
In detail, as shown in fig. 17 to 18, the method of manufacturing the three-dimensional memory further includes the steps of:
s5, as shown in fig. 17, the gate layer 24 is formed by replacement on the removed portion of the dummy gate layer 22 along the gate line separation groove GLS;
s6, as shown in fig. 18, the gate line separation grooves GLS are filled to form the gate line separation structures 6, and the inside of the Block structure Block is partitioned.
The gate layer 24 is a composite layer structure including a metal barrier layer and a metal conductive layer, and the detailed structure and process thereof can refer to the prior art and are not described herein again.
Optionally, as shown in fig. 19 to 20, the method for manufacturing a three-dimensional memory further includes:
s7, as shown in fig. 19, forming a first conductive plug CT1 and a second conductive plug CT2, wherein the first conductive plug CT1 and the second conductive plug CT2 are both disposed in the second dielectric layer 23, a plurality of first conductive plugs CT1 penetrate through the second dielectric layer 23 and are connected with the steps 3a in a one-to-one correspondence manner, and a second conductive plug CT2 penetrates through the second dielectric layer 23 to the substrate 1;
s8, as shown in fig. 20, a first bonding contact is formed, and the first bonding contact leads out the first conductive plug CT1, the second conductive plug CT2 and the conductive channel structure 4.
In detail, as shown in fig. 19 to 20, in step S7, a plurality of first conductive plugs CT1 are connected to a plurality of steps 3a in a one-to-one correspondence, and the gate layer 24 in each step 3a is electrically led out; a second conductive plug CT2 is inserted through the second dielectric layer 23 for electrical connection of subsequent logic circuits or well regions, etc.
In detail, as shown in fig. 20, in step S8, a first bonding contact is formed, and the first bonding contact leads out the first conductive plug CT1, the second conductive plug CT2, and the conductive channel structure 4 through a metal wire.
Through the above series of steps, the memory structure in the three-dimensional memory shown in fig. 20 is finally obtained, which includes:
a first substrate 10 including a front surface 10a and a back surface 10b disposed oppositely;
a stack structure 2' disposed on the front surface of the first substrate 10a, including a stack of alternating first dielectric layers 21 and gate layers 24, and including a step region 2A and a core region 2B disposed in a first direction, and further including a plurality of Block structures Block adjacently disposed in a second direction;
the conductive channel structure 4 is arranged in the core region 2B and vertically penetrates through the stack structure 2' along a third direction;
the isolation structure (shown by a dashed box in the figure) vertically penetrates through the stack structure 2 'along the third direction, and extends in the step area 2A and the core area 2B along the first direction to divide the stack structure 2' into different Block structures Block;
grid line separation structure 6 sets up in Block structure Block, runs through stack structure 2' perpendicularly along the third direction, and distributes intermittently in step area 2A and core area 2B along the first direction, divides into the inside of Block structure Block.
In detail, as shown by a dotted line box in fig. 20, the isolation structure includes:
several first dielectric layers 21 and dummy gate layers 22 are stacked alternately.
In detail, as shown in fig. 20, the storage structure further includes:
and a top isolation structure 5 arranged on the isolation structure, wherein the stack structure 2' is divided into a plurality of Block structures Block by the top isolation structure 5 and the isolation structure.
Therefore, in this embodiment, after the gate line separating grooves GLS for separating and isolating two adjacent Block structures Block are removed, when wet etching is performed on the dummy gate layer 22 through other gate line separating grooves GLS, the dummy gate layer 22 is partially left by using the limitation of the etching distance, and physical isolation between two adjacent Block structures Block can be realized through the remaining dummy gate layer 22; meanwhile, the isolation structure 5 arranged at the top of the stack structure 2 can realize physical isolation between two adjacent Block structures Block when the top layer of the stack structure 2 is over-etched to remove all the dummy gates 22, thereby further strengthening the physical isolation between the two Block structures Block; the reserved pseudo gate layer 22 connects the adjacent Block structures together, so that the structure is more stable, the support to the stack structure 2 is increased, and the yield of devices is improved; the grid line separating grooves GLS between the Block structures Block are omitted, so that the etching workload of the grid line separating grooves GLS is reduced, the thermal process is reduced, the change and the warping degree of the substrate stress are reduced, the film forming quality is improved, and the yield of devices is further improved; in addition, the grid line separating grooves GLS between the Block structures Block are omitted, the occupied area of the grid line separating grooves GLS is reduced, the chip area is saved on the basis of the same storage capacity, and the high-density and structure miniaturization design of the device is facilitated.
Example two
The manufacturing method of the three-dimensional memory provided by the embodiment one actually only completes the production and manufacturing of the storage structure in the three-dimensional memory and does not relate to the production and manufacturing of the peripheral driving control structure. Therefore, an embodiment of the present invention provides a method for manufacturing a three-dimensional memory based on the first embodiment, including:
sp1, forming a memory structure, forming the memory structure on the front side of the first substrate 10 by adopting the manufacturing method of the three-dimensional memory in the first embodiment of the invention, and forming a first bonding contact part on the top of the memory structure;
sp2, forming a driving control structure, wherein the driving control structure comprises a second substrate 20, a driving circuit 25 and a second bonding contact part, the driving circuit 25 and the second bonding contact part are arranged on the front surface of the second substrate 20, and the second bonding contact part leads out the driving circuit 25;
sp3, and the storage structure is electrically connected with the drive control structure through the bonding connection of the first bonding contact part and the second bonding contact part.
The step Sp1 of forming the memory structure may refer to the first embodiment, and is not described herein again; detailed structure of the memory structure as shown in fig. 20, the memory structure includes a stack structure 2', a conductive channel structure 4, an isolation structure (shown by a dashed line frame in the figure), a gate line separation structure 6, a first bonding contact, and the like, and the first bonding contact is disposed on the top of the memory structure.
In detail, as shown in fig. 21, in step Sp2, a second substrate 20 is provided, the second substrate 20 includes a front surface 20a and a back surface 20b, a driving circuit 25, a metal wiring and a second bonding contact are formed on the front surface 20a of the second substrate 20, and the driving circuit 25 may include various semiconductor devices, for example, a Metal Oxide Semiconductor Field Effect Transistor (MOSFET), a Bipolar Junction Transistor (BJT), a diode, a resistor, a capacitor, an inductor, etc.
Wherein the second bonding contact formed on the exposed surface of the driving control structure electrically leads out the driving circuit 25 through a metal wire, and the driving circuit 25 is electrically connected with the outside through the second bonding contact.
In detail, as shown in fig. 22, in step Sp3, the electrical connection between the storage structure and the driving control structure is realized through the bonding connection between the first bonding contact and the second bonding contact. In an alternative embodiment, the drive control structure is placed above and the memory structure is placed below for bonding, as shown in FIG. 22. A bonding interface is formed between the first bonding contact and the second bonding contact, and an electrical connection is formed at the bonding interface through a through hole process to connect the first bonding contact and the second bonding contact.
Optionally, the method for manufacturing the three-dimensional memory further comprises the steps of:
sp4, picking up the well region of the first substrate 10 from the back surface 10b of the first substrate 10, forming a well region pickup region 7;
sp5, forming an external connection pad 9 of the three-dimensional memory on the back surface 10b of the first substrate 10.
In detail, as shown in fig. 23, after the memory structure and the driving control structure are bonded in step Sp4, the back surface of the first substrate 10 of the memory structure is thinned (the first semiconductor layer 101 and a part of the second semiconductor layer 102 are removed), and then the well pickup is performed on the back surface 10b of the first substrate 10 to form the well pickup region 7; in step Sp5, well extraction pads 8 electrically connected to the well pickup regions 7 are formed on the back surface 10b of the first substrate 10, while external connection pads 9 are extracted at the back surface 10b of the first substrate 10.
Before that, a pad extraction layer 110 is formed at the back surface 10b of the thinned first substrate 10, a first through hole penetrating through the pad extraction layer 110 and the well region of the first substrate 10 may be formed by using a through hole technology, then a conductive material is filled in the first through hole to form a well region pickup region 7, and finally a well region extraction pad 8 electrically connected with the well region pickup region 7 is formed on the surface of the pad extraction layer 110. Meanwhile, a second through hole penetrating through the pad extraction layer 110 and the first substrate 10 may be formed by using a through hole technology, then a conductive material is filled in the second through hole to form a conductive structure, a part of the second metal plug CT2 is electrically extracted from the conductive structure, and finally an external pad 9 electrically connected with the conductive structure is formed on the surface of the pad extraction layer 110. Forming the well pickup region 7 at the rear surface 10b of the first substrate 10 can reduce the overall volume of the device and also improve the stress to the first substrate 10.
In an alternative embodiment, as shown in fig. 24, the well region of the first substrate 10 is also picked up from the back surface 10b of the first substrate 10, and the well region pickup region 7 and the well region lead-out pad 8 are formed; then, the external connection pad 9 of the three-dimensional memory is formed on the back surface 20b of the second substrate. Wherein, the step of forming the external connection pad 9 of the three-dimensional memory on the back surface 20b of the second substrate comprises: thinning the back surface 20b of the second substrate 20, forming a pad lead-out layer 111 at the back surface 20b of the thinned second substrate 20, forming a third through hole penetrating through the pad lead-out layer 11 and the second substrate 20 by adopting a through hole technology, then filling a conductive material in the third through hole to form a conductive structure, and finally forming an external pad 9 electrically connected with the conductive structure on the surface of the pad lead-out layer 111.
In another alternative embodiment, as shown in fig. 25, the well region of the first substrate 10 is picked up from the front side 10a of the first substrate 10 and electrically connected with the drive control structure; then, the external connection pad 9 of the three-dimensional memory is formed on the back surface 10b of the first substrate 10.
In yet another alternative embodiment, as shown in fig. 26, the well region of the first substrate 10 is picked up from the front side 10a of the first substrate 10 and electrically connected with the drive control structure; then, the external connection pad 9 of the three-dimensional memory is formed on the back surface 20b of the second substrate 20.
Finally, in the embodiment of the present invention, a three-dimensional memory as shown in fig. 23-26 is obtained, which includes:
a memory structure comprising a first substrate 10, a stack structure 2' and a first bonding contact, the stack structure 2' being disposed on a front side 10a of the first substrate 10, the first bonding contact being disposed on the stack structure 2 ';
the driving control structure comprises a second substrate 20, a driving circuit 25 and a second bonding contact part, wherein the driving circuit 25 and the second bonding contact part are arranged on the front surface 20a of the second substrate 20, and the driving circuit 25 is led out of the second bonding contact part;
a bonding interface between the first bonding contact and the second bonding contact, the first bonding contact contacting the second bonding contact at a bonding cross-section to form an electrical connection between the memory structure and the drive control structure;
wherein, the storage structure 2' further comprises an isolation structure and a gate line separation structure 6; the isolation structure vertically penetrates through the stack structure 2 'along a third direction, and the stack structure 2' is divided into different Block structures Block; the gate line partition structure 6 vertically penetrates the stack structure 2' in the third direction, and partitions the inside of the Block structure Block.
Wherein the stack structure 2' includes a first dielectric layer 21 and a gate layer 24 stacked alternately, and the isolation structure includes:
several first dielectric layers 21 and dummy gate layers 22 are stacked alternately.
In detail, the storage structure further includes a top isolation structure 5 disposed in the stack structure 2' and located at the top of the stack structure 2', and the top isolation structure 5 and the isolation structure divide the stack structure 2' into a plurality of Block structures Block.
In addition, the three-dimensional memory further includes a well pickup region 7 and an external pad 9, and the pickup of the well in the first substrate 10 (i.e., forming the well pickup region 7) and the formation of the external pad 9 may be performed in various manners as shown in fig. 23 to fig. 26, which is not described herein again.
In this embodiment, the memory structure has the same structure as the memory structure of the first embodiment, and therefore has the same technical effect. In addition, when the three-dimensional memory is formed in the embodiment, the pickup of the well region in the first substrate 10 of the memory structure and the formation of the external bonding pad 9 can be performed in various ways, so that the flexibility of the device design is increased.
In summary, in the memory structure, the three-dimensional memory and the manufacturing method thereof provided by the present invention, the gate line separating groove for dividing and isolating two adjacent block structures is removed, only the gate line separating groove for dividing and isolating the inside of the block structure is reserved, when the dummy gate layer is removed by etching along the gate line separating groove, the dummy gate segment with the length of the second interval in the second direction has a certain width, the reserved dummy gate layer and the first dielectric layer of the corresponding stack form an isolation structure, and different block structures can be divided and isolated by the isolation structure; the reserved pseudo gate layer connects the adjacent block structures together, so that the structure is more stable, the support to the stack structure is increased, and the yield of devices is improved; the grid line separating grooves between the block structures are omitted, so that the etching workload of the grid line separating grooves is reduced, the thermal process is reduced, the change of the stress of the substrate is reduced, the warping of the substrate is reduced, the film forming quality is improved, and the yield of devices is further improved; in addition, the grid line separating grooves between the block structures are omitted, the occupied area of the grid line separating grooves is reduced, the chip area is saved on the basis of the same storage capacity, and the high-density and structure miniaturization design of the device is facilitated.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims (26)

1. A method of fabricating a three-dimensional memory, comprising the steps of:
providing a first substrate;
forming a stack structure on the first substrate, the stack structure including a stack of alternating first dielectric layers and dummy gate layers, and the stack structure including a step region and a core region adjacently disposed along a first direction, the stack structure further including a plurality of block structures adjacently disposed along a second direction;
forming a plurality of grid line separation grooves penetrating through the stack structure along a third direction in the block structure, wherein the grid line separation grooves are intermittently distributed in the step area and the core area along the first direction;
removing the dummy gate layer along the gate line separation groove, reserving a part of the dummy gate layer in an edge area of the block structure, and forming an isolation structure with the first dielectric layer to divide the stack structure into a plurality of the block structures;
wherein, in a stack plane of the stack structure, the second direction is perpendicular to the first direction, and the third direction is perpendicular to both the second direction and the first direction.
2. The method of manufacturing a three-dimensional memory device according to claim 1, wherein after the forming of the stack structure and before the forming of the gate line separation groove, the method of manufacturing a three-dimensional memory device further comprises:
forming a step structure in the step region, the step structure comprising a plurality of steps;
forming a second dielectric layer covering the step structure and the core region;
a conductive channel structure is formed in the core region.
3. The method of claim 2, wherein the plurality of gate line separating grooves are alternately arranged in the second direction at first and second pitches, the dummy gate layer is divided into dummy gate segments having lengths of the first and second pitches in the second direction, and the first pitch is smaller than the second pitch.
4. The method of claim 3, wherein after the step of forming the gate line separating trench and before the step of etching away the dummy gate layer, the method further comprises the steps of:
forming a top isolation structure, wherein the top isolation structure and the isolation structure divide the stack structure into a plurality of the block structures.
5. The method of manufacturing a memory structure of claim 4, wherein the step of forming the top isolation structure comprises:
etching the stack structure to form a plurality of isolation grooves, wherein the isolation grooves extend in the step area and the core area along the first direction, the isolation grooves are arranged at intervals in the second direction, and the projection of each isolation groove on the stack structure along the third direction is positioned in the middle of the dummy gate section with the length of the dummy gate section being the second distance;
and filling the isolation groove to form the top isolation structure.
6. The method of claim 5, wherein the isolation trench extends through the first dielectric layers and the dummy gate layers at the top of the stack structure.
7. The method of claim 6, wherein the dummy gate segments having a length of the first pitch are completely removed in the second direction while the dummy gate layer is removed by etching along the gate line separating trench, and the dummy gate segments having a length of the second pitch have a width.
8. The method of manufacturing a three-dimensional memory according to claim 7, further comprising the steps of:
along the grid line separation groove, replacing the removal part of the dummy grid layer to form a grid layer;
and filling the grid line separation groove to form a grid line separation structure.
9. The method of manufacturing a three-dimensional memory according to claim 8, further comprising:
forming first conductive plugs and second conductive plugs, wherein the first conductive plugs and the second conductive plugs are arranged in the second dielectric layer, the first conductive plugs penetrate through the second dielectric layer and are connected with the steps in a one-to-one correspondence mode, and the second conductive plugs penetrate through the second dielectric layer to the substrate;
and forming a first bonding contact part, wherein the first bonding contact part leads out the first conductive plug, the second conductive plug and the conductive channel structure.
10. The method of manufacturing a three-dimensional memory according to claim 9, further comprising:
forming a drive control structure, wherein the drive control structure comprises a second substrate, a drive circuit and a second bonding contact part, the drive circuit and the second bonding contact part are arranged on the front surface of the second substrate, and the drive circuit is led out of the second bonding contact part; bonding the second bonding contact with the first bonding contact.
11. The method of manufacturing a three-dimensional memory according to claim 10, further comprising the steps of:
picking up a well region of the first substrate from a backside of the first substrate;
and forming an external bonding pad of the three-dimensional memory on the back surface of the first substrate.
12. The method of manufacturing a three-dimensional memory according to claim 10, further comprising the steps of:
picking up a well region of the first substrate from a backside of the first substrate;
and forming an external bonding pad of the three-dimensional memory on the back surface of the second substrate.
13. The method of manufacturing a three-dimensional memory according to claim 10, further comprising the steps of:
picking up a well region of the first substrate from a front side of the first substrate and electrically connecting the well region with the drive control structure;
and forming an external bonding pad of the three-dimensional memory on the back surface of the first substrate.
14. The method of manufacturing a three-dimensional memory according to claim 10, further comprising the steps of:
picking up a well region of the first substrate from a front side of the first substrate and electrically connecting the well region with the drive control structure;
and forming an external bonding pad of the three-dimensional memory on the back surface of the second substrate.
15. A memory structure, comprising:
a first substrate comprising a front side and a back side disposed opposite to each other;
a stack structure disposed on a front surface of the first substrate, including a stack of alternating first dielectric layers and gate layers, and including a step region and a core region adjacently disposed along a first direction;
the conductive channel structure is arranged in the core region and vertically penetrates through the stack structure along a third direction;
dividing the stack structure into a plurality of isolation structures of block structures, vertically penetrating the stack structure along the third direction, and extending in the step area and the core area along the first direction;
wherein, in a stack plane of the stack structure, the second direction is perpendicular to the first direction, and the third direction is perpendicular to both the second direction and the first direction.
16. The memory structure of claim 15, further comprising a gate line separation structure disposed within the block structure, the gate line separation structure extending vertically through the stack structure along the third direction, and the gate line separation structure being intermittently distributed within the mesa region and the core region along the first direction.
17. The memory structure of claim 16, wherein the isolation structure comprises:
and stacking a plurality of first dielectric layers and dummy gate layers which are alternately arranged.
18. The memory structure of claim 17, further comprising:
and the top isolation structure and the isolation structure divide the stack structure into a plurality of block structures.
19. The memory structure of claim 18, wherein the top isolation structure extends through a number of the first dielectric layers and a number of the gate layers at the top of the stack structure.
20. A three-dimensional memory, comprising:
the storage structure comprises a first substrate, a stack structure and a first bonding contact part, wherein the stack structure is arranged on the front surface of the first substrate, and the first bonding contact part is arranged on the stack structure;
the driving control structure comprises a second substrate, a driving circuit and a second bonding contact part, wherein the driving circuit and the second bonding contact part are arranged on the front surface of the second substrate, and the driving circuit is led out of the second bonding contact part;
a bonding interface between the first bonding contact and the second bonding contact, the first bonding contact contacting the second bonding contact at the bonding cross-section, forming an electrical connection between the storage structure and the drive control structure;
wherein the memory structure further comprises an isolation structure and a gate line separation structure; the isolation structure vertically penetrates through the stack structure to divide the stack structure into different block structures; the grid line separation structure vertically penetrates through the stack structure and divides the inside of the block structure.
21. The three-dimensional memory according to claim 20, wherein the stack structure comprises a stack of alternating first dielectric layers and gate layers, and wherein the isolation structure comprises:
and stacking a plurality of first dielectric layers and dummy gate layers which are alternately arranged.
22. The three-dimensional memory according to claim 21, wherein the storage structure further comprises a top isolation structure disposed within the stack structure and on the isolation structure.
23. The three-dimensional memory according to claim 22, further comprising:
the well region pickup area is formed on the back surface of the first substrate; and
and the external connection bonding pad is formed on the back surface of the first substrate.
24. The three-dimensional memory according to claim 22, further comprising:
the well region pickup area is formed on the back surface of the first substrate; and
and the external connection bonding pad is formed on the back surface of the second substrate.
25. The three-dimensional memory according to claim 22, further comprising:
the well region pickup area is formed on the front surface of the first substrate; and
and the external connection bonding pad is formed on the back surface of the first substrate.
26. The three-dimensional memory according to claim 22, further comprising:
the well region pickup area is formed on the front surface of the first substrate; and
and the external connection bonding pad is formed on the back surface of the second substrate.
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