CN112600629B - Method and system for realizing power calibration and data processing of radio frequency receiver of MIMO channel simulator - Google Patents

Method and system for realizing power calibration and data processing of radio frequency receiver of MIMO channel simulator Download PDF

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CN112600629B
CN112600629B CN202011468170.4A CN202011468170A CN112600629B CN 112600629 B CN112600629 B CN 112600629B CN 202011468170 A CN202011468170 A CN 202011468170A CN 112600629 B CN112600629 B CN 112600629B
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calibration
power
circuit
receiver
frequency
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CN112600629A (en
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解建红
江文冲
刘景鑫
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Southeast University
Shanghai TransCom Instruments Co Ltd
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Shanghai TransCom Instruments Co Ltd
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B17/00—Monitoring; Testing
    • H04B17/0082—Monitoring; Testing using service channels; using auxiliary channels
    • H04B17/0087—Monitoring; Testing using service channels; using auxiliary channels using auxiliary channels or channel simulators
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B17/00—Monitoring; Testing
    • H04B17/10—Monitoring; Testing of transmitters
    • H04B17/11—Monitoring; Testing of transmitters for calibration
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B17/00—Monitoring; Testing
    • H04B17/20—Monitoring; Testing of receivers
    • H04B17/21—Monitoring; Testing of receivers for calibration; for correcting measurements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B7/00—Radio transmission systems, i.e. using radiation field
    • H04B7/02—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas
    • H04B7/04—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas
    • H04B7/0413—MIMO systems
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
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    • Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks

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Abstract

The invention relates to a method for realizing power calibration and data processing of a radio frequency receiver of a MIMO channel simulator, which comprises the steps of calibrating the frequency response of an amplifier and a straight-through channel in a radio frequency channel and the frequency response of a numerical control attenuator of an individual frequency point according to the linear characteristic of the radio frequency numerical control attenuator through active circuit calibration and passive circuit calibration; and performing data calculation according to the existing calibration data, and processing to obtain a complete MIMO channel simulator receiver calibration table. The invention also relates to a system for realizing the power calibration and data processing of the radio frequency receiver of the MIMO channel simulator. By adopting the method and the system for realizing the power calibration and the data processing of the radio frequency receiver of the MIMO channel simulator, the calibration time of the receiver of the single-channel simulator is improved by 10-20 times, and the method and the system are particularly suitable for the power calibration of a transmitter of large-scale MIMO. The invention solves the contradiction between the calibration time and the power accuracy of the large-scale MIMO channel simulator receiver, namely reduces the total calibration time length and ensures the power accuracy.

Description

Method and system for realizing power calibration and data processing of radio frequency receiver of MIMO channel simulator
Technical Field
The invention relates to the technical field of communication measuring instrument calibration, in particular to the field of MIMO channel simulators, and specifically relates to a method and a system for realizing power calibration and data processing of a radio frequency receiver of the MIMO channel simulators.
Background
The number of antennas of the 5G MIMO channel simulator reaches 128 or even 256, and 128 or 256 channels corresponding to the number of the receiver channels of the MIMO channel simulator are provided. The accuracy of the received power is one of the important indicators of the performance of the channel simulator receiver, which is mainly dependent on the radio frequency circuitry in the receiver. In theory, the power accuracy of the channel simulator receiver can be guaranteed to be optimal for traversal calibration of different frequencies and different input powers. However, for a 256-channel MIMO system, if the traversal calibration is still employed, the calibration time would be necessarily undesirable because of the multiplication by 256. How to trade off between calibration total duration and power accuracy is important.
Thus, using the conventional walk-through calibration scheme is no longer applicable to 5G MIMO systems. On the premise of ensuring the power accuracy, how to quickly realize the power calibration of the MIMO channel simulator receiver is needed to be solved.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provides a method and a system for realizing power calibration and data processing of a radio frequency receiver of a MIMO channel simulator, which have the advantages of high accuracy, small error and wider application range.
In order to achieve the above object, the method for implementing power calibration and data processing of a MIMO channel simulator radio frequency receiver and the system thereof according to the present invention are as follows:
the method for realizing power calibration and data processing of the MIMO channel simulator radio frequency receiver is mainly characterized by comprising the following steps of:
(1) Calibrating the frequency response of an amplifier and a straight-through channel in a radio frequency channel and the frequency response of a numerical control attenuator of an individual frequency point according to the linear characteristics of the radio frequency numerical control attenuator by active circuit calibration and passive circuit calibration;
(2) And performing data calculation according to the existing calibration data, and processing to obtain a complete MIMO channel simulator receiver calibration table.
Preferably, the active circuit calibration in the step (1) includes calibration of a switching amplifying circuit, specifically, an amplifying circuit and a through path, and specifically includes the following processing procedures:
(1-1.1) maintaining the passive digitally controlled attenuator configured to attenuate to "0";
and (1-1.2) adjusting power values of the signal source power calibration amplifier in several states for different frequencies to enable the power received by the FPGA to be a fixed value.
Preferably, the passive circuit calibration in the step (1) includes calibration of a digitally controlled attenuator, and specifically includes the following steps:
(2-1.1) calibrating the frequency response of the numerical control attenuator of the first and the last frequency points of the whole frequency interval;
and (2-1.2) adjusting power values of the signal source power calibration numerical control attenuator under different attenuation values for the head and tail two frequency points, so that the power received by the FPGA is a fixed value.
Preferably, the step (2) specifically includes:
(2.1) dividing the power range to be calibrated into a plurality of gears according to the number of amplifiers, and calculating supplementary input power attenuation values among the gears through numerical control attenuator values;
(2.2) removing unreasonable calibration configurations beyond the power range or at the same input power to form a complete single channel simulator receiver calibration data table.
Preferably, the plurality of gears are "11" to "01" power gears, "01" to "00" power gears, and "00" to the upper limit power gear.
Preferably, the step (2) of calculating the supplementary input power attenuation value specifically includes the steps of:
the supplemental input power attenuation value is calculated according to the following equation:
Figure BDA0002835271100000021
Figure BDA0002835271100000022
Pn (i)(j) ＝Pn (i)(0) +Δn (i)(j) ；
wherein n is a gear value, f L For the initial frequency f H For termination frequency, (i) is a frequency value, i ε [ f ] L ，f H ](j) theoretical attenuation values for digitally controlled attenuators.
The system for realizing power calibration and data processing of the MIMO channel simulator radio frequency receiver is mainly characterized by comprising the following components: the digital-to-analog conversion circuit comprises a first switch amplifying circuit, a second switch amplifying circuit, a digital control attenuating circuit, a demodulation circuit, a local oscillation circuit, two ADC analog-to-digital conversion circuits and an FPGA circuit, wherein the first switch amplifying circuit, the second switch amplifying circuit, the digital control attenuating circuit and the demodulation circuit are sequentially connected, the output end of the local oscillation circuit is connected with the demodulation circuit, the input ends of the two ADC analog-to-digital conversion circuits are connected with the demodulation circuit, and the output ends of the two ADC analog-to-digital conversion circuits are connected with the FPGA circuit.
The method and the system for realizing the power calibration and the data processing of the radio frequency receiver of the MIMO channel simulator solve the algorithm problem of the power calibration of the receiver of the MIMO channel simulator in a large scale. By using the method, the calibration time of the receiver of the single-channel simulator is improved by 10-20 times, and the method is particularly suitable for calibrating the power of a transmitter of large-scale MIMO. The invention solves the contradiction between the calibration time and the power accuracy of the large-scale MIMO channel simulator receiver. By using the method, the total calibration time is reduced, and the power accuracy is ensured.
Drawings
Fig. 1 is a block diagram of a zero intermediate frequency architecture of a MIMO channel simulator receiver of the system for implementing power calibration and data processing of the MIMO channel simulator radio frequency receiver of the present invention.
Fig. 2 is a schematic diagram of a MIMO channel simulator receiver calibration instrument connection for implementing a system for power calibration and data processing of a MIMO channel simulator radio frequency receiver in accordance with the present invention.
Fig. 3 is a graph of a single channel simulator receiver fast calibration for implementing the method of MIMO channel simulator radio frequency receiver power calibration and data processing of the present invention.
Fig. 4 is a histogram of power accuracy verified using the calibration method of the present invention for a method of implementing MIMO channel simulator radio frequency receiver power calibration and data processing of the present invention.
Detailed Description
In order to more clearly describe the technical contents of the present invention, a further description will be made below in connection with specific embodiments.
The method for realizing power calibration and data processing of the MIMO channel simulator radio frequency receiver is mainly characterized by comprising the following steps of:
(1) Calibrating the frequency response of an amplifier and a straight-through channel in a radio frequency channel and the frequency response of a numerical control attenuator of an individual frequency point according to the linear characteristics of the radio frequency numerical control attenuator by active circuit calibration and passive circuit calibration;
(2) And performing data calculation according to the existing calibration data, and processing to obtain a complete MIMO channel simulator receiver calibration table.
Preferably, the active circuit calibration in the step (1) includes calibration of a switching amplifying circuit, specifically, an amplifying circuit and a through path, and specifically includes the following processing procedures:
(1-1.1) maintaining the passive digitally controlled attenuator configured to attenuate to "0";
and (1-1.2) adjusting power values of the signal source power calibration amplifier in several states for different frequencies to enable the power received by the FPGA to be a fixed value.
Preferably, the passive circuit calibration in the step (1) includes calibration of a digitally controlled attenuator, and specifically includes the following steps:
(2-1.1) calibrating the frequency response of the numerical control attenuator of the first and the last frequency points of the whole frequency interval;
and (2-1.2) adjusting power values of the signal source power calibration numerical control attenuator under different attenuation values for the head and tail two frequency points, so that the power received by the FPGA is a fixed value.
Preferably, the step (2) specifically includes:
(2.1) dividing the power range to be calibrated into a plurality of gears according to the number of amplifiers, and calculating supplementary input power attenuation values among the gears through numerical control attenuator values;
(2.2) removing unreasonable calibration configurations beyond the power range or at the same input power to form a complete single channel simulator receiver calibration data table.
Preferably, the plurality of gears are "11" to "01" power gears, "01" to "00" power gears, and "00" to the upper limit power gear.
Preferably, the step (2) of calculating the supplementary input power attenuation value specifically includes the steps of:
the supplemental input power attenuation value is calculated according to the following equation:
Figure BDA0002835271100000041
Figure BDA0002835271100000042
Pn (i)(j) ＝Pn (i)(0) +Δn (i)(j) ；
wherein n is a gear value, f L For the initial frequency f H For termination frequency, (i) is a frequency value, i ε [ f ] L ，f H ](j) theoretical attenuation values for digitally controlled attenuators.
The system for realizing power calibration and data processing of the MIMO channel simulator radio frequency receiver comprises: the digital-to-analog conversion circuit comprises a first switch amplifying circuit, a second switch amplifying circuit, a digital control attenuating circuit, a demodulation circuit, a local oscillation circuit, two ADC analog-to-digital conversion circuits and an FPGA circuit, wherein the first switch amplifying circuit, the second switch amplifying circuit, the digital control attenuating circuit and the demodulation circuit are sequentially connected, the output end of the local oscillation circuit is connected with the demodulation circuit, the input ends of the two ADC analog-to-digital conversion circuits are connected with the demodulation circuit, and the output ends of the two ADC analog-to-digital conversion circuits are connected with the FPGA circuit.
The invention relates to the technical field of communication measuring instrument calibration, in particular to the technical field of MIMO channel simulator receiver power calibration, and specifically relates to a method for realizing quick power calibration and power data processing of an MIMO channel simulator receiver. The invention comprises a multichannel channel simulator receiver circuit and a data calculation processing program based on the existing calibration data, and specifically comprises an analog-to-digital conversion circuit, a multistage amplifying circuit, a demodulation circuit, a frequency response calibration logic algorithm, upper computer control software and a data calculation processing program. By adopting the new method, the quick and accurate calibration of the MIMO channel simulator receiver can be realized based on a small amount of calibration data through data calculation processing. The method has the advantages of short time consumption, high accuracy and the like, and is particularly suitable for being used in the MIMO channel simulator receiver.
The invention needs to solve the problem of algorithm optimization of the power calibration of the large-scale MIMO channel simulator receiver. The traditional frequency and power traversal calibration method is adopted, the calibration time is too long, and the method is not suitable for the calibration of a large-scale MIMO channel simulator receiver and the mass production of the channel simulator.
The invention also needs to solve the contradiction between the calibration time and the power accuracy of the large-scale MIMO channel simulator receiver. By adopting the traditional traversal method, although certain accuracy can be ensured, the calibration time is too long; reducing the calibration steps and thus the calibration time necessarily causes a problem of reduced power accuracy.
The invention provides a method for realizing quick power calibration and power data processing of a MIMO channel simulator receiver. Devices in a radio frequency channel of the receiver are divided into two types, namely a passive device and an active device, and the linear characteristics of a radio frequency numerical control attenuator are fully utilized, and only the frequency response of an amplifier and a straight-through channel in the radio frequency channel and the frequency response of the numerical control attenuator of an individual frequency point are required to be calibrated, so that data calculation processing can be carried out based on the existing calibration data, and a complete MIMO channel simulator receiver calibration table is obtained. The power accuracy of the MIMO channel simulator receiver is ensured, and meanwhile, the calibration efficiency of the single-channel simulator receiver is greatly improved. The method is a brand new method for quick power calibration and power data processing of the MIMO channel simulator receiver.
The invention is mainly suitable for a zero intermediate frequency architecture MIMO channel simulator receiver, and an architecture schematic block diagram thereof is shown in figure 1, and specifically comprises a multistage amplifying circuit, a demodulation circuit, a local oscillation circuit, an ADC analog-to-digital conversion circuit and the like. The receiver demodulates the received radio frequency signal into an IQ signal with fixed power through power adjustment, and then the IQ signal is sampled into a digital signal by an ADC (analog-to-digital converter), and the digital signal is transmitted to a post-stage FPGA circuit for signal processing. A schematic diagram of the instrument connection during calibration of the MIMO channel simulator receiver is shown in fig. 2.
The calibration procedure for each channel of the MIMO channel simulator receiver is the same, and the calibration and calculation method of the present invention will be described below by taking a single receiver power calibration as an example. The calibration of the channel simulator receiver is divided into two steps, namely, quick power calibration, and data calculation processing based on the existing calibration data to obtain a complete MIMO channel simulator receiver calibration table.
The fast power calibration of step one is divided into two parts: active circuit calibration and passive circuit calibration.
Active circuit calibration mainly comprises a switching amplifying circuit, and specifically relates to calibration of the amplifying circuit and a through path. Because the frequency response difference value of the amplifier is not more linear and can not be traced in the two states of '0' and '1', the frequency response can not be simply added and subtracted, and the amplifiers AMP1 and AMP2 need to be independently tested and calibrated when the states are '00', '01' and '11'. The '10' state or the '01' state is configured according to actual needs, and the method is the same, so that the scheme is only described by taking '01' as an example. During active circuit calibration, the passive digitally controlled attenuator is kept configured to attenuate to '0'. And in the whole frequency interval, for different frequencies, adjusting the power values of the signal source power calibration amplifier in several states so that the power received by the FPGA is a fixed value. The present description illustrates only two switching amplifier circuits, and the method is equally applicable to a greater number of active switching amplifier circuit power calibrations.
Passive circuit calibration mainly includes digitally controlled attenuator calibration. The linearity of the attenuator is relatively high and is also less affected by frequency. The calibration of the passive circuit fully utilizes the linear characteristic of the passive circuit, and only the frequency response of the numerical control attenuator of the first and the last frequency points of the whole frequency interval is required to be calibrated, and the state of the configuration amplifier is '00'. And for the first and the last frequency points, adjusting the power value of the signal source under different attenuation values of the digital control attenuator, so that the power received by the FPGA is a fixed value. The default digitally controlled attenuator step is 0.25dB, 31.75dB total program.
From the above active circuit calibration and passive circuit calibration, a calibration curve as shown in fig. 3 can be obtained.
And step two, performing data calculation processing based on the existing calibration data to obtain a complete MIMO channel simulator receiver calibration table, wherein the calculation scheme is introduced as follows:
the power range to be calibrated is divided into several gears according to the number of amplifiers, and the present description includes three gears, namely, 11 to 01 power gear (the down power gear is in the interval), 01 to 00 power gear, and 00 to the upper limit power gear. The power value between each gear is calculated by numerical control attenuator value.
The power calculation of '00' to the upper limit power gear is calculated firstly, the existing calibration value is the most complete, and the calculation scheme is easier to understand.
(1) '00' to upper limit power gear
In this configuration, it is necessary to supplement the input power calibration value up to the upper power limit of curve 1 in fig. 3. The process is a numerical control attenuator, the linear characteristic of the numerical control attenuator is good, and addition and subtraction calculation can be used.
Let the start frequency be fL and the end frequency be fH, curve 4 in FIG. 3
Figure BDA0002835271100000061
And curve 5->
Figure BDA0002835271100000062
Where (j) represents the theoretical attenuation value of the digitally controlled attenuator, where j=k, k being the actual attenuation value. In actual test, although j is the same, the attenuation configuration of the numerical control attenuator is the same, and a small difference exists between j and the actual attenuation value k due to the frequency response difference of different frequency points, namely j is approximately equal to k.
The differences between fL and fH in curve 1 and curves 4 and 5 were calculated. For a certain determined j
Figure BDA0002835271100000063
According to
Figure BDA0002835271100000064
And->
Figure BDA0002835271100000065
j=0.25/0.5/1/ L ～f H A difference value Δ1 between k and k=0 (i)(j) Wherein (i) represents a frequency value, i ε f L ，f H ]。
Figure BDA0002835271100000066
The supplementary input power attenuation value for this interval is:
P1 (i)(j) ＝P1 (i)(0) +Δ1 (i)(j) ；
(2) '01' to '00' power stage
In this configuration, it is necessary to supplement the input power calibration value of approximately 31.75dB up curve 2 in fig. 3. The process is also calculated by a numerical control attenuator, has good linear characteristics and can be calculated by addition and subtraction. The calculation method is the same as '00' to the upper limit power gear.
The differences between fL and fH in curve 2 and curves 4 and 5 were calculated. For a certain determined j
Figure BDA0002835271100000067
According to
Figure BDA0002835271100000068
And->
Figure BDA0002835271100000069
Can calculate f L ～f H Δ2 including the difference in the frequency response of the amplifier and the value of the difference in j-k of the digitally controlled attenuator (i)(j) 。/>
Figure BDA0002835271100000071
The supplementary input power attenuation value for this interval is:
P2 (i)(j) ＝P2 (i)(0) +Δ2 (i)(j) ；
(3) '11' to '01' power stage
The calculation process is the same as the `01` to `00` power stage.
And after the frequency points and the power points are tested and calculated, removing useless unreasonable calibration configuration, and forming a complete calibration data table of the receiver of the single-channel simulator.
Using the method of the present invention, a frequency step of fstep is set, and for a single channel receiver, the calibration point number is
Figure BDA0002835271100000072
Wherein the method comprises the steps of
Figure BDA0002835271100000073
The number of calibration points is 1/2/3 of the curve in FIG. 2, and the number of calibration points is three; (128 x 2) calibration points for the digitally controlled attenuator at the start frequency fL and the end frequency fH, respectively.
Using conventional traversal methods, let frequency step be fstep, power range [ PL, PH ], step 1dB (common empirical value), for single channel receiver, calibration point number be
Figure BDA0002835271100000074
Power interval (P of general channel simulator H -P L ) At least 50dB, then
Figure BDA0002835271100000075
Comparison n 1 And n 2 Can see n 2 About n 1 17 times of (3). And (P) H -P L ) Calculated as 50dB only, the receiving power range of the practical MIMO channel simulator is necessarily more than 50dB, so n 2 /n 1 And will be larger.
Therefore, the calibration data size is obviously reduced, the accuracy of the calibration power is ensured by improving the calibration steps, the total calibration time of the MIMO channel simulator receiver is effectively improved, and the accuracy of the receiver power is displayed through actual measurement. It can be seen that the method of the present invention is particularly suitable for power calibration of a massive MIMO channel simulator receiver.
The circuit scheme block diagram of the method is shown in fig. 1. The device specifically comprises a two-stage switch amplifying circuit, a one-stage numerical control attenuation circuit, a one-stage demodulation circuit, a one-stage local oscillation circuit, a one-stage ADC circuit and a one-stage FPGA circuit. The receiver demodulates the received radio frequency signal into an IQ signal with fixed power through power adjustment, and then the IQ signal is sampled into a digital signal by an ADC (analog-to-digital converter), and the digital signal is transmitted to a post-stage FPGA circuit for signal processing.
The on-channel amplifier and digital attenuator configuration and input/output power relationship formula is as follows:
output power = input power + (AMP 1+ AMP 2) x 20-DAT-channel fixed frequency response;
where 'AMP1/2' represents a configuration value, such as '01', AMP1+ AMP2 = 1;20 represents the amplifier gain; DAT represents the numerical control attenuator attenuation value; the channel fixed frequency response is an inherent value influenced by hardware, and is a fixed value for a determined frequency point;
for a certain frequency point, the relation between the configuration of the amplifier and the digital control attenuator and the input/output power is as follows:
Figure BDA0002835271100000081
/>
the MIMO channel simulator receiver supports 256 channels, the frequency range is 0.4-6 GHz, the power range is-40 dBm to +20dBm, the dynamic state of the numerical control attenuator is 0-31.75 dB and steps by 0.25dB, and the gain of the two-stage amplifier is about 20dB.
First is active circuit calibration and passive circuit calibration.
Active circuit calibration mainly comprises a switching amplifying circuit, and specifically relates to calibration of the amplifying circuit and a through path. The holding passive digitally controlled attenuator is configured to attenuate to '0'. In the frequency interval of 0.4-6 GHz, 10MHz is used as a step, and for different frequencies, the power value of the signal source power is adjusted, and the power value of the amplifier is calibrated under three states of 'AMP1 AMP2' = '11'/'01'/'00', so that the power received by the FPGA is a fixed value C (C is a specific power value in the design of a receiver scheme).
The passive circuit calibration mainly comprises the calibration of a numerical control attenuator, and only the frequency points of 0.4GHz and 6GHz are required to be calibrated. The holding amplifier is configured as 'AMP1 AMP2' = '00', the digitally controlled attenuator attenuation value is adjusted from 0dB to 31.75dB in steps of 0.25dB, and the signal source power is adjusted so that the output power is a fixed value C.
From the above active circuit calibration and passive circuit calibration, a calibration curve as shown in fig. 3 can be obtained.
Then, based on the existing calibration data, the data calculation process is performed to obtain a complete calibration table of the receiver of the MIMO channel simulator, and the calculation scheme is introduced as follows:
firstly, calculating the power of the power range from '00' to the upper limit of 20dBm, wherein the existing calibration value is the most complete, and the calculation scheme is easier to understand.
(1) '00' to upper 20dBm power stage
In this configuration, it is necessary to supplement the input power calibration value up to the upper power limit of curve 1 in fig. 3. The process is a numerical control attenuator, the linear characteristic of the numerical control attenuator is good, and addition and subtraction calculation can be used.
According to the foregoing
Figure BDA0002835271100000082
According to (400, delta1 (400)(j) ) Sum (6000, delta1) (6000)(j) ) J=0.25/0.5/1/. Once..once..once per 31.75, the difference Δ1 between k and k=0 can be calculated at 400 to 600 mhz (i)(j) Wherein (i) represents a frequency value, i ε [400, 6000 ]]。
Figure BDA0002835271100000083
The supplementary input power value for this interval is:
P1 (i)(j) ＝P1 (i)(0) +Δ1 (i)(j)
(2) '01' to '00' power stage
In this configuration, it is necessary to supplement the input power calibration value of approximately 31.75dB up curve 2 in fig. 3. The process is also calculated by a numerical control attenuator, has good linear characteristics and can be calculated by addition and subtraction. The calculation method is the same as '00' to the upper limit of 20dBm power gear.
According to the foregoing
Figure BDA0002835271100000091
According to (400, delta 2 (400)(j) ) Sum (6000, delta 2) (6000)(j) ) Delta 2 MHz including the frequency response difference of the amplifier and the j-k difference value of the numerical control attenuator can be calculated from 400 to 6000MHz (i)(j) 。
Figure BDA0002835271100000092
/>
The supplementary input power attenuation value for this interval is:
P2 (i)(j) ＝P2 (i)(0) +Δ2 (i)(j)
(3) '11' (off-line-40 dBm) to '01' power stage
The calculation process is the same as the `01` to `00` power stage.
And after the frequency points and the power points are tested and calculated, removing calibration configuration which exceeds the power range or is unreasonable in configuration under the same input power, and forming a complete calibration data table of the receiver of the single-channel simulator.
The method of the invention is used, and for a single-channel receiver, the calibration point number is
Figure BDA0002835271100000093
Using conventional traversal methods, for a single channel receiver, the calibration points are
Figure BDA0002835271100000094
It is thus evident that the amount of calibration data is greatly reduced using the method of the invention.
Assuming that the calibration time of each point is 1s,256 channels of MIMO channel simulator receiver power calibration, the comparison with the conventional traversal method is as follows: (calibrated to last 24 hours)
Figure BDA0002835271100000095
By using the traditional calibration method, the calibration time of 3.5 months is theoretically needed without considering adverse factors in the actual process, and the calibration period can not meet the production requirement of the MIMO channel simulator. By using the method of the invention, the power calibration of the receiver of the MIMO channel simulator with 256 channels can be completed only in one week.
After the calibration by the method of the invention is carried out, the calculated calibration data is substituted for the power accuracy verification of the MIMO channel simulator receiver, the power accuracy measurement result histogram is shown in figure 4, the accuracy is within +/-0.5 dB and is about 97%, and the power accuracy by the method of the invention is ensured.
From the above embodiment, the calibration method of the present invention is used for calibrating the power of the receiver of the MIMO channel simulator, which shortens the total calibration time and ensures the power accuracy, and is especially suitable for calibrating the power of the receiver of the 5G large-scale MIMO channel simulator.
The invention also discloses a realization mode of fine power calibration in program control stepping, namely within 20dB. The digital-to-analog converter DAC is used in the transmitter corresponding to the receiver of the invention, which belongs to a digital device, and the digital-controlled attenuator is used in the receiver of the invention, which belongs to a radio frequency analog device. The DAC multiplies the baseband data by a certain coefficient to realize attenuation, but the DAC reduces the signal-to-noise ratio and has a certain influence on the quality of communication signals, so that the DAC is only suitable for scenes with low signal quality requirements, or the DAC has high performance, namely the DAC reduces 20dB, and the signal-to-noise ratio of the signals is still higher; the numerical control attenuator has no influence on the signal quality basically, and although the numerical control attenuator cannot realize attenuation within 0.25dB step, the attenuation range can be large, and the influence on the signal quality is smaller.
Furthermore, the digital-to-analog converter DAC can only be used in a transmitter, but cannot be used in the receiver of the present invention. Corresponding to the DAC is an analog-to-digital converter ADC used in the receiver. Whereas ADCs are more unusable for power regulation and belong to the final stage, if only ADCs are used to regulate the attenuation (ADCs can also realize a fine-step attenuation), then the devices in the previous channels, such as demodulators or prior art mixers, must be nonlinear or even saturated, resulting in a signal that is not demodulated, which is not desirable.
The method and the system for realizing the power calibration and the data processing of the radio frequency receiver of the MIMO channel simulator solve the algorithm problem of the power calibration of the receiver of the MIMO channel simulator in a large scale. By using the method, the calibration time of the receiver of the single-channel simulator is improved by 10-20 times, and the method is particularly suitable for calibrating the power of a transmitter of large-scale MIMO. The invention solves the contradiction between the calibration time and the power accuracy of the large-scale MIMO channel simulator receiver. By using the method, the total calibration time is reduced, and the power accuracy is ensured.
In this specification, the invention has been described with reference to specific embodiments thereof. It will be apparent, however, that various modifications and changes may be made without departing from the spirit and scope of the invention. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.

Claims (2)

1. A method for implementing power calibration and data processing of a radio frequency receiver of a MIMO channel simulator, said method comprising the steps of:
(1) Calibrating the frequency response of an amplifier and a straight-through channel in a radio frequency channel and the frequency response of a numerical control attenuator of an individual frequency point according to the linear characteristics of the radio frequency numerical control attenuator by active circuit calibration and passive circuit calibration;
(2) Performing data calculation according to the existing calibration data, and processing to obtain a complete MIMO channel simulator receiver calibration table;
the active circuit calibration in the step (1) comprises a switching amplifying circuit, specifically an amplifying circuit and a through path calibration, and specifically comprises the following processing procedures:
(1-1.1) maintaining the passive digitally controlled attenuator configured to attenuate to "0";
(1-1.2) for different frequencies, adjusting the power values of the signal source power calibration amplifier in several states to enable the power received by the FPGA to be a fixed value;
the passive circuit calibration in the step (1) comprises the calibration of a numerical control attenuator, and specifically comprises the following steps:
(2-1.1) calibrating the frequency response of the numerical control attenuator of the first and the last frequency points of the whole frequency interval;
(2-1.2) adjusting power values of the signal source power calibration numerical control attenuator under different attenuation values for the head and tail two frequency points to enable the power received by the FPGA to be a fixed value;
the step (2) is specifically as follows:
(2.1) dividing the power range to be calibrated into a plurality of gears according to the number of amplifiers, and calculating supplementary input power attenuation values among the gears through numerical control attenuator values;
(2.2) removing unreasonable calibration configuration beyond the power range or under the same input power to form a complete single-channel simulator receiver calibration data table;
the gears are 11 to 01 power gears, 01 to 00 power gears and 00 to the upper limit power gear;
the step (2) of calculating the supplementary input power attenuation value specifically comprises the following steps:
the supplemental input power attenuation value is calculated according to the following equation:
Figure FDA0004153407010000011
Figure FDA0004153407010000012
Pn (i)(j) ＝Pn (i)(0) +Δn (i)(j) ；
wherein n is a gear value, f L For the initial frequency f H For termination frequency, (i) is a frequency value, i ε [ f ] L ，f H ]And (j) the theoretical attenuation value of the numerical control attenuator, wherein P is the power value obtained by actual test when calibrating, P4 is the power value actually measured by the variation attenuation amount of the numerical control attenuator at the initial frequency, and P5 is the power value actually measured by the variation attenuation amount of the numerical control attenuator at the final frequency.
2. A system for power calibration and data processing of a MIMO channel simulator radio frequency receiver for implementing the method of claim 1, said system comprising: the digital-to-analog conversion circuit comprises a first switch amplifying circuit, a second switch amplifying circuit, a digital control attenuating circuit, a demodulation circuit, a local oscillation circuit, two ADC analog-to-digital conversion circuits and an FPGA circuit, wherein the first switch amplifying circuit, the second switch amplifying circuit, the digital control attenuating circuit and the demodulation circuit are sequentially connected, the output end of the local oscillation circuit is connected with the demodulation circuit, the input ends of the two ADC analog-to-digital conversion circuits are connected with the demodulation circuit, and the output ends of the two ADC analog-to-digital conversion circuits are connected with the FPGA circuit.
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