CN112599555A - Piezoelectric thin film device and preparation method thereof - Google Patents
Piezoelectric thin film device and preparation method thereof Download PDFInfo
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- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N39/00—Integrated devices, or assemblies of multiple devices, comprising at least one piezoelectric, electrostrictive or magnetostrictive element covered by groups H10N30/00 – H10N35/00
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42324—Gate electrodes for transistors with a floating gate
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Abstract
The invention discloses a piezoelectric thin film device and a preparation method thereof, wherein the piezoelectric thin film device comprises: the driving substrate comprises a substrate layer and a plurality of thin film transistors arranged on the substrate layer; the piezoelectric thin film layer is arranged on one side, far away from the substrate layer, of the thin film transistors; the floating gate layer is arranged between the thin film transistors and the piezoelectric thin film layer, and generates charge change when the piezoelectric thin film layer is stressed, and the charge change causes the channel current of the thin film transistors to change. The problem that the sensitivity of the existing piezoelectric element to induced stress is low and the application range of the existing piezoelectric element is limited can be solved.
Description
Technical Field
The application relates to the technical field of piezoelectric sensing, in particular to a piezoelectric thin film device and a preparation method thereof.
Background
A piezoelectric sensor is a sensor manufactured by using a dielectric substance that generates a piezoelectric effect when an external force is applied to the dielectric substance. In recent years, electronics related to human body sensing, such as pulse sensors or electronic olfactory sensors, have come to be of increasing interest. In the existing piezoelectric sensing technology, piezoelectric elements are usually manufactured by using equal-pressure electropolymers such as polyvinylidene fluoride (PVDF) as a piezoelectric film layer, and the equal-pressure electropolymers such as PVDF as the piezoelectric film layer have the advantages of light weight, good mechanical property, high elasticity, approximate acoustic impedance to biological tissues and the like.
At present, the structure of the existing piezoelectric element is to directly lead out a metal electrode on a piezoelectric film layer. When the piezoelectric film layer is stressed by external force, the surface bound charge amount changes, and because the PVDF piezoelectric film has high internal impedance and weak output signal, the piezoelectric measuring circuit is usually connected with a preamplifier, and the preamplifier can amplify the weak signal output by the piezoelectric film layer through the metal electrode. However, the sensing method of amplifying the weak signal output by the metal electrode by using the preamplifier causes the sensitivity of the piezoelectric element to induce stress to be low, thereby greatly limiting the application range of the existing piezoelectric element.
Disclosure of Invention
The invention provides a piezoelectric thin film device and a preparation method thereof, which can solve the problems that the sensitivity of the existing piezoelectric element to induced stress is low and the application range of the existing piezoelectric element is limited.
A first aspect of the present application provides a piezoelectric thin film device comprising:
a drive substrate including a substrate layer and a plurality of thin film transistors disposed on the substrate layer;
the piezoelectric thin film layer is arranged on one side, far away from the substrate layer, of the thin film transistors;
the floating gate layer is arranged between the piezoelectric thin film layer and the thin film transistors, and generates charge change when the piezoelectric thin film layer is stressed, and the charge change causes the channel current of the thin film transistors to change.
According to an embodiment, the floating gate layer comprises a floating gate metal layer.
According to one embodiment, the floating gate metal layer includes a plurality of floating gate electrodes disposed opposite to the channels of the thin film transistors.
According to one embodiment, the floating gate metal layer is of a multi-layer metal structure.
According to an embodiment, the thin film transistor comprises a unipolar transistor or a bipolar transistor.
According to one embodiment, the plurality of thin film transistors are arranged in an array.
According to an embodiment, the driving substrate further comprises a first metal layer, a second metal layer and a transparent electrode layer sequentially disposed on the substrate layer; a first isolation layer is arranged between the first metal layer and the second metal layer, and a second isolation layer is arranged between the second metal layer and the transparent electrode layer;
the first metal layer comprises a plurality of scanning lines extending along a first direction, the second metal layer comprises a plurality of data lines extending along a second direction, the plurality of scanning lines and the plurality of data lines are intersected to define a plurality of induction areas, and the thin film transistor is arranged in the induction areas; the thin film transistor comprises a bottom gate electrode, a semiconductor layer, a source electrode and a drain electrode, wherein the bottom gate electrode is positioned on the first metal layer, the source electrode and the drain electrode are positioned on the second metal layer, the semiconductor layer is arranged between the first isolation layer and the second metal layer, and the source electrode and the drain electrode are both contacted with the semiconductor layer; the transparent electrode layer comprises a transparent electrode, a through hole is formed in the second isolation layer, and the transparent electrode is in electric contact with the source electrode or the drain electrode through the through hole.
According to one embodiment, the semiconductor layer employs a carbon nanotube thin film layer.
According to one embodiment, the substrate layer is made of a flexible material.
A second aspect of the present application provides a method for manufacturing a piezoelectric thin film device, including:
arranging a plurality of thin film transistors on the substrate layer;
arranging a floating gate layer on one side of the thin film transistors far away from the substrate layer;
and arranging a piezoelectric thin film layer on one side of the floating gate layer, which is far away from the substrate layer, wherein the floating gate layer generates charge change when the piezoelectric thin film layer is stressed, and the charge change causes the channel current of the thin film transistor to change.
According to the piezoelectric thin film device and the preparation method thereof, the floating gate layer is arranged to be in contact with the piezoelectric thin film layer, when the piezoelectric thin film layer is subjected to stress deformation due to external stress to cause surface bound charge change, the floating gate layer can generate corresponding charge accumulation according to the surface bound charge change of the piezoelectric thin film layer, the process is that the floating gate layer converts the weak surface bound charge change on the piezoelectric thin film layer into self charge accumulation, and the charge accumulation on the floating gate layer can be regarded as amplification of the surface bound charge on the piezoelectric thin film layer; the accumulation of charge on the floating gate layer causes a change in the channel current of the thin film transistor, and the stress applied to the piezoelectric thin film device can be obtained by measuring the change in current flowing through the thin film transistor, which can be regarded as further amplification of the charge on the floating gate layer. The piezoelectric thin film layer is matched with the floating gate layer and the thin film transistor, a preamplifier in the prior art can be replaced, and compared with the existing preamplifier, the floating gate layer senses the surface bound charges of the piezoelectric thin film layer and generates a process of self charge accumulation, the floating gate layer is sensitive, the accumulated charges of the floating gate layer are converted into current values which are easy to monitor by the aid of the stacked thin film transistor, sensing sensitivity of the piezoelectric thin film device is further improved, and the piezoelectric thin film device has a wider application range.
Drawings
Fig. 1 is a schematic structural diagram of a piezoelectric thin film device provided in an embodiment of the present application;
fig. 2 is a schematic diagram illustrating deformation of a piezoelectric thin-film device according to an embodiment of the present disclosure when subjected to a tensile stress;
fig. 3 is a schematic diagram illustrating charge accumulation on a floating gate layer when a piezoelectric thin film device provided by an embodiment of the present application is subjected to a tensile stress;
fig. 4 is a schematic diagram illustrating deformation of a piezoelectric thin-film device according to an embodiment of the present disclosure when subjected to a compressive stress;
fig. 5 is a schematic diagram illustrating charge accumulation on a floating gate layer when a piezoelectric thin film device provided by an embodiment of the present application is subjected to a compressive stress;
fig. 6 is a schematic structural view of another piezoelectric thin film device provided in an embodiment of the present application;
fig. 7 is a schematic structural diagram of a driving substrate according to an embodiment of the present disclosure;
fig. 8 is a partial schematic structural view of still another piezoelectric thin-film device provided in an embodiment of the present application;
FIG. 9 is a schematic diagram illustrating a voltage-current characteristic curve and a current change under stress of a CNT-TFT according to an embodiment of the present disclosure;
fig. 10 is a schematic flowchart of a method for manufacturing a piezoelectric thin film device according to an embodiment of the present disclosure.
Detailed Description
In order to better understand the technical solutions provided by the embodiments of the present specification, the technical solutions of the embodiments of the present specification are described in detail below with reference to the drawings and specific embodiments, and it should be understood that the specific features in the embodiments and examples of the present specification are detailed descriptions of the technical solutions of the embodiments of the present specification, and are not limitations on the technical solutions of the embodiments of the present specification, and the technical features in the embodiments and examples of the present specification may be combined with each other without conflict.
In this document, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element. The term "two or more" includes the case of two or more.
The structure of the existing piezoelectric element is that a metal electrode is directly led out from a piezoelectric film layer. When the piezoelectric film layer is subjected to stress change due to external force, the surface data charge quantity changes, and because the PVDF piezoelectric film has high internal impedance and weak output signals, the piezoelectric measurement circuit is generally required to be connected with a preamplifier, and the preamplifier can amplify weak signals output by the piezoelectric film layer through the metal electrodes. However, the sensing method of amplifying the weak signal output by the metal electrode by using the preamplifier causes the sensitivity of the piezoelectric element to induce stress to be low, thereby greatly limiting the application range of the existing piezoelectric element.
In view of this, fig. 1 is a schematic structural diagram of a piezoelectric thin film device according to an embodiment of the present application. As shown in fig. 1, the present embodiment provides a piezoelectric thin film device including a driving substrate 1, a piezoelectric thin film layer 2, and a floating gate layer 3. The drive substrate 1 includes a substrate layer 11 and a plurality of thin film transistors 12 disposed on the substrate layer 11. The piezoelectric thin film layer 2 is provided on a side of the plurality of thin film transistors 12 away from the substrate layer 11. Based on the advantages of light weight, good mechanical property, high elasticity, approximate acoustic impedance to biological tissues and the like of PVDF materials, the piezoelectric film layer 2 can adopt PVDF. The floating gate layer 3 is disposed between the piezoelectric thin film layer 2 and the plurality of thin film transistors 12, and the floating gate layer 3 generates charge accumulation when the piezoelectric thin film layer 2 is subjected to stress, and the charge accumulation causes a channel current of the thin film transistors 12 to change. The material of the floating gate layer 3 may not be particularly limited as long as induced charges can be achieved.
Fig. 2 is a schematic diagram illustrating deformation of a piezoelectric thin-film device according to an embodiment of the present disclosure when subjected to a tensile stress; fig. 3 is a schematic diagram illustrating charge accumulation on a floating gate layer when a piezoelectric thin film device according to an embodiment of the present disclosure is subjected to a tensile stress. With reference to fig. 2 and fig. 3, in the piezoelectric thin film device provided in this embodiment, when the piezoelectric thin film layer 2 is under tensile stress, for example, the piezoelectric thin film layer 2 is pressed, a local area of the piezoelectric thin film device that is pressed may generate stress deformation, where the specific deformation is a concave bending on a side of the piezoelectric thin film layer 2 that is laterally far away from the substrate layer 11, and the driving substrate 1, the floating gate layer 3, and the piezoelectric thin film layer 2 are both bent synchronously. The piezoelectric thin film layer 2 is bent along with the bending of the whole piezoelectric thin film device, at this time, the deformation of the piezoelectric thin film layer 2 can cause the change of the surface bound charges, the change of the surface bound charges on the piezoelectric thin film layer 2 can cause the charge accumulation on the floating gate layer 3 which is in contact with the piezoelectric thin film layer, and the charge accumulation on the floating gate layer 3 further causes the change of the channel current on the thin film transistor 12. Therefore, the tensile stress to which the piezoelectric thin film device is subjected can be measured by testing the change of the channel current. Specifically, as shown in fig. 2 and 3, positive charges are accumulated on the side of the floating gate layer 3 close to the piezoelectric thin film layer 2 when the piezoelectric thin film layer 2 is subjected to tensile stress deformation. The positive charge accumulated on the floating gate layer 3 causes a change in capacitance and voltage difference between the thin film transistor 12 and the floating gate layer 3, thereby changing the current flowing through the channel of the thin film transistor 12. The tensile stress applied to the piezoelectric thin film device can be obtained by monitoring the change in current flowing through the thin film transistor 12.
Fig. 4 is a schematic diagram illustrating deformation of a piezoelectric thin-film device according to an embodiment of the present disclosure when subjected to a compressive stress; fig. 5 is a schematic diagram illustrating charge accumulation on a floating gate layer when a piezoelectric thin film device according to an embodiment of the present disclosure is subjected to a compressive stress. With reference to fig. 4 and 5, in the piezoelectric thin film device provided in this embodiment, when the piezoelectric thin film layer 2 is under compressive stress, for example, the piezoelectric thin film layer 2 is under a pressing force, a local area of the piezoelectric thin film device under the pressing force may generate stress deformation, the specific deformation is that one side of the piezoelectric thin film layer 2 laterally far away from the substrate layer 11 is convexly curved, the driving substrate 1 and the floating gate layer 3 are both synchronously curved with the piezoelectric thin film layer 2, at this time, the deformation of the piezoelectric thin film layer 2 may cause a change in surface bound charges, the change in surface bound charges on the piezoelectric thin film layer 2 may cause a charge accumulation on the floating gate layer 3 in contact therewith, and the charge accumulation on the floating gate layer 3 further causes a change in channel current on the thin film transistor 12. Therefore, the compressive stress to which the piezoelectric thin film device is subjected can be measured by testing the change of the channel current. Specifically, as shown in fig. 4 and 5, when the piezoelectric thin film layer 2 is deformed by compressive stress, negative charges are accumulated on the side of the floating gate layer 3 close to the piezoelectric thin film layer 2. The accumulated negative charge on the floating gate layer 3 causes a change in capacitance and voltage difference between the thin film transistor 12 and the floating gate layer 3, thereby changing the current flowing through the channel of the thin film transistor 12. The compressive stress applied to the piezoelectric thin film device can be obtained by monitoring the change in current flowing through the thin film transistor 12.
According to the piezoelectric thin film device provided by the embodiment, by arranging the floating gate layer 3 in contact with the piezoelectric thin film layer 2, when the piezoelectric thin film layer 2 is subjected to stress deformation to cause the change of the surface bound charges, the floating gate layer 3 can generate corresponding charge accumulation according to the change of the surface bound charges of the piezoelectric thin film layer 2, the floating gate layer 3 converts the weak surface bound charge change on the piezoelectric thin film layer 2 into the charge accumulation of the floating gate layer 3 in the process, and the charge accumulation on the floating gate layer 3 can be regarded as the amplification of the changed surface bound charges on the piezoelectric thin film layer 2; the charge accumulation of the floating gate layer 3 causes the channel current of the thin film transistor 12 to change, the stress change on the piezoelectric thin film device can be obtained by measuring the current change flowing through the thin film transistor 12, and the thin film transistor 12 can be regarded as further amplifying the charge on the floating gate layer 3. The piezoelectric thin film layer 2 is matched with the floating gate layer 3 and the thin film transistor 12, a preamplifier in the prior art can be replaced, compared with the existing preamplifier, the process that the floating gate layer 3 senses the surface bound charges of the piezoelectric thin film layer 2 and generates self charge accumulation is more sensitive, the thin film transistor 12 converts the accumulated charges of the floating gate layer 3 into a current value which is easy to monitor, the sensing sensitivity of the piezoelectric thin film device is further improved, and the piezoelectric thin film device has a larger application range.
In a possible implementation, the floating gate layer 3 mentioned in the foregoing embodiment may include a floating gate metal layer. Since metals generally have a good ability to conduct electric charges, metals, which are conventional conductive materials, may be used as materials for the floating gate layer. For example, the material of the floating gate metal layer may be a metal material of a conventional semiconductor electrode such as Mo, Cu, Au, or Ti, and the application is not limited in particular.
Illustratively, the floating gate metal layer mentioned in the foregoing embodiments may adopt a single-layer metal structure, the preparation process is simple, and the effect of conducting charge variation can be achieved. Illustratively, the floating gate metal layer may also be a multi-layer metal structure, and may be, for example, Ti-Al (titanium-aluminum) or Ti-Al-Ti (titanium-aluminum-titanium). A Ti-Al or Ti-Al-Ti composite electrode structure is an electrode layer structure which is applied more in the field of semiconductor integrated circuits. Although the multilayer metal stacked structure can increase the preparation process flow, the layered composition of Al can obviously reduce the resistance of the electrode on the basis of maintaining the performance of pure Ti.
Fig. 6 is a schematic structural view of a piezoelectric thin-film device according to another embodiment of the present application. As shown in fig. 6, the floating gate metal layer mentioned in the foregoing embodiment may include a plurality of floating gate electrodes 31, and the floating gate electrodes 31 are disposed opposite to the channels of the thin film transistors 12. The floating gate metal layer can obtain a plurality of floating gate electrodes 31 through an etching process, the positions of the floating gate electrodes 31 correspond to the channels of the thin film transistors 12, so that the change of the channel current of the thin film transistors 12 can be caused to the maximum extent when charges are accumulated on the floating gate electrodes 31, and the change of the surface bound charges on the piezoelectric thin film layer 2 can be amplified better.
Illustratively, in some embodiments of the present invention, the thin film transistor 12 mentioned in the foregoing embodiments may comprise a unipolar transistor in practical applications. A unipolar transistor, also called a field Effect transistor (fet) for short, is a voltage-controlled device, and controls the magnitude of output current by the electric field Effect generated by input voltage, and only one kind of carriers (majority carriers) participate in conduction during operation, and has unidirectional conductivity. The unipolar transistor has the characteristics of low noise, good thermal stability, simple preparation process and easiness in integration, and the characteristics of the unipolar transistor are relatively convenient to control, and the unipolar transistor has small power and small volume, so that the floating gate layer can be matched with the unipolar transistor to better amplify the change of surface bound charges generated by stress on the piezoelectric thin film layer.
Illustratively, in some embodiments of the present invention, the thin film transistor 12 mentioned in the foregoing embodiments may comprise a bipolar transistor in practical applications. The bipolar transistor is also called a transistor, is a current control type device, controls output current by input current, has a current amplification effect, participates in a conduction process by two current carriers of electrons and holes during working, and has bidirectional conductivity. The bipolar transistor is a contactless switch for amplifying weak signals based on the characteristics, and has the advantages of firm structure, long service life, small volume, low power consumption and the like. Because bipolar transistor's two-way conductivity (positive voltage and negative voltage all can switch on), no matter the electric charge that the floating gate layer is accumulated is positive or negative, the homoenergetic makes bipolar transistor be switched on and take place the current change, consequently when floating gate layer collocation bipolar transistor received the stress and produced surface constraint charge change to the piezoelectric film layer and enlargies, bipolar transistor's current change can reflect that the piezoelectric film layer received is compressive stress or tensile stress, the improvement piezoelectric film device's that can bigger degree sensitivity, and then improve the induction precision, enlarge application range.
Illustratively, in some embodiments of the present invention, the substrate layer 11 may be made of a flexible material, and the flexible piezoelectric thin film device is capable of inducing compressive stress and tensile stress corresponding to bidirectional bending of the flexible substrate layer, so that the piezoelectric thin film device using the flexible material as the substrate layer can be applied to a wider field such as electronic skin, cardiac patch, or pulse detection patch.
Fig. 7 is a schematic structural diagram of a driving substrate according to an embodiment of the present disclosure; fig. 8 is a partial schematic structural view of another piezoelectric thin-film device provided in an embodiment of the present application. It should be noted that the structure shown in fig. 8 is directed to a cross-sectional structure of a single thin film transistor and a single floating gate electrode. As shown in fig. 7, the plurality of thin film transistors 12 may be arranged in an array. As shown in fig. 8, the driving substrate 1 may further include a first metal layer 13, a second metal layer 15, and a transparent electrode layer 17 sequentially disposed on the substrate layer 11; a first isolation layer 14 is disposed between the first metal layer 13 and the second metal layer 15, and a second isolation layer 16 is disposed between the second metal layer 15 and the transparent electrode layer 17. The material of the first isolation layer 14 may adopt a single-layer structure of silicon oxide or silicon nitride, or a structure of overlapping or alternately overlapping films of silicon oxide and silicon nitride, for example, a film structure of silicon oxide-silicon nitride-silicon oxide, which is not limited in this application. The second isolation layer 16 may be made of aluminum oxide or hafnium oxide, and atomic layer deposition of aluminum oxide or hafnium oxide has less fixed charges and less influence on channel carriers.
Referring to fig. 7 and 8, the first metal layer 13 includes a plurality of scan lines 131 extending along a first direction X, the second metal layer 15 includes a plurality of data lines 151 extending along a second direction Y, the plurality of scan lines 131 and the plurality of data lines 151 intersect to define a plurality of sensing regions SS, and the tft 12 is disposed in the sensing regions SS. The thin film transistor 12 includes a bottom gate electrode 121, a semiconductor layer 122, a source electrode 123, and a drain electrode 124. The bottom gate electrode 121 is located in the first metal layer 13, the source electrode 123 and the drain electrode 124 are located in the second metal layer 15, the semiconductor layer 122 is located between the first isolation layer 14 and the second metal layer 15, and both the source electrode 123 and the drain electrode 124 are in contact with the semiconductor layer 122. The second isolation layer 16 is provided with a via hole 161, and the transparent electrode layer 17 is in contact with the source electrode 123 or the drain electrode 124 through the via hole 161. As shown in fig. 7 and 8, the transparent electrode 171 electrically connected to the source electrode 123 or the drain electrode 124 is located in the transparent electrode layer 17, and the transparent electrode 171 corresponds to a common electrode. The bottom gate electrode 121 is electrically connected to the scan line 131, one of the source electrode 123 and the drain electrode 124 is electrically connected to the data line 151, the other is electrically connected to the transparent electrode 171, and the floating gate electrode 31 is disposed opposite to the channel 1221 of the thin film transistor.
The scan line 131 may provide a scan signal to the bottom gate electrode 121 of the thin film transistor 12, and the data line 151 may provide a data signal to the source electrode 123 or the drain electrode 124 of the thin film transistor 12 or collect a current on the source electrode 123 or the drain electrode 124. For example, if the tfts 12 on the driving substrate 1 are an array of N rows by M columns, N scan lines 131 and M data lines 151 may be provided, and the N scan lines may be regularly supplied row by row according to the program setting in the driving chip. When some sensing regions SS on the nth (1. ltoreq. N. ltoreq. N) column generate charge accumulation under the action of stress and the charge accumulation causes the channel current of the corresponding thin film transistor 12 to change, the current change can be collected by the data lines 151 corresponding to some sensing regions SS under the action of stress in a fixed scanning period and fed back to the driving chip.
For example, the semiconductor layer 122 mentioned in the foregoing embodiments may be a carbon nanotube film layer in practical applications. When the carbon nanotube film layer is used as the semiconductor layer to manufacture the thin film transistor, ion doping of the semiconductor layer is not needed, and the process is simple. In addition, fig. 9 is a schematic diagram of a voltage-current characteristic curve and a current change under stress of a CNT-TFT according to an embodiment of the present disclosure. As shown in fig. 9, the current-voltage characteristic curve (Id-Vg curve, Id is drain current, Vg is gate voltage) of the carbon nanotube thin film transistor (CNT-TFT) is V-shaped, the off-state voltage range of the gate is extremely narrow, the transistor can be turned on regardless of the positive or negative gate voltage, and the transistor can operate in a low current state and has a good bidirectional conduction performance.
Illustratively, in conjunction with fig. 9, when the bipolar thin film transistor operates near the minimum current, and the piezoelectric thin film layer 2 is under stress (compressive stress or tensile stress), the floating gate electrode 31 in contact with the piezoelectric thin film layer 2 will generate an accumulated charge Δ Q (the compressive stress corresponds to negative charge, and the tensile stress corresponds to positive charge), and the accumulated charge Δ Q will change the channel current of the thin film transistor, and since the channel current passes through the sub-threshold region, the sensitivity of the piezoelectric thin film device provided by this embodiment is very high, and by using the bidirectional conduction characteristic of the bipolar thin film transistor, the response can be generated to both tensile stress and compressive stress, so that the application range is wider.
The specific channel current variation relational expression is as follows:
ΔQ＝C1*ΔV，
Vgs＝Voff+ΔV，
ΔI＝Ids-Ioff，
c1 is floating gate capacitance between the floating gate layer and the second isolation layer, Δ V is the change of the voltage difference between the floating gate and the source electrode, VoffThe gate-source voltage difference, V, of the thin film transistor corresponding to the minimum current valuegsIn order to be subjected to the stress,gate-source voltage difference of thin film transistor, IdsWhen stressed, the gate-source current of the thin film transistor, Z is the width of the thin film transistor channel, L is the length of the thin film transistor channel, CgIs the gate capacitance of the thin film transistor, and μ is the electron mobility of the semiconductor layer of the thin film transistor, VthIs the voltage threshold of the thin film transistor, and Δ I is the channel current variation of the thin film transistor, IoffIs the minimum operating current of the thin film transistor. According to the relational expression, the stress on the piezoelectric thin film layer causes the floating gate layer to generate accumulated charges delta Q, the accumulated charges delta Q on the floating gate layer finally cause the channel current of the thin film transistor to change, and the stress magnitude and the stress type of the piezoelectric thin film layer can be obtained by testing the channel current variation delta I of the thin film transistor.
According to the piezoelectric thin film device, the floating gate layer is arranged to be in contact with the piezoelectric thin film layer, when the piezoelectric thin film layer is subjected to stress deformation to cause surface bound charge change, the floating gate layer can generate corresponding charge accumulation according to the surface bound charge change of the piezoelectric thin film layer, the process is that the floating gate layer converts weak surface bound charge change on the piezoelectric thin film layer into self charge accumulation, and the charge accumulation on the floating gate layer can be regarded as amplification of the surface bound charge on the piezoelectric thin film layer; the accumulation of charge on the floating gate layer causes a change in the channel current of the thin film transistor, and the stress applied to the piezoelectric thin film device can be obtained by measuring the change in current flowing through the thin film transistor, which can be regarded as further amplification of the charge on the floating gate layer. The piezoelectric thin film layer is matched with the floating gate layer and the thin film transistor, a preamplifier in the prior art can be replaced, and compared with the existing preamplifier, the floating gate layer senses the surface bound charges of the piezoelectric thin film layer and generates a process of self charge accumulation, the floating gate layer is sensitive, the accumulated charges of the floating gate layer are converted into current values which are easy to monitor by the aid of the stacked thin film transistor, sensing sensitivity of the piezoelectric thin film device is further improved, and the piezoelectric thin film device has a wider application range.
Fig. 10 is a schematic flowchart of a method for manufacturing a piezoelectric thin film device according to an embodiment of the present disclosure. As shown in fig. 10, the present embodiment provides a method for manufacturing a piezoelectric thin film device, including:
s1: arranging a plurality of thin film transistors on the substrate layer;
s2: arranging a floating gate layer on one side of the thin film transistors, which is far away from the substrate layer;
s3: and a piezoelectric film layer is arranged on one side of the floating gate layer, which is far away from the substrate layer.
In one possible implementation, step S1 may include the following steps:
cleaning the substrate layer; the substrate layer here may be made of a flexible substrate material PI (polyimide).
Depositing a first metal layer on the substrate layer; the first metal layer can adopt metal Mo, the deposition mode can adopt a sputtering coating mode, and the thickness of the first metal layer can be about 220 nm.
Etching the first metal layer to define a scanning line and a bottom gate electrode; the etching can adopt wet etching, it is easy to understand that the substrate with the first metal layer needs to be coated, exposed and developed by photoresist before etching so as to transfer the pattern on the mask plate to the first metal layer, the first metal layer which is not covered by the photoresist is etched by the wet etching, the remaining metal layer forms a scanning line and a bottom gate electrode, the photoresist stripping process is needed after the etching process is finished, and the same contents related to the subsequent etching steps will not be described again.
Depositing a first isolation layer on the etched substrate, where the material of the first isolation layer may adopt a single-layer structure of silicon oxide or silicon nitride, or a stacked or alternate stacked structure of silicon oxide and silicon nitride, for example, a film structure of silicon oxide-silicon nitride-silicon oxide, and the application is not limited specifically. The deposition mode of the film layer may adopt a plasma enhanced chemical vapor deposition process, and the thickness of the first isolation layer may be between 100 and 200nm, which is not specifically limited in this application.
Coating a semiconductor layer on the surface of the first isolation layer; the semiconductor layer may be made of carbon nanotubes, the coating process may be a solution process (spin-coating or din-coating), the diameter of the carbon nanotubes may be 1.4nm, and the average length may be 1-3 um.
Etching the semiconductor layer to define a channel pattern; the etching mode can adopt oxidation reaction ion etching.
Depositing a second metal layer on the etched substrate; the material of the second metal layer can adopt Cu, and the thickness can be about 200 nm.
And etching the second metal layer to define patterns of the data line, the source electrode and the drain electrode.
Preparing a second isolation layer on the etched substrate; the second isolation layer can be made of aluminum oxide or hafnium oxide, and atomic layer deposition of the aluminum oxide or the hafnium oxide has less fixed charges and less influence on channel carriers. The preparation process can adopt an ALD (atomic layer deposition) process, the thickness of a film layer can be about 50nm, the process temperature can adopt a temperature near 200 ℃, and the gas source can adopt trimethyl aluminum and water.
Etching the second isolation layer to form a via hole; the via passes through the second isolation layer to the source or drain.
Continuing with step S2, in some embodiments, step S2 may include:
preparing a floating gate layer on the second isolation layer; the floating gate layer can be made of Mo, and the preparation method can be a sputtering coating method.
And etching the floating gate layer to define the pattern of the floating gate electrode.
Continuing to perform step S3, in some embodiments, step S3 may include:
arranging a piezoelectric film layer on the substrate etched with the floating gate electrode pattern; the piezoelectric thin film layer can be made of PVDF, the film forming mode can be a PVDF solution spin coating mode, and the PVDF polymer thin film is formed after annealing. The position of the via hole on the second isolation layer can be avoided through the design of the coating transfer printing plate in the film forming process of the piezoelectric film layer.
Depositing a transparent electrode layer on the piezoelectric thin film layer; the transparent electrode layer can be made of ITO (indium tin oxide), the thickness can be about 135nm, the transparent electrode layer can be in contact with the source electrode or the drain electrode through the through hole, and the deposition mode can be a sputtering coating process.
And etching the transparent electrode layer to define the pattern of the transparent electrode.
While preferred embodiments of the present specification have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all changes and modifications that fall within the scope of the specification.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present specification without departing from the spirit and scope of the specification. Thus, if such modifications and variations of the present specification fall within the scope of the claims of the present specification and their equivalents, the specification is intended to include such modifications and variations.
Claims (10)
1. A piezoelectric thin film device, comprising:
a drive substrate including a substrate layer and a plurality of thin film transistors disposed on the substrate layer;
the piezoelectric thin film layer is arranged on one side, far away from the substrate layer, of the thin film transistors;
the floating gate layer is arranged between the piezoelectric thin film layer and the thin film transistors, and generates charge change when the piezoelectric thin film layer is stressed, and the charge change causes the channel current of the thin film transistors to change.
2. The piezoelectric thin film device of claim 1, wherein the floating gate layer comprises a floating gate metal layer.
3. The piezoelectric thin film device according to claim 2, wherein the floating gate metal layer includes a plurality of floating gate electrodes disposed opposite to channels of the thin film transistors.
4. The piezoelectric thin film device according to claim 3, wherein the floating gate metal layer has a multilayer metal structure.
5. The piezoelectric thin film device according to any one of claims 1 to 4, wherein the thin film transistor comprises a unipolar transistor or a bipolar transistor.
6. The piezoelectric thin film device according to claim 5, wherein a plurality of the thin film transistors are arranged in an array.
7. The piezoelectric thin film device according to claim 1, wherein the driving substrate further comprises a first metal layer, a second metal layer, and a transparent electrode layer sequentially disposed on the substrate layer; a first isolation layer is arranged between the first metal layer and the second metal layer, and a second isolation layer is arranged between the second metal layer and the transparent electrode layer;
the first metal layer comprises a plurality of scanning lines extending along a first direction, the second metal layer comprises a plurality of data lines extending along a second direction, the plurality of scanning lines and the plurality of data lines are intersected to define a plurality of induction areas, and the thin film transistor is arranged in the induction areas; the thin film transistor comprises a bottom gate electrode, a semiconductor layer, a source electrode and a drain electrode, wherein the bottom gate electrode is positioned on the first metal layer, the source electrode and the drain electrode are positioned on the second metal layer, the semiconductor layer is arranged between the first isolation layer and the second metal layer, and the source electrode and the drain electrode are both contacted with the semiconductor layer; the transparent electrode layer comprises a transparent electrode, a through hole is formed in the second isolation layer, and the transparent electrode is in electric contact with the source electrode or the drain electrode through the through hole.
8. The piezoelectric thin film device according to claim 7, wherein the semiconductor layer is a carbon nanotube thin film layer.
9. The piezoelectric thin film device of claim 1, wherein the substrate layer is made of a flexible material.
10. A method for manufacturing a piezoelectric thin film device, comprising:
arranging a plurality of thin film transistors on the substrate layer;
arranging a floating gate layer on one side of the thin film transistors far away from the substrate layer;
and arranging a piezoelectric thin film layer on one side of the floating gate layer, which is far away from the substrate layer, wherein the floating gate layer generates charge change when the piezoelectric thin film layer is stressed, and the charge change causes the channel current of the thin film transistor to change.
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