CN112596811A - Method, system, computer equipment and storage medium for reducing memory overhead by dynamic data loading - Google Patents

Method, system, computer equipment and storage medium for reducing memory overhead by dynamic data loading Download PDF

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CN112596811A
CN112596811A CN202011522425.0A CN202011522425A CN112596811A CN 112596811 A CN112596811 A CN 112596811A CN 202011522425 A CN202011522425 A CN 202011522425A CN 112596811 A CN112596811 A CN 112596811A
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model
address
loading
memory
models
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CN112596811B (en
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方利红
柳振强
包建意
陈波
徐韡
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Guanzhifu (Chongqing) Technology Co.,Ltd.
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Hangzhou Aixin Intelligent Technology Co ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/445—Program loading or initiating
    • G06F9/44568—Immediately runnable code
    • G06F9/44578—Preparing or optimising for loading
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
    • G06F9/5011—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals
    • G06F9/5016—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals the resource being the memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
    • G06F9/5011—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals
    • G06F9/5022—Mechanisms to release resources

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  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Stored Programmes (AREA)

Abstract

The application relates to a method, a system, computer equipment and a storage medium for reducing memory overhead by dynamic data loading, wherein the method comprises the following steps: setting a fixed model address, a current model address and a next model address in an RAM; loading models M1-Mn from FLASH in sequence by a CPU; loading the model M1 into the fixed model address through DMA, and simultaneously loading other models except the model M1 into the current model address and the next model address in sequence through DMA; except that the initialization step processes data through the CPU running model M1, the rest steps process data through the model loaded by the current model address, and the memory of the model is released after the data are processed until all the models are processed. According to the method, a large amount of model space which is not needed in the near term during operation is released by a dynamic model loading method, and the time consumption of the CPU caused by frequent loading is reduced by a DMA (direct memory access) cooperative model loading method.

Description

Method, system, computer equipment and storage medium for reducing memory overhead by dynamic data loading
Technical Field
The present application relates to the field of depth camera data processing technologies, and in particular, to a method, a system, a computer device, and a storage medium for reducing memory overhead in dynamic data loading.
Background
Nowadays, under the background of the era of rapid development of computer information technology, computer devices have more and more functions and more stable performance, which means that the data computation amount of a CPU is likely to be larger and larger. When a large number of models are needed to process data during the operation of computer equipment, in order to increase the operation efficiency of the equipment, the early computer programs mostly adopt the concept of changing space into time, that is, the models are loaded into the RAM of the CPU regardless of whether the models are used all the time.
However, when the device is required to perform more functions, more and more models need to be loaded and used, and according to the traditional concept of changing space and time, more memory space is needed, and a CPU with a larger memory needs to be changed to solve the requirement. This means that more capital equipment is required to be updated, and this increase in cost is not acceptable to the consumer or producer, either.
Disclosure of Invention
In view of the foregoing, it is desirable to provide a method, a system, a computer device and a storage medium for dynamic data loading with reduced memory overhead.
A method for reducing memory overhead in dynamic data loading comprises the following steps:
setting a fixed model address, a current model address and a next model address in an RAM;
loading models M1-Mn from FLASH in sequence by a CPU;
loading the model M1 into the fixed model address through DMA, and simultaneously loading other models except the model M1 into the current model address and the next model address in sequence through DMA;
except that the initialization step processes data through the CPU running model M1, the rest steps process data through the model loaded by the current model address, and the memory of the model is released after the data are processed until all the models are processed.
As an embodiment, the method further comprises the following steps:
when one model fails to process, the memories of the current model address and the next model address are released, and the model M1 is processed again.
As an embodiment, the sequentially loading the models M1-Mn from FLASH by the CPU specifically includes the following steps:
appointing a CPU to load the packet heads of the models M1 to Mn from FLASH in sequence, and acquiring and recording the sizes of the models to the corresponding sizes 1 to Size n;
and dynamically allocating the memory with the Size according to the model, and recording the memory address to the corresponding model address.
A method and system for reducing memory overhead in dynamic data loading includes:
the address unit is used for setting a fixed model address, a current model address and a next model address in the RAM;
the CPU unit is used for sequentially loading the models M1-Mn from the FLASH through the CPU;
a DMA unit, configured to load the model M1 into the fixed model address through DMA, and simultaneously load other models except the model M1 into the current model address and the next model address in sequence through DMA;
and the data processing unit is used for processing data through the model loaded by the current model address in the rest steps except the data processing through the CPU operation model M1 in the initialization step, and releasing the memory of the data processing unit after the data processing until all the models are processed.
A computer arrangement comprising a memory and a processor, the memory storing a computer program, characterized in that the processor, when executing the computer program, performs the steps of the method for dynamic data loading with reduced memory overhead.
A computer-readable storage medium, on which a computer program is stored which, when being executed by a processor, carries out the steps of the method for dynamic data loading with reduced memory overhead.
According to the method, the system, the computer equipment and the storage medium for reducing the memory overhead by dynamic data loading, a large amount of model space which is not needed in the near term of operation is released by a method for dynamically loading the model, and the time consumption of the CPU due to frequent loading is reduced by a method for cooperatively loading the model by DMA (direct memory access), so that the problem that the CPU needs to be replaced to ensure the normal operation of the algorithm is solved.
Drawings
FIG. 1 is a diagram of an application environment in which a method for reducing memory overhead for dynamic data loading is implemented, according to an embodiment;
FIG. 2 is a flow diagram illustrating a method for reducing memory overhead for dynamic data loading, according to an embodiment;
FIG. 3 is a block diagram of a system for dynamic data loading with reduced memory overhead, according to an embodiment;
FIG. 4 is a diagram illustrating an internal structure of a computer device according to an embodiment.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
The method for reducing memory overhead by dynamic data loading can be applied to the application environment shown in fig. 1. Wherein the terminal 102 communicates with the server 104 via a network. The terminal 102 may be, but not limited to, various personal computers, notebook computers, smart phones, tablet computers, and the like, and the server 104 may be implemented by an independent server or a server cluster formed by a plurality of servers.
In one embodiment, as shown in FIG. 2, a method for reducing memory overhead for dynamic data loading is provided. The method is described as an example of the application to the terminal in fig. 1, and the method includes the following steps:
s100: setting a fixed model address, a current model address and a next model address in an RAM;
s200: loading models M1-Mn from FLASH in sequence by a CPU;
s300: loading the model M1 into the fixed model address through DMA, and simultaneously loading other models except the model M1 into the current model address and the next model address in sequence through DMA;
s400: except that the initialization step processes data through the CPU running model M1, the rest steps process data through the model loaded by the current model address, and the memory of the model is released after the data are processed until all the models are processed.
Step S200 specifically includes the following:
appointing a CPU to load the packet heads of the models M1 to Mn from FLASH in sequence, and acquiring and recording the sizes of the models to the corresponding sizes 1 to Size n;
and dynamically allocating the memory with the Size according to the model, and recording the memory address to the corresponding model address.
Besides the steps, the method also comprises the following steps:
when one model fails to process, the memories of the current model address and the next model address are released, and the model M1 is processed again.
In an embodiment, the detailed flow of the method for reducing the memory overhead in dynamic data loading of the present invention is as follows:
step one, setting a model as M1To MnThe fixed model address AddrA, the current model address Addr B and the next model address AddrC are set in the RAM for storing 3 models except at M1When processing data, the memory space of the fixed model address Addr A is used, and the memory space of addrB is used by other models. Meanwhile, the Step variable Step is 0;
step two, appointing the CPU to load the model M from the FLASH in sequence1To MnThe Size of each model is obtained and recorded to the corresponding Size1To SizenPerforming the following steps;
step three, dynamically distributing Size1A memory with a certain size, and after recording the memory address to the fixed model address Add r A, loading the model M by using DMA1To fixed model address Addr A;
step four, using the model M when needed1When the data is processed, setting Step to be 1;
step five, dynamically distributing Size2A large memory for recording the memory address to the next model address Add R C, and loading the model M by using DMA2Moving to the next model address Addr C, and using the model M in the fixed model address Addr A1Processing data;
step six, if M1And if the data processing fails, the space of the next model address Addr C is released. Next step requires model M1Processing, returning to the step five;
step seven, after the model M1 successfully processes the data, the DMA is used for loading the M2 to the current model address Addr
B, simultaneously, dynamically allocating Size3Memory with the size of the memory, and the memory address is recorded to the next model address Addr
C, setting Step to Step + 1; the next round of processing data through model M2, and similarly, subsequent steps process data sequentially through other models, and in subsequent steps, the model that currently processes data uses M to process dataStepExpressing;
step eight, if the model MStepSuccessful treatment, requiring model MStep+1When processing data, firstly interchanging the addresses of the current model address Addr B and the next model address Addr C, and setting Step to Step + 1;
step nine, dynamically distributing SizeStep+1The memory with the size is used for recording the memory address AddrC and loading the model M by using DM AStep+1Moving to the next model address Addr C, and using the model M in the current model address Addr BStepProcessing data;
step ten, if the model MStepFailure to process the data, the next step requires step M1Processing, firstly releasing the memory space of the current model address Addr B and the next model address Addr CReturning to the step four;
step eleven, if the model MStepProcessing is successful, Step is less than n-1, and the Step eight is returned after the current model address Ad dr B is released;
step twelve, if the model MStepThe processing is successful, and Step is equal to n-1, and after the current model address Ad dr B is released, Step is equal to n;
step thirteen, interchanging the addresses of the current model address Addr B and the next model address Addr C, and obtaining the model MnAfter the processing is finished, whether the processing is successful or failed, the next step is the model M1And processing, releasing the current model address Addr B, and returning to the step four.
In an embodiment, as shown in fig. 3, a method and system for reducing memory overhead in dynamic data loading includes an address unit 1, a CPU unit 2, a DMA unit 3, and a data processing unit 4, where the address unit 1 is configured to set a fixed model address, a current model address, and a next model address in a RAM; the CPU unit 2 is used for sequentially loading the models M1-Mn from the FLASH through the CPU; the DMA unit 3 is used for loading the model M1 into the fixed model address through DMA, and simultaneously loading other models except the model M1 into the current model address and the next model address in sequence through DMA; the data processing unit 4 is configured to, except for the initialization step, process data by running the model M1 through the CPU, process data by using the model loaded by the current model address in the remaining steps, and release the memory of the data processing unit after the data processing until all the models are processed.
For the specific limitations of the above system, reference may be made to the limitations of the above method, which are not described herein again. The various modules in the above-described apparatus may be implemented in whole or in part by software, hardware, and combinations thereof. The modules can be embedded in a hardware form or independent from a processor in the computer device, and can also be stored in a memory in the computer device in a software form, so that the processor can call and execute operations corresponding to the modules.
In one embodiment, a computer device is provided, which may be a server, the internal structure of which may be as shown in fig. 4. The computer device includes a processor, a memory, a network interface, and a database connected by a system bus. Wherein the processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device comprises a nonvolatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program, and a database. The internal memory provides an environment for the operation of an operating system and computer programs in the non-volatile storage medium. The database of the computer equipment is used for storing the data of the human face living body detection method based on the infrared image. The network interface of the computer device is used for communicating with an external terminal through a network connection. The computer program is executed by a processor to realize a human face living body detection method based on infrared images.
Those skilled in the art will appreciate that the architecture shown in fig. 4 is merely a block diagram of some of the structures associated with the disclosed aspects and is not intended to limit the computing devices to which the disclosed aspects apply, as particular computing devices may include more or less components than those shown, or may combine certain components, or have a different arrangement of components.
In one embodiment, there is provided a computer device comprising a memory and a processor, the memory storing a computer program, the processor implementing the following steps when executing the computer program:
s100: setting a fixed model address, a current model address and a next model address in an RAM;
s200: loading models M1-Mn from FLASH in sequence by a CPU;
s300: loading the model M1 into the fixed model address through DMA, and simultaneously loading other models except the model M1 into the current model address and the next model address in sequence through DMA;
s400: except that the initialization step processes data through the CPU running model M1, the rest steps process data through the model loaded by the current model address, and the memory of the model is released after the data are processed until all the models are processed.
Step S200 specifically includes the following:
appointing a CPU to load the packet heads of the models M1 to Mn from FLASH in sequence, and acquiring and recording the sizes of the models to the corresponding sizes 1 to Size n;
and dynamically allocating the memory with the Size according to the model, and recording the memory address to the corresponding model address.
Besides the steps, the method also comprises the following steps:
when one model fails to process, the memories of the current model address and the next model address are released, and the model M1 is processed again.
In an embodiment, the detailed flow of the method for reducing the memory overhead in dynamic data loading of the present invention is as follows:
step one, setting a model as M1To MnThe fixed model address AddrA, the current model address Addr B and the next model address AddrC are set in the RAM for storing 3 models except at M1When processing data, the memory space of the fixed model address Addr A is used, and the memory space of addrB is used by other models. Meanwhile, the Step variable Step is 0;
step two, appointing the CPU to load the model M from the FLASH in sequence1To MnThe Size of each model is obtained and recorded to the corresponding Size1To SizenPerforming the following steps;
step three, dynamically distributing Size1A memory with a certain size, and after recording the memory address to the fixed model address Add r A, loading the model M by using DMA1To fixed model address Addr A;
step four, using the model M when needed1When the data is processed, setting Step to be 1;
step five, dynamically distributing Size2A large memory for recording the memory address to the next model address Add R C, and loading the model M by using DMA2Moving to the next model address Addr C, and using the model M in the fixed model address Addr A1Processing data;
step six, if M1And if the data processing fails, the space of the next model address Addr C is released. Next step requires model M1Processing, returning to the step five;
step seven, after the model M1 successfully processes the data, the DMA is used for loading the M2 to the current model address Addr
B, simultaneously, dynamically allocating Size3Memory with the size of the memory, and the memory address is recorded to the next model address Addr
C, setting Step to Step + 1; the next round of processing data through model M2, and similarly, subsequent steps process data sequentially through other models, and in subsequent steps, the model that currently processes data uses M to process dataStepExpressing;
step eight, if the model MStepSuccessful treatment, requiring model MStep+1When processing data, firstly interchanging the addresses of the current model address Addr B and the next model address Addr C, and setting Step to Step + 1;
step nine, dynamically distributing SizeStep+1The memory with the size is used for recording the memory address AddrC and loading the model M by using DM AStep+1Moving to the next model address Addr C, and using the model M in the current model address Addr BStepProcessing data;
step ten, if the model MStepFailure to process the data, the next step requires step M1Processing, namely releasing the memory space of the current model address Addr B and the next model address Addr C, and returning to the step four;
step eleven, if the model MStepProcessing is successful, Step is less than n-1, and the Step eight is returned after the current model address Ad dr B is released;
step twelve, if the model MStepThe processing is successful, and Step is equal to n-1, and after the current model address Ad dr B is released, Step is equal to n;
step thirteen, interchanging the addresses of the current model address Addr B and the next model address Addr C, and obtaining the model MnAfter the processing is finished, whether the processing is successful or failed, the next step is the model M1And processing, releasing the current model address Addr B, and returning to the step four.
In one embodiment, a computer-readable storage medium is provided, having a computer program stored thereon, which when executed by a processor, performs the steps of:
s100: setting a fixed model address, a current model address and a next model address in an RAM;
s200: loading models M1-Mn from FLASH in sequence by a CPU;
s300: loading the model M1 into the fixed model address through DMA, and simultaneously loading other models except the model M1 into the current model address and the next model address in sequence through DMA;
s400: except that the initialization step processes data through the CPU running model M1, the rest steps process data through the model loaded by the current model address, and the memory of the model is released after the data are processed until all the models are processed.
Step S200 specifically includes the following:
appointing a CPU to load the packet heads of the models M1 to Mn from FLASH in sequence, and acquiring and recording the sizes of the models to the corresponding sizes 1 to Size n;
and dynamically allocating the memory with the Size according to the model, and recording the memory address to the corresponding model address.
Besides the steps, the method also comprises the following steps:
when one model fails to process, the memories of the current model address and the next model address are released, and the model M1 is processed again.
In an embodiment, the detailed flow of the method for reducing the memory overhead in dynamic data loading of the present invention is as follows:
step one, setting a model as M1To MnThe fixed model address AddrA, the current model address Addr B and the next model address AddrC are set in the RAM for storing 3 models except at M1When processing data, the memory space of the fixed model address Addr A is used, and the memory space of addrB is used by other models. Meanwhile, the Step variable Step is 0;
step two, appointing the CPU to load the model M from the FLASH in sequence1To MnThe Size of each model is obtained and recorded to the corresponding Size1To SizenPerforming the following steps;
step three, dynamically distributing Size1A memory with a certain size, and after recording the memory address to the fixed model address Add r A, loading the model M by using DMA1To fixed model address Addr A;
step four, using the model M when needed1When the data is processed, setting Step to be 1;
step five, dynamically distributing Size2A large memory for recording the memory address to the next model address Add R C, and loading the model M by using DMA2Moving to the next model address Addr C, and using the model M in the fixed model address Addr A1Processing data;
step six, if M1And if the data processing fails, the space of the next model address Addr C is released. Next step requires model M1Processing, returning to the step five;
step seven, after the model M1 successfully processes the data, the DMA is used for loading the M2 to the current model address Addr
B, simultaneously, dynamically allocating Size3Memory with the size of the memory, and the memory address is recorded to the next model address Addr
C, setting Step to Step + 1; the next round of processing data through model M2, and similarly, subsequent steps process data sequentially through other models, and in subsequent steps, the model that currently processes data uses M to process dataStepExpressing;
step eight, if the model MStepSuccessful treatment, requiring model MStep+1When processing data, firstly interchanging the addresses of the current model address Addr B and the next model address Addr C, and setting Step to Step + 1;
step nine, dynamically distributing SizeStep+1The memory with the size is used for recording the memory address AddrC and loading the model M by using DM AStep+1Moving to the next model address Addr C, and using the model M in the current model address Addr BStepProcessing data;
step ten, if the model MStepFailure to process the data, the next step requires step M1Processing, namely releasing the memory space of the current model address Addr B and the next model address Addr C, and returning to the step four;
step eleven, if the model MStepProcessing is successful, Step is less than n-1, and the Step eight is returned after the current model address Ad dr B is released;
step twelve, if the model MStepThe processing is successful, and Step is equal to n-1, and after the current model address Ad dr B is released, Step is equal to n;
step thirteen, interchanging the addresses of the current model address Addr B and the next model address Addr C, and obtaining the model MnAfter the processing is finished, whether the processing is successful or failed, the next step is the model M1And processing, releasing the current model address Addr B, and returning to the step four.
It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by hardware related to instructions of a computer program, which can be stored in a non-volatile computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. Any reference to memory, storage, database, or other medium used in the embodiments provided herein may include non-volatile and/or volatile memory, among others. Non-volatile memory can include read-only memory (ROM), Programmable ROM (PROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms, such as Static RAM (SRAM), Dynamic RAM (DRAM), Synchronous DRAM (SDRAM), Double Data Rate SDRAM (DDRSDRAM), Enhanced SDRAM (ESDRAM), synchronous Link (Synchlink)
Dram (sldram), Rambus (Rambus) direct ram (rdram), direct memory bus dynamic ram (drdram), and memory bus dynamic ram (rdram), among others.
The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims (6)

1. A method for reducing memory overhead in dynamic data loading is characterized by comprising the following steps:
setting a fixed model address, a current model address and a next model address in an RAM;
loading models M1-Mn from FLASH in sequence by a CPU;
loading the model M1 into the fixed model address through DMA, and simultaneously loading other models except the model M1 into the current model address and the next model address in sequence through DMA;
except that the initialization step processes data through the CPU running model M1, the rest steps process data through the model loaded by the current model address, and the memory of the model is released after the data are processed until all the models are processed.
2. The method for reducing memory overhead for dynamic data loading according to claim 1, further comprising the steps of:
when one model fails to process, the memories of the current model address and the next model address are released, and the model M1 is processed again.
3. The method for reducing memory overhead in dynamic data loading according to claim 1, wherein the loading of the models M1-Mn from FLASH in sequence by the CPU specifically comprises the following steps:
appointing a CPU to load the packet heads of the models M1 to Mn from FLASH in sequence, and acquiring and recording the sizes of the models to the corresponding sizes 1 to Size n;
and dynamically allocating the memory with the Size according to the model, and recording the memory address to the corresponding model address.
4. A method and system for reducing memory overhead in dynamic data loading is characterized by comprising the following steps:
the address unit is used for setting a fixed model address, a current model address and a next model address in the RAM;
the CPU unit is used for sequentially loading the models M1-Mn from the FLASH through the CPU;
a DMA unit, configured to load the model M1 into the fixed model address through DMA, and simultaneously load other models except the model M1 into the current model address and the next model address in sequence through DMA;
and the data processing unit is used for processing data through the model loaded by the current model address in the rest steps except the data processing through the CPU operation model M1 in the initialization step, and releasing the memory of the data processing unit after the data processing until all the models are processed.
5. A computer device comprising a memory and a processor, the memory storing a computer program, characterized in that the processor realizes the steps of the method of any one of claims 1 to 3 when executing the computer program.
6. A computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out the steps of the method of any one of claims 1 to 3.
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