CN112595966A

CN112595966A - IEEE standard based Chiplet circuit testing method

Info

Publication number: CN112595966A
Application number: CN202110233827.7A
Authority: CN
Inventors: 蔡志匡; 王运波; 宋健; 周国鹏; 王子轩
Original assignee: Nanjing University of Posts and Telecommunications
Current assignee: Nanjing University of Posts and Telecommunications
Priority date: 2021-03-03
Filing date: 2021-03-03
Publication date: 2021-04-02

Abstract

The invention provides a test method of a Chiplet circuit based on IEEE 1687 standard, which comprises the following steps: 1) reading all designed ICL and PDL, and modeling the complete chip by using the ICL and the PDL; 2) performing an IEEE 1687 design rule check to verify that instructions and other components (e.g., SIBs, etc.) are properly connected to the various levels of the design; 3) carrying out test vector redirection from the core particles to the chip to generate a test vector for testing the chip; 4) converting the generated reoriented IEEE 1687 PDL into a testbench and a standard test vector format; the Chiplet test technology provided by the invention can realize that the test vector is redirected to the chip, the test structure is more flexible, and the test effectiveness can be improved under the condition of not increasing the area cost.

Description

IEEE standard based Chiplet circuit testing method

Technical Field

The invention relates to the field of testing of ultra-large-scale digital integrated circuits, in particular to a testing method of a chip circuit based on an IEEE standard.

Background

With the development of chip technology, Very Large Scale Integration (VLSI) manufacturing technology has become one of the important factors supporting the continuous development and progress of the information society. The mass production process of the nano-crystalline silicon material reaches 7nm nowadays, and the process is advancing to 5nm and 3nm along with the improvement of the process. However, as the process complexity of very large scale integrated circuits increases dramatically, the corresponding manufacturing cost also increases dramatically. This presents a significant challenge to the design and implementation of multi-domain chips. When multiple chips are integrated into one product, the higher the yield of the assembly, the lower the yield loss at the final assembly. It is widely accepted by the industry and academia that "supermolar" and "post-molar" times are forthcoming. In recent years, with the rapid development of tsv (through Silicon via) technology, it provides a new architecture for 3D technology. By using the layering technique, the most suitable product can be assembled: one possible solution is to divide a large single chip with a low yield into smaller chips with a higher yield. These chips are fabricated, tested, and then assembled in a three-dimensional dielectric layer. In the background, a chip (also called a core particle or a small chip) heterogeneous integration technology has received much attention as a key technology for solving the above problems. Chip technology attempts to integrate a plurality of modular chips into one package through internal interconnection technology to form heterogeneous chips with special functions, thereby solving the problems of scale, development cost, reduced cycle time of cost, and the like involved in chip development. By adopting advanced packaging technologies such as 2.5D and 3D, the chip can realize high-performance on-chip interconnection of multiple chips, the integration level of a chip system is improved, and the performance and power consumption optimization space of the chip system are expanded. In addition, the modularized integration method can effectively improve the research and development speed of the chip, reduce the research and development cost and the chip development threshold, and can focus the research and development of the chip on the algorithm and the core technology, thereby improving the overall innovation level and the capability of the industry. Design for testability is a significant challenge in terms of the above integration approach, where the test architecture must allow for both pre-assembly single die testing and post-assembly full chip testing to improve fault coverage. Also in this case, the test vectors from pre-assembly to post-assembly testing must be easily redirected to reduce test development effort, to easily test individual components, and to reduce test costs.

Disclosure of Invention

The invention aims to provide a test method of a Chiplet circuit based on IEEE standard, which not only can test classical logic (digital logic, IO, RAM and the like) on a chip and test connected TSV, but also can test a final chip circuit. By using IEEE 1687ICL and PDL language to redirect the test vector, the operation can realize the test from the redirection of the core grain to the chip, thereby ensuring the test operation of each component at different levels.

The invention provides a test method of a Chiplet circuit based on IEEE standard, which comprises the following steps of;

the method comprises the following steps: reading ICL and PDL of all designs, modeling a complete chip by using the ICL and PDL, and inserting a test circuit by using a tool;

step two: performing an IEEE 1687 standard design rule check to verify that instructions and other components (e.g., SIBs, etc.) are properly connected to the various levels of the design;

step three: carrying out test vector redirection from the core particles to the chip to generate a test vector for testing the chip;

step four: the generated redirected PDL of the IEEE 1687 standard is converted into testbench and a standard test vector format.

The further improvement lies in that: reading in all ICLs and PDLs of a non-chip level according to an existing chip level RTL design circuit, constructing a chip level network structure, automatically inserting a TAP controller, an SIB/TDR and a boundary scanning unit test circuit by using a tesent tool, and finally extracting the ICLs and the PDLs of all modules into a database to generate a final netlist.

The further improvement lies in that: the second step performs IEEE 1687 design rule checking: firstly, checking ICL connection rules among core particles, then checking the ICL connection rules of a dielectric layer and the core particles, and finally finishing the ICL connection rule check of the whole chip.

The further improvement lies in that: and in the third step, a PDL process is programmed to control the operation of testing different layers, and the PDL description of the core particles is relocated to the chip. Generating a test vector for testing the core grain by setting a current design variable as the core grain; test vectors for testing the chip are generated by setting the current design variables to the chip.

The further improvement lies in that: and step four, converting the redirected PDL of the IEEE 1687 standard into testbench and standard test vectors, wherein the test vectors are in a WGL (WGL) or STIL (static test language) or SVF (singular value decomposition) format for simulation verification and machine testing.

The invention has the beneficial effects that: the proposed circuit testing method allows testing at the core die and chip level, by which not only classical logic (digital logic, IO, RAM, etc.) on the core die and TSVs connected to the test can be tested, but also the final chip circuit can be tested. By utilizing IEEE 1687ICL and PDL languages, the test vector can be redirected, and the operation from the redirection of the core particles to the chip is realized, so that the test of each component at different levels is ensured, the structure is more flexible, and the test effectiveness can be improved under the condition of not increasing the area cost.

Drawings

FIG. 1 is a test layout of a Chiplet circuit based on the IEEE 1687 standard;

FIG. 2 is a flow chart of a Chiplet test circuit based on the IEEE 1687 standard;

FIG. 3 is a core grain redirection chip test flow of the present invention;

FIG. 4 is a block diagram of a SIB-TDR-based access BIST circuit controlled Memory in accordance with the present invention.

Detailed Description

In order to enhance the understanding of the present invention, the present invention will be further described with reference to the following examples, which are provided for illustration only and are not intended to limit the scope of the present invention.

As shown in fig. 1-4, the present embodiment provides a method for testing a chipset circuit based on IEEE standard, which comprises the following steps:

Reading in all ICLs and PDLs of a non-chip level according to an existing chip level RTL design circuit, constructing a chip level network structure, automatically inserting a TAP controller, an SIB/TDR and a boundary scanning unit test circuit by using a tesent tool, and finally extracting all modules ICLs and PDLs of the modules into a database to generate a final netlist. In the second step, the design rule check of the IEEE 1687 standard is executed: firstly, checking ICL connection rules among core particles, then checking the ICL connection rules of a dielectric layer and the core particles, and finally finishing the ICL connection rule check of the whole chip. Writing PDL process in the third step to control the test of different levels, relocating PDL description of the core particles to the chip, and generating test vectors for testing the core particles by setting the current design variables as the core particles; test vectors for testing the chip are generated by setting the current design variables to the chip. And step four, converting the redirected PDL of the IEEE 1687 standard into testbench and standard test vectors, wherein the format of the test vectors is WGL, STIL or SVF for simulation verification and machine testing.

The testing method is improved aiming at the technical problem of how to test the Chiplet structure, and creatively exemplifies the testing method based on the IEEE 1687 standard Chiplet circuit, and the implemented testing structure considers the comprehensiveness of the core particles, the dielectric layer and the whole chip. By the circuit testing method, the classical logic (digital logic, IO, RAM and the like) on the chip and the TSV connected with the chip can be tested, and the final chip circuit can be tested. By using IEEE 1687ICL and PDL language to redirect the test vector, the method can realize the operation of redirecting from the core grain to the chip, thereby ensuring the test of each component at different levels. Therefore, faults of all layers can be well detected, and the fault coverage rate is improved.

Fig. 1 shows a test design diagram of a chip circuit based on IEEE 1687 standard, as shown in the figure, a chip structure is constructed according to the RTL description, that is, 3 core particles are stacked on one dielectric layer to form a whole chip. Reading in all ICLs and PDLs of a non-chip level, and constructing a chip level network structure. The DFT architecture requires that all core dies are inserted into the JTAG interface (TDI, TDO, TMS, TCK, optional TRST), TAP controller and Segment Insert Bits (SIB) and associated Test Data Registers (TDR) as test access mechanisms to form a scan chain. The TAP controller is automatically generated by using a tesent tool to access the Mbist circuit through SIB/TDR to test the memory and test the IP module, and the port is tested by using a boundary scan register, etc. A selector in the core die is used to switch the test path between the core die and the chip. During the core grain testing period, respective testing data are respectively input into TDI ports of 3 accumulated core grains and dielectric layers, testing is carried out through respective scan chains, then testing results are respectively output from respective TDO ports, output results are compared with theoretical results, if the output results are consistent with the theoretical results, testing is free of problems, otherwise, faults exist, and in the testing period, the three core grains are mutually independent and do not influence each other. During chip testing, the TDI of the test data dielectric layer is transmitted to the core particles, a test path is configured by using the instruction register, test data can finally reach the dielectric layer TDO (a bold line in fig. 1 is a path) through the three core particles, a test flow is written by using a tesent tool so as to test a circuit, similarly, during chip testing, a test vector is input through the TDI, an output test result is observed through the TDO, and the output result is compared with a theoretical result. The test vectors required for testing are provided by the PDL redirecting the test vectors generated by the component. The selector in the dielectric layer is used for bypassing the core grains with faults, so that the test path is better adjusted, the test coverage rate is improved, and the test time is saved.

Fig. 2 shows a flow chart of the test of the chip circuit based on the IEEE 1687 standard, as shown in the figure, four steps need to be completed to complete the test circuit, step one: reading ICL and PDL of all designs, modeling a complete chip by using the ICL and PDL, and inserting a test circuit by using a tool; step two: performing an IEEE 1687 standard design rule check to verify that instructions and other components (e.g., SIBs, etc.) are properly connected to the various levels of the design; step three: carrying out test vector redirection from the core particles to the chip to generate a test vector for testing the chip; step four: the generated redirected PDL of the IEEE 1687 standard is converted into testbench and a standard test vector format.

Reading in all ICLs and PDLs of a non-chip level according to an existing chip level RTL design circuit, constructing a chip level network structure, automatically inserting a TAP controller, an SIB/TDR and a boundary scanning unit test circuit by using a tesent tool, and finally extracting all modules ICLs and PDLs of the modules into a database to generate a final netlist. Step two includes executing IEEE 1687 standard design rule check: firstly, checking ICL connection rules among core particles, then checking the ICL connection rules of a dielectric layer and the core particles, and finally finishing the ICL connection rule check of the whole chip. Step three, writing a PDL process to control tests of different levels, relocating PDL description of the core particles to a chip, and generating test vectors for testing the core particles by setting current design variables as the core particles; test vectors for testing the chip are generated by setting the current design variables to the chip. Step four, converting the PDL of the reoriented IEEE 1687 standard into testbench and standard test vectors in the format of WGL, STIL and SVF for simulation verification and machine testing.

FIG. 3 is a flow chart of the testing of the core grain redirection chip of this example. First, for DFT insertion, TAP logic generation, all tasks of BSR logic generation can be done automatically by the tool. In the first step of core grain test, test vectors need to be generated to provide test input for testing core grains, and the core grain test is completed according to the set TAP chain path. The TAP chain comprises SIB-TDR, memory BIST, boundary scan unit, test module and other units. And in the second step of chip testing, firstly, the connection of the core particles and the dielectric layer is required to form an integral chip structure, and the chip testing is completed according to the set TAP chain path. The TAP chain comprises a medium layer, three SIB-TDR units required by the interior of a core particle, a memory BIST unit, a boundary scanning unit, a test module and the like. The test core grain and the chip generate the test vectors required by each layer through PDL configuration.

FIG. 4 is a block diagram of the SIB-TDR-based access BIST circuit control memory architecture of the present example, the proposed SIB-TDR registers are integrated into the TAPchain for accessing the built-in self-test circuit, which will implement the different BIST command registers to set and enable the BIST circuit, and ultimately read the memory BIST results. Wherein the SIB-TDR register can be configured and processed by the test tool to allow testing of the memory by Mbist from the core die or chip.

The above description is only a preferred embodiment of the present invention, and is not intended to limit the present invention, and all equivalent variations made by using the contents of the present specification and the drawings are within the protection scope of the present invention.

Claims

1. A method for testing a Chiplet circuit based on an IEEE standard is characterized by comprising the following steps:

step two: performing an IEEE 1687 standard design rule check to verify that instructions and other components are properly connected to the various levels of the design;

2. The IEEE standard-based Chiplet circuit testing method as claimed in claim 1, wherein the first step is to design a circuit according to an existing chip level RTL, read in all ICLs and PDLs of a non-chip level, construct a chip level network structure, automatically insert a test circuit by using a tesent tool, and finally extract the ICLs and PDLs of all modules into a database to generate a final netlist.

3. The IEEE standard-based chip circuit testing method of claim 1, wherein the IEEE 1687 standard design rule checking method performed in step two is as follows: firstly, checking ICL connection rules among core particles, then checking the ICL connection rules of a dielectric layer and the core particles, and finally finishing the ICL connection rule check of the whole chip.

4. The IEEE standard-based Chiplet circuit testing method of claim 1, wherein in the third step, a PDL process is programmed to control different levels of testing, the PDL description of the core grain is relocated to the chip, and a test vector for testing the core grain is generated by setting a current design variable as the core grain; test vectors for testing the chip are generated by setting the current design variables to the chip.

5. The IEEE standard Chiplet circuit testing method as claimed in claim 1, wherein the fourth step is converting the PDL of the reoriented IEEE 1687 standard into testbench and standard test vectors in the format of WGL, STIL or SVF for simulation verification and machine testing.