CN112582428A

CN112582428A - Integrated circuit device

Info

Publication number: CN112582428A
Application number: CN202011031328.1A
Authority: CN
Inventors: 钟淑维; 王彦森
Original assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date: 2019-09-27
Filing date: 2020-09-27
Publication date: 2021-03-30

Abstract

An Integrated Circuit (IC) apparatus according to the present disclosure, comprising: a substrate including a first surface and a second surface opposite to the first surface; a redistribution layer disposed on the first surface and including conductive features; a passivation structure disposed on the redistribution layer; a metal-insulator-metal (MIM) capacitor embedded in the passivation structure; a dummy MIM feature embedded in the passivation structure and including an opening; a top contact pad on the passivation structure; a contact via extending between the conductive feature and the top contact pad; and a through via extending through the passivation structure and the substrate. The dummy MIM feature is separated from the MIM capacitor and the through via extends through the opening of the dummy MIM feature and does not contact the dummy MIM feature.

Description

Integrated circuit device

Technical Field

The present disclosure relates to integrated circuit devices, and more particularly, to integrated circuit devices having dummy metal-insulator-metal structures.

Background

The Integrated Circuit (IC) industry has experienced rapid growth. As ICs evolve, the functional density (i.e., the number of interconnects per unit of chip area) generally increases, while the geometry (i.e., the smallest component (or line) that can be created using a fabrication process) decreases.

As semiconductor devices continue to shrink, manufacturing challenges may ensue. Passive devices requiring a larger surface area may be moved to back-end-of-line (BEOL) structures. Metal-Insulator-Metal (MIM) capacitors are examples of such passive components. A typical MIM capacitor includes multiple conductor plate (conductor plate) layers that are insulated from each other by multiple insulator layers. To mitigate uneven etch loading and uneven mechanical strength caused by uneven distribution of MIM capacitors, dummy MIM structures with equal value (configurable) conductor plate layers may be inserted in the isolation regions without MIM capacitors. The presence of vias that lack long-range order features (long-range order seeds) presents challenges to uniform distribution of the dummy MIM structure, and results in less-than-optimal etch loading and reduced mechanical strength. Thus, while current semiconductor fabrication methods have been generally adequate for their intended purposes, they have not been entirely satisfactory in every aspect.

Disclosure of Invention

The disclosed embodiments provide an Integrated Circuit (IC) device. The IC device includes: the substrate comprises a first surface and a second surface opposite to the first surface; a redistribution layer disposed on the first surface and including conductive features; a passivation structure disposed on the redistribution layer; a metal-insulator-metal (MIM) capacitor embedded in the passivation structure; a dummy MIM feature embedded in the passivation structure and including an opening; a top contact pad on the passivation structure; a contact via extending between the conductive feature and the top contact pad; and a through via extending through the passivation structure and the substrate. The dummy MIM feature is separated from the MIM capacitor and the through via extends through the opening of the dummy MIM feature and does not contact the dummy MIM feature.

The disclosed embodiments provide a method of manufacturing an integrated circuit device. The method comprises the following steps: receiving a design comprising a plurality of metal-insulator-metal (MIM) structures and a plurality of vias, the vias not extending through the MIM structures; determining a plurality of dummy MIM shapes; identifying a subset of the vias that overlap the dummy MIM shape; determining a plurality of opening shapes located on the subset of the vias; superposing the dummy MIM shapes and the opening shapes to obtain a plurality of final dummy MIM structures; and inserting the final dummy MIM structure into the design to obtain a modified design.

The disclosed embodiments provide a method of manufacturing an integrated circuit device. The method includes receiving a design, the design including: a substrate; a redistribution layer disposed on the substrate and including a conductive feature; a passivation structure disposed on the redistribution layer; a plurality of metal-insulator-metal (MIM) capacitors embedded in the passivation structure; and a plurality of through vias extending through the passivation structure and the substrate, the through vias being separated from the MIM capacitor. The method further comprises the following steps: determining a plurality of dummy MIM shapes based on a distribution of the MIM capacitor structures in the passivation structure; identifying a subset of the through vias that overlap the virtual MIM shape; determining a plurality of opening shapes on the subset of through-holes; superposing the dummy MIM shapes and the opening shapes to obtain a plurality of final dummy MIM structures; and inserting the final dummy MIM structure into the design to obtain a modified design.

Drawings

Aspects of the disclosure can be better understood from the following description and drawings. It is emphasized that, according to the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

FIG. 1 is a partial cross-sectional view of a device according to the present disclosure.

Fig. 2 is a flow chart of a method for inserting a dummy metal-insulator-metal (MIM) structure according to an aspect of the present disclosure.

FIG. 3 is a simplified block diagram of an Integrated Circuit (IC) manufacturing system and associated IC manufacturing flow, according to aspects of the present disclosure.

Fig. 4, 5, 6A, 6B, 7A, 7B, 8A, 8B are partial top views of an apparatus at various conceptual stages of the method of fig. 3, shown in accordance with aspects of the present disclosure.

Fig. 9A-9D are schematic top views of exemplary dummy MIM structures according to aspects of the present disclosure.

Fig. 10A-10C are schematic cross-sectional views of the dummy MIM structure along line I-I' in fig. 9A, according to aspects of the present disclosure.

FIG. 11 is a partial top view of a device according to aspects of the present disclosure.

Wherein the reference numerals are as follows:

10: a first die

12: first substrate

12-1: first surface

12-2: second surface

14: first redistribution structure

16: a first passivation structure

20: second crystal grain

22: second substrate

24: second redistribution layer

26: second passivation structure

30: first isolation region

32: second isolation region

100: IC device

110: first top contact pad

112: second top contact pad

120: a first MIM structure

122: second MIM structure

130: first conductive feature

132: second conductive feature

140: first contact via

142: second through via

150: the first through hole

152: second through via

160: first bottom contact pad

162: second bottom contact pad

1201: bottom conductor plate layer

1202: intermediate conductor plate layer

1203: top conductor plate layer

200: method of producing a composite material

202-216: square frame

300: IC manufacturing system

302: design studio

304: photomask studio

306: IC manufacturer

400: isolated area template

400A: rectangular virtual MIM shape

400B: square virtual MIM shape

500A: first opening shape

500B: second opening shape

400C: diamond virtual MIM shape

400D: stepped virtual MIM shape

500C: third opening shape

500D: fourth opening shape

170: dummy MIM structure

172: dummy MIM structure

S: distance between each other

M: minimum margin

I-I': line segment

1701: bottom dummy conductor plate layer

1702: middle virtual conductor plate layer

1703: top dummy conductor plate layer

100': IC device

180: first opening

182: second opening

Detailed Description

It is to be understood that the following disclosure provides many different embodiments, or examples, for implementing different features of the disclosure. Specific examples of the components and arrangements of the present disclosure are set forth below to simplify the description. Of course, these examples are not intended to limit the present disclosure. For example, if the description recites a first feature formed on or over a second feature, it may include embodiments in which the first and second features are formed in direct contact, and it may also include embodiments in which additional features are formed between the first and second features, such that direct contact between the first and second features is not provided. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, the present disclosure may use spatially relative terms, such as "below …," "below," "…," "above," and the like, to facilitate describing the relationship of one element or feature to another element or feature in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below …" can include both an orientation of "above …" and "below …". The device may be turned to a different orientation (rotated 90 degrees or otherwise) and the spatially relative terms used herein should be interpreted accordingly.

Still further, when a number or range of numbers is described in terms of "about," "approximately," or the like, the term is intended to encompass reasonable numbers including the number, such as +/-10% of the number or other value as understood by one of ordinary skill in the art. For example, the term "about 5 nanometers (nm)" covers a size ranging from 4.5nm to 5.5 nm.

Metal-insulator-metal (MIM) capacitors (or ultra-high density MIM, SHDMIM) have been widely used for functional circuits such as mixed signal (mixed signal) circuits, analog circuits, Radio Frequency (RF) circuits, Dynamic Random Access Memory (DRAM), embedded DRAM, and logic operation circuits. In system-on-chip (SOC) or system-on-integrated-circuit (SOIC) applications, different capacitors for different functional circuits must be integrated on the same chip to serve different purposes. For example, in mixed signal circuits, capacitors are used as decoupling capacitors and high frequency noise filters. For DRAM and embedded DRAM circuits, capacitors are used for memory, while for RF circuits capacitors are used in oscillators (oscillators) and phase-shift networks (phase-shift networks) for coupling and/or bypassing (bypass) purposes. For microprocessors, capacitors are used for decoupling. As the name implies, MIM capacitors comprise a sandwich structure of alternating metal and insulating layers. An exemplary MIM capacitor includes a bottom conductor plate layer, a middle conductor plate layer on the bottom conductor plate layer, and a top conductor plate layer on the middle conductor plate layer, each of which is insulated from adjacent conductor plate layers by an insulator layer. Because MIM capacitors are fabricated at the back end of line (BEOL) stage in order to have a large surface area, they can be embedded in a redistribution (redistribution) structure or a passivation (passivation) structure on an interconnect structure. MIM capacitors in IC designs do not necessarily have a uniform distribution in the passivation structure. Due to differences in materials, construction, and thermal expansion coefficients (thermal expansion coefficients), the uneven distribution of MIM structures in dielectric passivation structures can lead to uneven etch loading and stress around MIM structures and other conductive features. Non-uniform etch loading may lead to etch endpoint failure, while stress around MIM structures may lead to cracking (crack) and delamination (delamination).

Dummy MIM structures can be introduced into the isolation regions without MIM structures to provide a more uniform distribution of MIM structures (or similarly configured dummy MIM structures) in the passivation layer. However, the introduction of the dummy MIM structure is not always as simple. For example, a die (die) in a three-dimensional integrated circuit (3DIC) or a System On Integrated Circuit (SOIC) includes a through via (through via) that may extend through a passivation layer without electrically coupling to a MIM structure. These vias may not be evenly distributed and cause an obstruction to evenly insert the dummy MIM structures. As such, the through vias may prevent the dummy MIM structures from being uniformly distributed in the isolation regions without MIM structures, thereby at least partially defeating the purpose of the dummy MIM structures to exist at the outset. The present disclosure provides dummy MIM structures and methods for inserting dummy MIM structures to provide improved distribution of MIM structures or similar structures.

Fig. 1 shows a partial cross-sectional view of an IC device 100. The IC device 100 may be a semiconductor device die, a semiconductor device package (package), or a System On Integrated Circuit (SOIC) device. Depending on the context, the IC device 100 may represent an actual IC device or the design of the IC device 100. In the embodiment shown in fig. 1, the IC device 100 includes a first die 10 bonded (bond) to a second die 20. Attention is first turned to the first die 10. In some embodiments, the first die 10 includes a first substrate 12. The first substrate 12 includes circuitry fabricated thereon. These circuits may include passive and active microelectronic devices such as resistors, capacitors, inductors, diodes, p-type field effect transistors (PFETs), n-type field effect transistors (NFETs), Metal Oxide Semiconductor Field Effect Transistors (MOSFETs), Complementary Metal Oxide Semiconductor (CMOS) transistors, Bipolar Junction Transistors (BJTs), Laterally Diffused MOS (LDMOS) transistors, high voltage transistors, high frequency transistors, other suitable components, or combinations thereof. The first substrate 12 may also include an elemental semiconductor, a compound semiconductor, or an alloy semiconductor. Examples of elemental semiconductors include silicon or germanium. Examples of the compound semiconductor include silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, and/or indium antimonide. Examples of alloy semiconductors include silicon germanium (SiGe), GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP, or combinations thereof. In some embodiments, the first substrate 12 is a semiconductor-on-insulator (SOI) substrate, such as a silicon-on-insulator (SOI) substrate, a silicon germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. As shown in fig. 1, the first substrate 12 extends along an X-Y plane and has a normal (normal) direction along a Z direction. The first substrate 12 includes a first surface 12-1 and an opposing second surface 12-2. In some embodiments, circuitry in the first substrate 12 may be disposed adjacent to the first surface 12-1. A first bottom contact pad 160 may be disposed adjacent to the second surface 12-2 of the first substrate 12.

The IC device 100 also includes a first redistribution structure 14 (also referred to as a first interconnect structure 14) disposed on the first surface 12-1 of the first substrate 12. The first redistribution structure 14 includes various conductive elements, such as metal lines, contacts, and vias, to provide horizontal and vertical electrical routing. The metal lines are distributed in multiple metal layers, such as a first metal layer (e.g., M1 layer), a second metal layer (e.g., M2 layer), …, and the first conductive feature 130. A first conductive feature 130 is disposed on a top surface of the first redistribution structure 14 remote from the first substrate 12. In some embodiments, the first conductive feature 130 may include copper, aluminum, alloys thereof, or other conductive materials. In one embodiment, the first conductive feature 130 may comprise an alloy comprising about 95% aluminum and about 5% copper to provide adhesion to an overlying (overlapping) first passivation structure 16 (described below), and may be referred to as a first aluminum (Al) pad 130. The conductive elements of the first redistribution structure 14 may provide electrical connections to (to) circuitry in the first substrate 12. The first redistribution structure 14 also includes a plurality of dielectric layers to provide electrical isolation between the various conductive elements and thereby prevent electrical shorting.

The first die 10 further includes a first passivation structure 16 disposed on the first redistribution structure 14. The first passivation structure 16 may include one or more silicon nitride layers, one or more silicon carbonitride layers, one or more Undoped Silica Glass (USG) layers, one or more silicon oxide layers deposited using High Density Plasma Chemical Vapor Deposition (HDPCVD), and one or more polymer layers. The polymer layer may comprise polyimide (polyimide). The first MIM structure 120 is embedded in the first passivation structure 16. In some examples, the first passivation structure 16 includes a silicon nitride layer (or a silicon carbonitride layer) disposed on the first redistribution structure 14, and a USG layer disposed on the silicon nitride layer (or the silicon carbonitride layer). The first MIM structure 120 is disposed on the USG layer and is fully covered by another USG layer (blanket cover). In some embodiments, the first passivation structure 16 further includes one or more polymeric passivation layers disposed on the USG layer overlying the first MIM structure 120. Although only the first MIM structure 120 is shown in fig. 1 for simplicity, the first die 10 includes a plurality of MIM structures similar to the first MIM structure 120.

The first MIM structure 120 can include two or more conductor plate layers. In one embodiment, the first MIM structure 120 comprises three conductor plate layers separated by insulator layers. In this embodiment, first MIM structure 120 includes bottom conductor plate layer 1201, middle conductor plate layer 1202 situated on bottom conductor plate layer 1201, and top conductor plate layer 1203 situated on middle conductor plate layer 1202. It should be noted that bottom conductor plate layer 1201 is first formed on the workpiece (workbench), followed by middle conductor plate layer 1202 and top conductor plate layer 1203. If the workpiece is thereafter flipped, the bottom conductor plate layer 1201 may appear to be on top of the middle conductor plate layer 1202. In some embodiments, each of bottom conductor plate layer 1201, middle conductor plate layer 1202, and top conductor plate layer 1203 may be formed of a transition metal or transition metal nitride, such as titanium (Ti), tantalum (Ta), titanium nitride (TiN), or tantalum nitride (TaN). Transition metals or transition metal nitrides may provide better prevention against electro-migration (electro-migration) and oxygen diffusion (oxygen diffusion) than copper or aluminum. Each of bottom conductor plate layer 1201, middle conductor plate layer 1202, and top conductor plate layer 1203 may have a thickness between about 40nm and about 80 nm. Each insulator layer between bottom conductor plate layer 1201 and middle conductor plate layer 1202, and between middle conductor plate layer 1202 and top conductor plate layer 1203, may be a single thin layer or multiple thin layers formed of silicon oxide, zirconium oxide, hafnium oxide, aluminum oxide, tantalum oxide, titanium oxide, or combinations thereof. As shown in fig. 1, the first die 10 also includes a first top contact pad 110, the first top contact pad 110 being disposed on a top surface of the first passivation structure 16 remote from the first redistribution structure 14. One or more first contact vias 140 may extend through a portion of the first MIM structure 120 between the first top contact pad 110 and the first conductive feature 130. The one or more first contact vias 140 provide electrical connection to one or more conductor plate layers in the (to) first MIM structure 120.

The first top contact pad 110 may be formed of a metal or metal alloy, such as copper, cobalt, nickel, aluminum, tungsten, titanium, or a combination thereof. The first die 10 further includes a first through via 150, the first through via 150 extending through the first passivation structure 16, the first redistribution structure 14, and the first substrate 12 to electrically couple to the first top contact pad 110 and the first bottom contact pad 160. The first through via 150 may include a metal filled layer of a barrier liner (line). The metal fill layer may comprise a metal or metal alloy, such as copper, cobalt, nickel, aluminum, tungsten, titanium, or combinations thereof. The barrier layer may include a transition metal nitride, such as titanium nitride or tantalum nitride. Although only the first through via 150 is shown in fig. 1 for simplicity of illustration, the first die 10 includes a plurality of vias similar to the first through via 150.

The IC device 100 also includes a second die 20 bonded (bond) to the first die 10. For illustrative purposes, the second grains 20 in fig. 1 include similar features to the first grains 10. For example, the second die 20 includes a second substrate 22 similar to the first substrate 12; a second redistribution layer 24 similar to the first redistribution structure 14; a second passivation structure 26 similar to the first passivation structure 16; a second MIM structure 122 similar to the first MIM structure 120; a second conductive feature 132 similar to the first conductive feature 130; a second through via 152 similar to the first through via 150; the first contact via 140 is similar to the second contact via 142; a second top contact pad 112 similar to the first top contact pad 110; and a second bottom contact pad 162 similar to the first bottom contact pad 160. As shown in fig. 1, the first die 10 and the second die 20 are bonded together such that the first bottom contact pad 160 is in direct contact with the second bottom contact pad 162. Detailed descriptions of similar features in the second die 20 are omitted.

Still referring to fig. 1. Since the first MIM structure 120 is arranged at one side of the first passivation structure 16, a first isolation region 30 without any MIM structure is obtained. The first isolation region 30 is split (divot) by a first through via 150 extending through the first passivation structure 16, the first through via 150 not touching (clear) the first MIM structure 120. Similarly, the arrangement of the second MIM structure 122 in the second passivation structure 26 is such that the second isolation region 32 is free of any MIM structure. In a similar manner, the second isolation region 32 is split by a second through via 152 extending through the second passivation structure 26. When the dummy MIM structures are disposed away from the through vias, the dummy MIM structures may not have sufficient density to prevent etching load and provide satisfactory mechanical strength.

The present disclosure provides a method for inserting dummy MIM structures in isolation regions, for example in first isolation region 30 and second isolation region 32. The dummy MIM structure according to the present disclosure includes an opening to accommodate a through via similar to the first through via 150 and the second through via 152.

Fig. 2 is a flow chart illustrating a method 200 for fabricating a device according to aspects of the present disclosure. The method 200 is merely an example and is not intended to limit the present disclosure to what is explicitly shown in the method 200. Other operations may be provided before, during, and after the method 200, and some of the operations described herein may be replaced, eliminated, or removed for other embodiments of the method 200. For simplicity of illustration, not all operations are described in detail herein. The method 200 is described below in conjunction with fig. 3-5, 6A, 6B, 7A, 7B, 8A, 8B, 9A-9D, and 10.

The method of the present disclosure, such as the method 200 in fig. 2, may be performed at any point in time between the generation of the IC design layout and the actual fabrication of the photomask. Referring now to fig. 3, fig. 3 illustrates a simplified block diagram of an Integrated Circuit (IC) manufacturing system 300 and associated IC manufacturing flow that may benefit from various aspects of the present disclosure. IC manufacturing system 300 includes a plurality of entities, such as a design studio 302, a mask studio 304, and an IC manufacturer 306, i.e., a fabrication area (fab), that interact with each other in the design, development, and fabrication cycles and/or services associated with fabricating Integrated Circuit (IC) devices 160. The entities are linked by a communication network, which may be a single network or a variety of different networks, such as an intranet and the internet, and may include wired and/or wireless communication channels. Each entity may interact with other entities and may provide services to and/or receive services from other entities. One or more of the design studio 302, the reticle studio 304, and the IC fab 306 may have the same owner and may co-exist in a common facility (common facility) and use common resources.

In various embodiments, a design studio 302, which may include one or more design teams, generates an IC design layout (i.e., design). The IC design layout may include various geometric patterns (patterns) designed for the fabrication of the IC device 100. For example, the geometric pattern may correspond to a pattern of thin layers of metal, oxide, or semiconductor that make up various components of the IC device 100 to be fabricated. The various thin layers are combined to form various features of the IC device 100. For example, various portions of an IC design layout may include features such as active regions (active regions), gate electrodes, source and drain regions, metal lines or vias for metal interconnects, openings for bond pads (bond pads), and other features formed in a semiconductor substrate (e.g., a silicon wafer) and various layers of materials disposed thereon as are known in the art. In various examples, the design studio 302 executes a design program to form the IC design layout 122. Design programs may include logic designs, physical designs, and/or placement and routing. The IC design layout may be presented in one or more data files having information about the geometric patterns to be used in manufacturing the IC device 100. In some examples, the IC design layout 122 may be represented in a graphic database system II (GDSII) file format, or a DF II file format.

In some embodiments, the design studio 302 may transfer the IC design layout to the reticle studio 304, for example, via the network connection described above. The mask shop 304 may then use the IC design layout to manufacture one or more masks to be used to manufacture the various layers of the IC device 100 according to the IC design layout. In various examples, the reticle studio 304 performs reticle data preparation, wherein the IC design layout is converted into a form that can be physically written by a reticle writer (mask writer), wherein the data prepared by the reticle data preparation is modified to conform to a particular reticle writer and/or reticle fab and then manufactured. In the example of FIG. 3, mask data preparation and mask fabrication are depicted as individual elements, however, in some embodiments, mask data preparation 132 and mask fabrication 144 may be collectively referred to as mask preparation.

After mask data preparation and during mask fabrication, a mask or set of masks may be fabricated based on the modified IC design layout. For example, an electron beam (e-beam) writer or a multiple electron beam mechanism is used to pattern a mask (reticle) based on the modified IC design layout. The mask can be formed using various techniques. In one embodiment, the mask is formed using binary technology (binary technology). In some embodiments, the mask pattern includes opaque (opaque) regions and transparent regions. A radiation beam, such as an Ultraviolet (UV) beam, is used to expose a layer of radiation-sensitive material (e.g., photoresist) applied to a wafer, which is blocked by an opaque region and passes through a transparent region. In one example, a binary reticle includes a transparent substrate (e.g., fused quartz) and an opaque material (e.g., chrome) applied to opaque regions of the reticle. In some examples, the mask is formed using a phase shift technique. In a Phase Shift Mask (PSM), various features in a pattern formed on the mask are configured to have a phase difference (phase difference) configured in advance to enhance image resolution and imaging quality. In various embodiments, the phase shift mask may be an attenuated (attenuated) PSM or an alternating (alternating) PSM.

In some embodiments, an IC fab 306 (e.g., a semiconductor foundry (foundry)) uses a mask (or masks) manufactured by the mask shop 304 to transfer one or more mask patterns onto a wafer and thereby manufacture IC devices on the wafer. IC fab 306 may include IC manufacturing facilities, which may include countless manufacturing facilities for manufacturing a variety of different IC products. For example, the IC fab 306 may include a first fabrication facility (i.e., front-end-of-line (FEOL)) for front-end fabrication of a plurality of IC products, while a second fabrication facility may provide back-end-of-line (BEOL) for interconnection and packaging of the IC products, and a third fabrication facility may provide other services (e.g., research and development) for wafer foundry. In some embodiments, the method 200 may be performed after the IC design layout is generated by the design studio 302 but before the reticle fabrication by the reticle studio 304. In some embodiments, the method 200 may be performed during mask data preparation using a computer system.

Referring now to fig. 1 and 2, a method 200 includes a block 202, where the block 202 receives a design (i.e., an IC design layout). The design may be a GDSII in DFII format and may include features in the thin layers that make up a semiconductor device, such as the representative IC device 100 of fig. 1. In some embodiments, the design may include only features in a thin layer that forms a part of the IC device 100, such as the first die 10, the second die 20, the first passivation structure 16, or the second passivation structure 26. For example, a design may include multiple MIM structures (similar to the first MIM structure 120 and the second MIM structure 122), and multiple vias (e.g., the first through via 150 and the second through via 152) that do not pass through the multiple MIM structures. More specifically, the design may include information regarding the coordinates, dimensions, and shapes of the plurality of MIM structures and the plurality of vias.

Referring to fig. 1, 2, 4, and 5, the method 200 includes a block 204, where in the block 204, an isolation region is identified based on a distribution of a plurality of MIM structures. Multiple MIM junctions as described above in connection with FIG. 1Structures, such as the first MIM structure 120 and the second MIM structure 122, may not be evenly distributed across the device in a design. For example, the first passivation structure 16 includes a first isolation region 30, and the second passivation structure 26 includes a second isolation region 32. By using a computer system capable of reading and analyzing the design, the isolation regions in the same thin layer of multiple MIM structures can be identified based on the distribution of the multiple MIM structures shown in figure 4. In some embodiments, as shown in FIG. 5, the isolated region template 400 may be stored in a database accessible by a computer system. The isolation region template 400 may be square or rectangular in shape and may have a predetermined area, which may be between about 0.001 times and about 1 times the average area of the plurality of MIM structures. In some other embodiments, the isolation region template 400 may have a diamond (rhombus) shape, a diamond shape, or a stair-step (standing-like) shape. In some cases, the isolation region template 400 may have an area between about 1 μm²And about 250000 μm²In the meantime. In these embodiments, when the isolation region template 400 is lined (fit) with a region without any MIM structure, the region may be identified as a portion of the isolation region. Conversely, when the isolation region template 400 is unlined with a region without any MIM structure, the region can still be excluded from the isolation region.

Referring to fig. 2, 6A, and 6B, method 200 includes block 206, determining a plurality of dummy MIM shapes (e.g., rectangular dummy MIM shapes 400A or square dummy MIM shapes 400B) in the isolation regions, block 206. For computational simplicity, a plurality of virtual MIM shapes (rectangular virtual MIM shape 400A/square virtual MIM shape 400B) can be stored in a database accessible to a computer system for performing method 200. In some embodiments, the dummy MIM shape (rectangular dummy MIM shape 400A/square dummy MIM shape 400B) can be rectangular (as shown in 400A of fig. 6A), square (as shown in 400B of fig. 6B), diamond, or polygonal, or can be a staircase shape. In some embodiments, the computer system for performing the method 200 operates to select a single virtual MIM shape and line as many virtual MIM shapes as possible in the identified isolation regions. In block 206, the computer system ensures that each of the plurality of dummy MIM shapes (e.g., rectangular dummy MIM shape 400A or square dummy MIM shape 400B) is separated (e.g., separated by a minimum spacing) from adjacent MIM structures. The minimum spacing may be determined based on process parameters and a desired process margin (margin). A minimum spacing is required to ensure that the dummy MIM shapes are isolated from the MIM structure.

It should be noted that, at least in some embodiments, the operations in

blocks

204 and 206 do not take into account the size and shape of the plurality of vias (e.g., the first through via 150 and the second through via 152 in fig. 1). That is, the operations in

blocks

204 and 206 do not treat the plurality of vias as obstructive features when placing the plurality of dummy MIM structures. As will be described below, rather than avoiding multiple vias, the methods of the present disclosure utilize openings to accommodate the multiple vias as any of the multiple vias pass through the virtual MIM structure.

Referring to fig. 2, 7A and 7B, the method 200 includes identifying a subset of the plurality of vias (e.g., the first through via 150 or the second through via 152 of fig. 1) that overlap the plurality of rectangular dummy MIM shapes 400A/square dummy MIM shapes 400B (collectively referred to as dummy MIM shapes 400A/400B) in block 208. In some embodiments shown in fig. 7A and 7B, not all of the plurality of vias (e.g., first through via 150 or second through via 152 shown in fig. 1) overlap with rectangular dummy MIM shape 400A (also referred to as dummy MIM shape 400A) or square dummy MIM shape 400B (also referred to as dummy MIM shape 400B). A computer system for performing the operations of method 200 may compare a thin layer of a design including a

virtual MIM shape

400A or 400B to a thin layer of a design including a plurality of vias to identify a subset of the plurality of vias that overlap the plurality of virtual MIM shapes.

Referring to fig. 2, 8A and 8B, the method 200 includes a block 210, where a plurality of opening shapes for a subset of the plurality of vias is determined in the block 210. In some embodiments shown in fig. 8A, a first opening shape 500A that overlaps each of a plurality of rectangular dummy MIM shapes 400A is determined. That is, each of the plurality of rectangular dummy MIM shapes 400A is fitted with a first opening shape 500A. Similarly, in some embodiments shown in fig. 8B, a second opening shape 500B that overlaps each of the plurality of square dummy MIM shapes 400B is determined. Each of the plurality of square dummy MIM shapes 400B is fitted with a second opening shape 500B. The operations of block 210 continue until all subsets of the plurality of vias overlap the plurality of opening shapes. In some embodiments shown in fig. 8A and 8B, each of the plurality of opening shapes is annular in shape (circular), and the operation at block 210 is performed such that a region center (area center) or a center of gravity (weight center) of each of the plurality of opening shapes is aligned with a region center or a center of gravity of each of the plurality of vias. In some cases not specifically shown in fig. 8A and 8B, a portion of the plurality of opening shapes may not fall exactly on the plurality of dummy MIM shapes. In these embodiments where each of the plurality of opening shapes is annular, each of the plurality of opening shapes is larger than the via and overlaps in area on the X-Y plane. In other words, the cross-sectional area of the opening is larger than the cross-sectional area of the via hole along the Z direction perpendicular to the substrate or the die.

Referring to fig. 2 and 9A-9D, the method 200 includes a block 212 in which a plurality of opening shapes are superimposed (super-position) on a plurality of dummy MIM shapes to obtain a plurality of final dummy MIM structures, at block 212. After determining a plurality of virtual MIM shapes based on the distribution of the plurality of MIM structures in block 208 and fitting the plurality of opening shapes to the subset of the plurality of vias in block 210, the plurality of opening shapes are superimposed on the plurality of virtual MIM shapes in block 212 to obtain a final virtual MIM structure. Examples of such overlap are shown in fig. 9A-9D. Referring to fig. 9A, a first opening shape 500A is superimposed on a rectangular dummy MIM shape 400A to obtain a final dummy MIM structure (similar to the first dummy MIM structure 170 or the second dummy MIM structure 172 of fig. 11). Referring to fig. 9B, a second opening shape 500B is superimposed on the square dummy MIM shape 400B to obtain a final dummy MIM structure (similar to the first dummy MIM structure 170 or the second dummy MIM structure 172 in fig. 11). Referring to fig. 9C, a third opening shape 500C is superimposed on the diamond or diamond-shaped dummy MIM shape 400C to form a final dummy MIM structure (similar to the first dummy MIM structure 170 or the second dummy MIM structure 172 in fig. 11). Referring to fig. 9D, a fourth opening shape 500D is superimposed on the stepped dummy MIM shape 400D to obtain a final dummy MIM structure (similar to the first dummy MIM structure 170 or the second dummy MIM structure 172 in fig. 11). Each opening shape in fig. 9A-9D represents an opening in a respective MIM structure for receiving one of a plurality of vias.

Referring to fig. 2, the method 200 includes a block 214 in which a plurality of final dummy MIM structures are inserted into the design to obtain a modified design. In block 214, the final dummy MIM structure representatively shown in fig. 9A through 9D is inserted into the design to obtain a modified design. Refer to fig. 3. With respect to the IC fabrication flow, the final dummy MIM structure of fig. 9A-9D may be inserted into the design received from the design chamber 302 (i.e., the IC design layout) to obtain a modified design.

To ensure a satisfactory process window and avoid undesired capacitance, each of the first opening shape 500A, the second opening shape 500B, the third opening shape 500C, and the fourth opening shape 500D is substantially coaxial with the first through via 150 (or the second through via 152, as the case may be) and is separated from the first through via 150 (or the second through via 152, as the case may be) by a spacing S. In some cases, the spacing S may be between about 1 μm and about 2 μm. To ensure uniform stress distribution and prevent crack propagation, the edges of the first, second, third, and fourth opening shapes 500A, 500B, 500C, 500D are separated from the edges of the first dummy MIM structure 170 (or the second dummy MIM structure 172, as the case may be) by a minimum margin M. In some cases, the minimum margin M may be between about 1 μ M and about 2 μ M. It can be observed that when the pitch S is smaller than 1 μm, the process window may be reduced, since overlay error may cause the first through via 150 (or the second through via 152) to contact the first dummy MIM structure 170 (or the second dummy MIM structure 172). When the spacing S and the minimum margin M are greater than 2 μ M, the overall size of the first dummy MIM structure 170 (or the second dummy MIM structure 172) may be too large, such that the efficiency of inserting the isolation region is reduced.

The dummy MIM structures may have different arrangements of dummy conductor plates. For illustration purposes, cross-sectional views of the dummy MIM structure in fig. 9A along line I-I' are shown in fig. 10A, 10B, and 10C. As shown in fig. 10A, 10B, and 10C, first dummy MIM structure 170 (or second dummy MIM structure 172, as the case may be) includes a bottom dummy conductor plate layer 1701, an intermediate dummy conductor plate layer 1702 on bottom dummy conductor plate layer 1701, and a top dummy conductor plate layer 1703 on intermediate dummy conductor plate layer 1702. Of the three dummy conductor plate layers, a bottom dummy conductor plate layer 1701 is first formed, and an intermediate dummy conductor plate layer 1702 and a top dummy conductor plate layer 1703 are sequentially formed on the bottom dummy conductor plate layer 1701. In some embodiments, similar to the conductor plate layers in the first MIM structure 120 and the second MIM structure 122, the bottom dummy conductor plate layer 1701, the middle dummy conductor plate layer 1702, and the top dummy conductor plate layer 1703 are insulated from each other by at least one insulator layer. Depending on the orientation of the first die 10 and the second die 20, the bottom dummy conductor plate layer 1701 may appear on top for the first dummy MIM structure 170 or may descend to the bottom for the second dummy MIM structure 172. The different orientations are shown in fig. 11 (described below).

In some embodiments shown in fig. 10A, the bottom dummy conductor plate layer 1701, the middle dummy conductor plate layer 1702, and the top dummy conductor plate layer 1703 are coextensive (coextensive), and the first opening shape 500A is replicated in each dummy conductor plate layer. In some embodiments shown in fig. 10B, the first opening shape 500A is accommodated in the bottom dummy conductor plate layer 1701, but the openings in the middle dummy conductor plate layer 1702 and the top dummy conductor plate layer 1703 are larger than the first opening shape 500A. In some embodiments shown in fig. 10C, prior to depositing intermediate dummy conductor plate layer 1702, bottom dummy conductor plate layer 1701 is patterned such that intermediate dummy conductor plate layer 1702 may extend onto sidewalls of bottom dummy conductor plate layer 1701. In the embodiment shown in fig. 10C, the first opening shape 500A is defined by the pattern in the middle dummy conductor plate layer 1702. A similar arrangement of dummy conductor plate layers may be implemented in the embodiments of the dummy MIM structures shown in fig. 9B, 9C, and 9D.

Referring to fig. 2 and 11, the method 200 includes a block 216 where the IC device 100' is fabricated based on the modified design in the block 216. In some cases, the reticle studio 304 may manufacture the reticle based on the modified design obtained from block 214 and transmit the reticle to the IC manufacturer 306. Next, the IC manufacturer 306 may manufacture the IC device 100' shown in fig. 11. At this point, the dummy MIM structure inserted into the modified design is implemented in the IC device 100'. Compared to the IC arrangement 100 of fig. 1, the IC arrangement 100' additionally comprises a first dummy MIM structure 170 located in the first isolation region 30 of fig. 1 and a second dummy MIM structure 172 located in the second isolation region 32 of fig. 1. With respect to the first die 10 in fig. 11, the first dummy MIM structure 170 is one of a plurality of dummy MIM structures disposed in an isolation region in the IC device 100'. With respect to the first die 20 in fig. 11, the second dummy MIM structure 172 is one of a plurality of dummy MIM structures disposed in an isolation region in the IC device 100'. The first dummy MIM structure 170 comprises a first opening 180 to accommodate the first through via 150. The first opening 180 is larger than the first through via 150 with respect to the X-Y cross-sectional plane such that the first dummy MIM structure 170 is separated from the first through via 150. Similarly, the second dummy MIM structure 172 includes a second opening 182 to accommodate the second through via 152. The second opening 182 is larger than the second through via 152 in terms of the X-Y cross-sectional plane such that the second dummy MIM structure 172 is separated from the second through via 152.

The first dummy MIM structure 170 and the second dummy MIM structure 172 are shown in fig. 11 as having a dummy conductor plate layer configuration similar to that shown in fig. 10A. In other embodiments, they may have the dummy conductor plate layer arrangement shown in FIG. 10B or FIG. 10C. For the avoidance of doubt, the first dummy MIM structure 170 and the second dummy MIM structure 172 may have the shape, structure and opening shown in fig. 9A, 9B, 9C or 9D. For example, the first opening 180 and the second opening 182 may correspond to the first opening shape 500A in fig. 9A, the second opening shape 500B in fig. 9B, the third opening shape 500C in fig. 9C, or the fourth opening shape 500D in fig. 9D.

The dummy MIM structures of the present disclosure include structures that are substantially equivalent to functional MIM structures. Still referring to fig. 11. As described above, first MIM structure 120 includes bottom conductor plate layer 1201, middle conductor plate layer 1202, and top conductor plate layer 1203. In some embodiments, each of bottom conductor plate layer 1201, middle conductor plate layer 1202, and top conductor plate layer 1203 may be formed of a transition metal or transition metal nitride, such as titanium (Ti), tantalum (Ta), titanium nitride (TiN), or tantalum nitride (TaN). In some embodiments shown in fig. 11, first dummy MIM structure 170 includes a bottom dummy conductor plate layer 1701, an intermediate dummy conductor plate layer 1702 on bottom dummy conductor plate layer 1701, and a top dummy conductor plate layer 1703 on intermediate dummy conductor plate layer 1702. Each of the bottom dummy conductor plate layer 1701, the middle dummy conductor plate layer 1702, and the top dummy conductor plate layer 1703 may be formed of a transition metal or a transition metal nitride, such as titanium (Ti), tantalum (Ta), titanium nitride (TiN), or tantalum nitride (TaN). Bottom conductor plate layer 1201 and bottom dummy conductor plate layer 1701 may be formed simultaneously in the same process step. In a similar manner, middle conductor plate layer 1202 and middle dummy conductor plate layer 1702 may be formed simultaneously, and top conductor plate layer 1203 and top dummy conductor plate layer 1703 may be formed simultaneously. In some cases, at least a portion of bottom conductor plate layer 1201 may be coplanar (coplaner) with at least a portion of bottom dummy conductor plate layer 1701; at least a portion of the middle conductor plate layer 1202 may be coplanar with at least a portion of the middle dummy conductor plate layer 1702; and at least a portion of top conductor plate layer 1203 may be coplanar with at least a portion of top dummy conductor plate layer 1703. Similar to the first MIM structure 120, the bottom dummy conductor plate layer 1701, the middle dummy conductor plate layer 1702, and the top dummy conductor plate layer 1703 are insulated from each other by one or more insulator layers, respectively. The same can be said for the second MIM structure 122 and the second dummy MIM structure 172. The second MIM structure 122 and the second dummy MIM structure 172 may have similar compositions formed in the same process step. The dummy conductor plate layers in the second dummy MIM structure 172 are also insulated from each other by one or more insulator layers. Unlike the functional first and

second MIM structures

120 and 122, the first and second

dummy MIM structures

170 and 172 are electrically floating. That is, the first dummy MIM structure 170 and the second dummy MIM structure 172 are not electrically coupled to any functional structures in the IC device 100'.

Based on the above discussion, it can be seen that the present disclosure provides advantages over conventional methods and apparatus. However, it is to be understood that other embodiments may provide additional advantages, and that not all advantages need be disclosed herein, and that no particular advantage is required for all embodiments. Among other advantages, the method of the present disclosure allows for the insertion of dummy MIM structures around through vias to provide improved distribution of MIM structures or dummy MIM structures, thereby preventing uneven etch loading or cracks around MIM structures. Another advantage is that the method of the present disclosure contemplates the presence of through vias that do not interfere with the insertion of the dummy MIM structure.

Accordingly, the present disclosure provides an IC device. The IC device includes a substrate including a first surface and a second surface opposite the first surface, a redistribution layer disposed on the first surface and including conductive features, a passivation structure disposed on the redistribution layer, a metal-insulator-metal (MIM) capacitor embedded in the passivation structure, a dummy MIM feature embedded in the passivation structure and including an opening, a top contact pad on the passivation structure, a contact via extending between the conductive feature and the top contact pad, and a through via extending through the passivation structure and the substrate. The dummy MIM feature is separated from the MIM capacitor and the through via extends through the opening of the dummy MIM feature and does not contact the dummy MIM feature.

In some embodiments, the conductive feature comprises aluminum. In some embodiments, a MIM capacitor includes a first bottom conductor plate, a first middle conductor plate on the first bottom conductor plate, and a first top conductor plate on the first middle conductor plate. In some embodiments, the dummy MIM feature includes a second bottom conductor plate, a second middle conductor plate on the second bottom conductor plate, and a second top conductor plate on the second middle conductor plate. In some embodiments, the first bottom conductor plate is coplanar with the second bottom conductor plate. In some embodiments, the dummy MIM feature is electrically floating. In some embodiments, the opening is annular. In some embodiments, the dummy MIM features include a square, a rectangle, or a stair-step shape when viewed from a direction perpendicular to the substrate. In some embodiments, the IC device further includes a bottom contact pad on the second surface of the substrate, wherein the through via extends between and is electrically coupled to the top contact pad and the bottom contact pad.

The present disclosure also provides a method of manufacturing an integrated circuit device. The method includes receiving a design including a plurality of metal-insulator-metal (MIM) structures and a plurality of vias that do not extend through the MIM structures, determining a plurality of dummy MIM shapes, identifying a subset of the vias that overlap the dummy MIM shapes, determining a plurality of opening shapes located on the subset of vias, superimposing the dummy MIM shapes and the opening shapes to obtain a plurality of final dummy MIM structures, and inserting the final dummy MIM structures into the design to obtain a modified design.

In some embodiments, each of the virtual MIM shapes comprises a square, a rectangle, or a step. In some embodiments, each of the above opening shapes comprises a ring shape. In some embodiments, the determination of the virtual MIM shape is based on a distribution of the MIM structures. In some embodiments, each of the MIM structures and each of the final dummy MIM structures includes a bottom conductor plate, a middle conductor plate on the bottom conductor plate, and a top conductor plate on the middle conductor plate. In some embodiments, the method further comprises fabricating an integrated circuit device based on the modified design. In some embodiments, the fabrication of the integrated circuit device includes simultaneously forming the MIM structure and the final dummy MIM structure.

The present disclosure further provides a method of manufacturing an integrated circuit device. The method includes receiving a design including a substrate, a redistribution layer disposed on the substrate and including a conductive feature, a passivation structure disposed on the redistribution layer, a plurality of metal-insulator-metal (MIM) capacitors embedded in the passivation structure, and a plurality of through vias extending through the passivation structure and the substrate, the through vias being separated from the MIM capacitors. The method further includes determining a plurality of dummy MIM shapes based on a distribution of the MIM capacitor structures in the passivation structure, identifying a subset of the through vias that overlap the dummy MIM shapes, determining a plurality of opening shapes on the subset of the through vias, superimposing the dummy MIM shapes and the opening shapes to obtain a plurality of final dummy MIM structures, and inserting the final dummy MIM structures into the design to obtain a modified design.

In some embodiments, each of the opening shapes is larger than a cross-sectional area of each of the subsets of the through vias along a direction perpendicular to the substrate. In some embodiments, each of the dummy MIM shapes comprises a square, a rectangle, or a step, and each of the opening shapes comprises a ring. In some embodiments, the method may further include fabricating an integrated circuit device based on the modified design.

The foregoing outlines features of various embodiments or examples so that those skilled in the art may better understand the disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments or examples introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims

1. An integrated circuit device, comprising:

a substrate including a first surface and a second surface opposite to the first surface;

a redistribution layer disposed on the first surface and including a conductive feature;

a passivation structure disposed on the redistribution layer;

a metal-insulator-metal capacitor embedded in the passivation structure;

a dummy metal-insulator-metal feature embedded in the passivation structure and including an opening;

a top contact pad on the passivation structure;

a contact via extending between the conductive feature and the top contact pad; and

a through via extending through the passivation structure and the substrate;

wherein said dummy metal-insulator-metal feature is separate from said metal-insulator-metal capacitor;

wherein the through via extends through the opening of the dummy metal-insulator-metal feature without contacting the dummy metal-insulator-metal feature.