CN112582340A - Method for forming metal cobalt interconnection layer and contact hole layer - Google Patents
Method for forming metal cobalt interconnection layer and contact hole layer Download PDFInfo
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- CN112582340A CN112582340A CN202011479297.6A CN202011479297A CN112582340A CN 112582340 A CN112582340 A CN 112582340A CN 202011479297 A CN202011479297 A CN 202011479297A CN 112582340 A CN112582340 A CN 112582340A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
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Abstract
A method for forming a metal cobalt interconnection layer and a contact hole layer comprises providing a substrate containing an interconnection line layer structure, and forming a dielectric layer on the substrate; carrying out photoetching process on the dielectric layer to form a through hole layer; carrying out tungsten deposition on the through hole layer by adopting a selective tungsten deposition process so that metal tungsten fills the through holes in the through hole layer to form first parts of the through holes; depositing a TIN bonding layer by adopting an ALD (atomic layer deposition) or CVD (chemical vapor deposition) process, and filling metal tungsten into the through holes in the through hole layer by adopting a CVD (chemical vapor deposition) tungsten process so as to form second parts of the through holes; and depositing a TIN bonding layer by adopting an ALD (atomic layer deposition) or CVD (chemical vapor deposition) process, filling the through holes in the through hole layer with metal tungsten by adopting a CVD (chemical vapor deposition) tungsten process to form second parts of the through holes, and removing the TIN bonding layer by using a dry etching or wet etching process. The invention partially fills the through holes in the through hole layer by using a selective tungsten deposition process, and blocks the permeation of CMP grinding fluid by using a subsequently deposited TIN bonding layer, thereby solving the problem of cobalt loss of nodes of 7nm and below.
Description
Technical Field
The invention relates to the technical field of semiconductor integrated circuit processes, in particular to a method for forming a metal cobalt interconnection layer and a contact hole layer, which is used for solving cobalt loss of the interconnection layer in a node manufacturing process of 7nm or below.
Background
With the shrinking of the size of the semiconductor device and the shrinking of the contact hole or the contact groove CD, the RS (Sheet Resistance) is increased, and the contribution of the bonding layer (Ti/TiN) to the RS is more and more obvious. At present, a plurality of international research institutes have carried out research on selective tungsten deposition technology (selective W deposition) without an adhesive layer, and particularly, the selective W deposition technology is applied to filling of a Via layer Via 0(V0) of a technical node of 10nm and below, and certain results have been achieved, because 7nm starts to have higher requirements on RS of a contact groove in an interconnection layer (M0), the traditional tungsten metal is generally replaced by cobalt metal with lower RS.
In the forming method of the metal cobalt interconnection layer and the contact hole layer in the prior art, the via hole layer adopts a selective metal tungsten deposition process without an adhesive layer.
However, it is clear to those skilled in the art that if the via layer is formed by a selective metal tungsten deposition process without an adhesive layer, the adhesion between the via layer and the silicon oxide/silicon nitride dielectric layer on the sidewall is not good, which may cause the problem that the slurry of CMP corrodes the active cobalt in the lower layer (interconnect layer) through the interface during the subsequent process of chemical mechanical polishing (tungsten polishing W CMP) of the tungsten in the via layer, resulting in cobalt loss.
Disclosure of Invention
The invention aims to provide a method for forming a metal cobalt interconnection layer and a contact hole layer, which is used for solving the cobalt deficiency of nodes with the thickness of 7nm and below.
In order to achieve the purpose, the technical scheme of the invention is as follows:
a method for forming a metal cobalt interconnection layer and a contact hole layer comprises the following steps:
step S1: providing a substrate containing an interconnection layer structure, and forming a dielectric layer on the substrate, wherein the interconnection layer structure comprises interconnection material including metal cobalt;
step S2: carrying out a standard photoetching process on the dielectric layer to form a patterned through hole layer; wherein the through hole in the through hole layer penetrates through the dielectric layer;
step S3: carrying out tungsten deposition on the through hole layer by adopting a selective tungsten deposition process so as to enable metal tungsten to fill the through holes in the through hole layer to form first parts of the through holes; the upper surface of the first part of the through hole is lower than the upper surface of the dielectric layer;
step S4: depositing a TIN bonding layer by using an ALD (atomic layer deposition) or CVD (chemical vapor deposition) process, and filling metal tungsten in the through hole layer by using a CVD (chemical vapor deposition) tungsten process to form a second part of the through hole; wherein the bottom of the second portion of the via hole is higher than the upper surface of the TIN bonding layer;
step S5: performing a tungsten chemical mechanical planarization process on the through hole layer, and removing a second part of the through hole to stop on the TIN bonding layer on the upper surface of the first part of the through hole;
step S6: and removing the TIN bonding layer by adopting a dry etching or wet etching process.
Further, the dielectric layer sequentially comprises a contact hole etching stop layer and a silicon oxide layer from bottom to top.
Furthermore, the contact hole etching stop layer is made of silicon nitride or nitrogen-doped silicon carbide.
Further, the wet etching process is an SPM process.
Further, the step S4 further includes performing a compressive stress process on the surface of the via layer to increase the compressive stress between the dielectric in the dielectric layer and the metal tungsten and the sidewall in the via.
Further, the compressive stress process is a plasma bias bombardment process.
Further, the plasma bias bombardment process is a heavy ion plasma bias bombardment process.
Further, the heavy ions are Ar ions.
Further, the dielectric layer sequentially includes a contact hole etching stop layer and a flow type chemical vapor deposition silicon oxide layer from bottom to top, and the step S4 further includes performing a water vapor annealing process on the flow type chemical vapor deposition silicon oxide layer to further increase the compressive stress between the dielectric in the dielectric layer and the sidewall of the through hole tungsten plug.
Further, the interconnection layer structure is an interconnection layer structure M0; the via layer is via layer V0.
According to the technical scheme, after the through hole layer is etched to form the through hole, tungsten is partially filled in the through hole of the through hole layer by using a selective tungsten deposition process, then a TIN bonding layer and tungsten are deposited to fill the through hole layer, and then the TIN bonding layer and the tungsten are ground to the TIN material on the tungsten metal selectively deposited in the through hole layer through a CMP process; because the grinding liquid is blocked by the TIN in the CMP process, the lower layer of M0 cobalt cannot be corroded downwards by penetration, and finally the TIN layer is removed by using a dry etching or wet etching process, the problem of cobalt deficiency is solved, and the process integration is not complex.
Drawings
FIG. 1 is a flow chart of a method for forming a metal cobalt interconnect layer and a contact hole layer according to an embodiment of the present invention
FIGS. 2-7 are schematic diagrams illustrating the formation of a cobalt interconnect layer and a contact hole layer according to a preferred embodiment of the present invention
Detailed Description
The following description of the present invention will be made in detail with reference to the accompanying drawings 1 to 7.
The invention discloses a method for forming a metal cobalt interconnection layer and a contact hole layer, which is a method for partially filling through holes of the through hole layer through a selective tungsten deposition process and blocking CMP grinding fluid from permeating by using a subsequently deposited TIN bonding layer. Specifically, the idea of the invention is to fill tungsten in the through hole layer through a selective tungsten deposition process after forming the through hole through etching the through hole layer, and then deposit a TIN adhesive layer and tungsten to fill the through hole layer through hole, and then grind a TIN material on the tungsten metal selectively deposited in the through hole layer through hole through subsequent CMP. Because the grinding liquid is blocked by the TIN bonding layer in the CMP process, the lower M0 cobalt metal cannot be corroded by the grinding liquid, and finally the TIN layer is removed by using a dry etching or wet etching process, the problem of cobalt loss caused by the fact that the grinding liquid of the CMP corrodes the cobalt in the lower layer (an interconnection layer) in the manufacturing process of chemical mechanical grinding (tungsten grinding W CMP) of tungsten in the subsequent through hole layer is solved.
Referring to fig. 1, fig. 1 is a flow chart illustrating a method for forming a cobalt interconnect layer and a contact hole layer according to an embodiment of the invention. In an embodiment of the present invention, the method for forming the metal cobalt interconnection layer and the contact hole layer specifically includes the following steps:
step S1: providing a substrate containing an interconnection layer structure, and forming a dielectric layer on the substrate, wherein the interconnection layer structure comprises interconnection material including metal cobalt;
step S2: carrying out a standard photoetching process on the dielectric layer to form a patterned through hole layer; wherein the through hole in the through hole layer penetrates through the dielectric layer;
step S3: carrying out tungsten deposition on the through hole layer by adopting a selective tungsten deposition process so as to enable metal tungsten to fill the through holes in the through hole layer to form first parts of the through holes; the upper surface of the first part of the through hole is lower than the upper surface of the dielectric layer;
step S4: depositing a TIN bonding layer by using an ALD (atomic layer deposition) or CVD (chemical vapor deposition) process, and filling metal tungsten in the through hole layer by using a CVD (chemical vapor deposition) tungsten process to form a second part of the through hole; wherein the bottom of the second portion of the via hole is higher than the upper surface of the TIN bonding layer;
step S5: performing a tungsten chemical mechanical planarization process on the through hole layer, and removing a second part of the through hole to stop on the TIN bonding layer on the upper surface of the first part of the through hole;
step S6: and removing the TIN bonding layer by adopting a dry etching or wet etching process.
Further, the interconnection layer structure is an interconnection layer structure M0; the via layer is via layer V0.
The technical solution of the present invention is exemplified by a specific example below.
In the embodiment of the invention, the dielectric Layer sequentially comprises a Contact Etch Stop Layer (CESL for short) and a silicon oxide Layer from bottom to top. Preferably, the contact hole etching stop layer is made of silicon nitride or nitrogen-doped silicon carbide.
Referring to fig. 2-7, fig. 2-7 are schematic diagrams illustrating a process of forming a cobalt interconnect layer and a contact hole layer according to a preferred embodiment of the present invention. As shown in fig. 2, a substrate 1 having an interconnect layer structure 2 is provided, and a dielectric layer 3 (silicon nitride 31 and silicon oxide 32) is formed on the substrate 1, wherein the interconnect layer structure 2 includes a metal cobalt, and the silicon nitride 31 is a Contact Etch Stop Layer (CESL).
As shown in fig. 3, a result pattern obtained by performing a standard photolithography etching process on the dielectric layer is shown, that is, a patterned via layer is formed; wherein the through holes in the via layer penetrate the dielectric layer, that is, the through holes in the via layer have been etched through a contact hole etch stop layer (CESL), stopping on the surface of the interconnect lines in the interconnect layer structure.
As shown in fig. 4, a selective tungsten deposition process is used to perform tungsten deposition on the via layer, so that metal tungsten fills the via in the via layer to form a first portion of the via; wherein the upper surface of the first part of the through hole is lower than the upper surface of the dielectric layer.
In an embodiment of the present invention, to further increase the compressive stress between the dielectric in the dielectric layer and the tungsten metal and the sidewall in the through hole, the step S4 further includes performing a compressive stress process on the surface of the through hole layer to increase the compressive stress between the dielectric in the dielectric layer and the tungsten metal and the sidewall in the through hole.
Further, the compressive stress process is a plasma bias bombardment process. Preferably, the plasma bias bombardment process is a heavy ion plasma bias bombardment process. For example, the heavy ions are Ar ions.
In another embodiment of the present invention, the dielectric layer sequentially includes, from bottom to top, a contact hole etching stop layer and a flowing chemical vapor deposition silicon oxide layer, and the step S4 further includes performing a water vapor annealing process on the flowing chemical vapor deposition silicon oxide layer to further increase the compressive stress between the dielectric in the dielectric layer and the tungsten metal in the through hole and the sidewall.
As shown in fig. 5, an Atomic Layer Deposition (ALD) or Chemical Vapor Deposition (CVD) process is used to deposit a TIN adhesion layer, and a Chemical Vapor Deposition tungsten process is used to fill the via holes in the via layer with metal tungsten to form the second portion of the via holes.
As shown in fig. 6, the via layer is subjected to a tungsten chemical mechanical planarization process to remove the second portion of the via to stop on the TIN adhesion layer on the upper surface of the first portion of the via. That is, the tungsten chemical mechanical planarization process through the via layer removes not only the second portion of the via, but also the TIN adhesion layer on the top surface and a portion of the sidewall of the silicon oxide 32, and the silicon oxide 32 material above the bottom of the second portion of the via.
As shown in fig. 7, the TIN bonding layer on the upper surface of the first portion of the through hole is removed by using a dry etching or wet etching process, and the upper surface of the first portion of the through hole is exposed, so that the manufacturing of the metal cobalt interconnection layer and the contact hole layer is completed. Preferably, the wet etching process is an SPM process, wherein H is usually used in the SPM process2SO4、H2O2、H2And (3) a mixed solution of O.
The above description is only for the preferred embodiment of the present invention, and the embodiment is not intended to limit the scope of the present invention, so that all the equivalent structural changes made by using the contents of the description and the drawings of the present invention should be included in the scope of the present invention.
Claims (10)
1. A method for forming a metal cobalt interconnection layer and a contact hole layer is characterized by comprising the following steps:
step S1: providing a substrate containing an interconnection layer structure, and forming a dielectric layer on the substrate, wherein the interconnection layer structure comprises interconnection material including metal cobalt;
step S2: carrying out a standard photoetching process on the dielectric layer to form a patterned through hole layer; wherein the through hole in the through hole layer penetrates through the dielectric layer;
step S3: carrying out tungsten deposition on the through hole layer by adopting a selective tungsten deposition process so as to enable metal tungsten to fill the through holes in the through hole layer to form first parts of the through holes; the upper surface of the first part of the through hole is lower than the upper surface of the dielectric layer;
step S4: depositing a TIN bonding layer by using an ALD (atomic layer deposition) or CVD (chemical vapor deposition) process, and filling metal tungsten in the through hole layer by using a CVD (chemical vapor deposition) tungsten process to form a second part of the through hole;
step S5: performing a tungsten chemical mechanical planarization process on the through hole layer, and removing a second part of the through hole to stop on the TIN bonding layer on the upper surface of the first part of the through hole;
step S6: and removing the TIN bonding layer by using a dry etching or wet etching process.
2. The method of claim 1, wherein the dielectric layer comprises, in order from bottom to top, a contact etch stop layer and a silicon oxide layer.
3. The method of claim 2, wherein the contact etch stop layer is made of silicon nitride or silicon carbide doped with nitrogen.
4. The method of claim 3, wherein the wet etching process is an SPM process.
5. The method of claim 2, wherein the step S4 further comprises performing a compressive stress process on the surface of the via layer to increase the compressive stress between the dielectric in the dielectric layer and the tungsten metal and the sidewall in the via.
6. The method of claim 5, wherein the compressive stress process is a plasma bias bombardment process.
7. The method of claim 6, wherein the plasma bias bombardment process is a heavy ion plasma bias bombardment process.
8. The method of claim 6, wherein the heavy ions are Ar ions.
9. The method of claim 1, wherein the dielectric layer comprises, in order from bottom to top, a contact hole etch stop layer and a flowable chemical vapor deposition silicon oxide layer, and the step S4 further comprises performing a water vapor annealing process on the flowable chemical vapor deposition silicon oxide layer to further increase a compressive stress between the dielectric in the dielectric layer and the sidewall of the via tungsten plug.
10. The method of forming interconnect and contact hole layers in a semiconductor device of claim 1, wherein said interconnect layer structure is an interconnect layer structure M0; the via layer is via layer V0.
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| CN202011479297.6A CN112582340B (en) | 2020-12-15 | 2020-12-15 | Method for forming metal cobalt interconnection layer and contact hole layer |
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| CN202011479297.6A CN112582340B (en) | 2020-12-15 | 2020-12-15 | Method for forming metal cobalt interconnection layer and contact hole layer |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023220968A1 (en) * | 2022-05-18 | 2023-11-23 | 华为技术有限公司 | Chip and preparation method therefor, and electronic device |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1253376A (en) * | 1998-11-06 | 2000-05-17 | 日本电气株式会社 | Method for making semi-conductor device |
| JP2004235211A (en) * | 2003-01-28 | 2004-08-19 | Matsushita Electric Ind Co Ltd | Semiconductor device and manufacturing method therefor |
| US20050184394A1 (en) * | 2004-02-24 | 2005-08-25 | Sang-Woo Lee | Methods of forming a metal wiring in semiconductor devices using etch stop layers and devices so formed |
| US20070222078A1 (en) * | 2006-03-23 | 2007-09-27 | Nec Electronics Corporation | Semiconductor device and method of manufacturing the same |
| CN104157562A (en) * | 2014-08-26 | 2014-11-19 | 上海华虹宏力半导体制造有限公司 | Method for forming semiconductor structure |
| CN109690755A (en) * | 2016-09-30 | 2019-04-26 | 英特尔公司 | Using tungstenic adhesive layer enhancing interlinking reliability can with realize cobalt interconnection microelectronic component and method |
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- 2020-12-15 CN CN202011479297.6A patent/CN112582340B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1253376A (en) * | 1998-11-06 | 2000-05-17 | 日本电气株式会社 | Method for making semi-conductor device |
| JP2004235211A (en) * | 2003-01-28 | 2004-08-19 | Matsushita Electric Ind Co Ltd | Semiconductor device and manufacturing method therefor |
| US20050184394A1 (en) * | 2004-02-24 | 2005-08-25 | Sang-Woo Lee | Methods of forming a metal wiring in semiconductor devices using etch stop layers and devices so formed |
| US20070222078A1 (en) * | 2006-03-23 | 2007-09-27 | Nec Electronics Corporation | Semiconductor device and method of manufacturing the same |
| CN104157562A (en) * | 2014-08-26 | 2014-11-19 | 上海华虹宏力半导体制造有限公司 | Method for forming semiconductor structure |
| CN109690755A (en) * | 2016-09-30 | 2019-04-26 | 英特尔公司 | Using tungstenic adhesive layer enhancing interlinking reliability can with realize cobalt interconnection microelectronic component and method |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023220968A1 (en) * | 2022-05-18 | 2023-11-23 | 华为技术有限公司 | Chip and preparation method therefor, and electronic device |
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