CN112581563A

CN112581563A - Geometry rendering method, electronic device, and computer-readable storage medium

Info

Publication number: CN112581563A
Application number: CN202011501865.8A
Authority: CN
Inventors: 不公告发明人
Original assignee: Advanced Manufacturing EDA Co Ltd
Current assignee: Advanced Manufacturing EDA Co Ltd
Priority date: 2020-12-17
Filing date: 2020-12-17
Publication date: 2021-03-30
Anticipated expiration: 2040-12-17
Also published as: CN112581563B

Abstract

A geometry rendering method, an electronic device, and a computer-readable storage medium are described herein. The method comprises the following steps: determining a second geometric figure from a set of geometric figures adjacent to the first geometric figure, the first geometric figure being colored a first color other than the predetermined color, the second geometric figure being colored a second color of the predetermined color, the second color being different from the color of the geometric figures of the first set other than the second geometric figure; re-coloring the first and second geometries to obtain a re-colored circuit layout, the first geometry being colored in a second color and the second geometry being colored in a third color of the predetermined plurality of colors different from the second color; determining whether adjacent geometric figures with the same color exist in the recoloring circuit layout; if it is determined that the first and second geometric figures are not present, the recoloring of the first and second geometric figures is retained. In this way, coloring conflicts can be significantly reduced, enabling the coloring of the geometry to be optimized.

Description

Geometry rendering method, electronic device, and computer-readable storage medium

Technical Field

Embodiments of the present disclosure relate generally to the field of semiconductor technology, and more particularly, to a method, electronic device, and computer-readable storage medium for coloring geometry in a circuit layout.

Background

As integrated circuit fabrication processes evolve, distances between target patterns in an integrated circuit decrease and the density of circuit layout patterns increases. When the wavelength of light used in the photolithography technique cannot be reduced accordingly, pattern collision may occur if the distance between two layout patterns on the same photomask is less than a predetermined value. The multi-patterning technique is one of the effective means for solving the pattern conflict. The technique involves decomposing a design layout pattern into layout patterns in two or more photomasks.

In generating a photomask for multiple patterning, it is desirable to be able to reduce the time required to generate a photomask for multiple patterning. Therefore, in order to implement triple patterning coloring, which is increasingly widely used, it is desirable to provide a rapid and reliable coloring method. However, finding the number of colors for a graph is an NP-C problem (Non-deterministic Polynomial complex, a Non-deterministic problem of Polynomial complexity). Briefly, the NP-C problem is whether the polynomial time (polynomial time is O (1), O (logN)), O (N)²) Such time complexity, which can be expressed by a polynomial, is generally considered to be limited to solving the computer-solvable problem within polynomial time), the answer is not unambiguous. At present, no polynomial time algorithm is found, and no polynomial time algorithm exists.

A pattern coloring algorithm, the Welsh Powell (WP) algorithm, is known. The algorithm runs faster. However, this algorithm also does not guarantee that the graphic is colored with the minimum number of colors required.

Disclosure of Invention

Embodiments of the present disclosure provide geometric figure shading methods, electronic devices, and computer-readable storage media that are capable of reducing or even eliminating shading conflicts in geometric figures shaded with current shading schemes at a faster rate.

In a first aspect, a method of coloring a geometry in a circuit layout is provided. The method comprises the following steps: determining a second geometric figure from a first set of geometric figures adjacent to the first geometric figure, wherein the first geometric figure is colored in a first color other than the predetermined plurality of colors, and the second geometric figure is colored in a second color of the predetermined plurality of colors, the second color being different from the colors of the other geometric figures in the first set of geometric figures other than the second geometric figure; re-coloring the first geometry and the second geometry to obtain a re-colored circuit layout in which the first geometry is colored in a second color and the second geometry is colored in a third color of the predetermined plurality of colors, the third color being different from the second color; if it is determined that no coloring conflicts exist in the recolored circuit layout, recolored first and second geometries are retained. The coloring conflict indicates neighboring geometries that are the same color due to recoloring the first geometry and the second geometry.

In a second aspect, an electronic device is provided. The electronic device includes: a processing unit; a memory coupled to the processing unit and including a program stored thereon that, when executed by the processing unit, causes the electronic device to perform actions comprising: determining a second geometric figure from a first set of geometric figures adjacent to the first geometric figure, wherein the first geometric figure is colored in a first color other than the predetermined plurality of colors, and the second geometric figure is colored in a second color of the predetermined plurality of colors, the second color being different from the colors of the other geometric figures in the first set of geometric figures other than the second geometric figure; re-coloring the first geometry and the second geometry to obtain a re-colored circuit layout in which the first geometry is colored in a second color and the second geometry is colored in a third color of the predetermined plurality of colors, the third color being different from the second color; if it is determined that no coloring conflicts exist in the recolored circuit layout, recolored first and second geometries are retained. The coloring conflict indicates neighboring geometries that are the same color due to recoloring the first geometry and the second geometry.

In some embodiments, if it is determined that a coloring conflict exists in the recolored circuit layout, then recolored of the first geometry and the second geometry is abandoned.

In some embodiments, wherein determining the second geometry from the first set of geometries that is adjacent to the first geometry comprises: determining at least one third geometric figure from the first set of geometric figures, each third geometric figure of the at least one third geometric figure having a different color than the other geometric figures of the first set of geometric figures; and selecting the second geometry from the at least one third geometry based on the number of neighboring geometries of each of the at least one third geometry.

In some embodiments, wherein selecting the second geometry from the at least one third geometry based on the number of neighboring geometries of each of the at least one third geometry comprises: and determining the third geometric figure with the minimum number of adjacent geometric figures in the at least one third geometric figure as the second geometric figure.

In some embodiments, wherein recoloring the first geometry and the second geometry to obtain a recoloring circuit layout comprises: recoloring the first geometric figure with a second color; selecting a third color from a predetermined plurality of colors; and recoloring the second geometry with a third color to obtain a recoloring circuit layout.

In some embodiments, wherein recoloring the first geometry and the second geometry to obtain a recoloring circuit layout comprises: determining a fourth geometric figure which is colored into a fourth color from a second group of geometric figures adjacent to the second geometric figure, wherein the fourth color is different from the colors of the geometric figures except the fourth geometric figures in the second group of geometric figures in the predetermined plurality of colors; coloring the second geometric figure with a fourth color; and recoloring the fourth geometry with a color of the predetermined plurality of colors to obtain a recoloring circuit layout.

In some embodiments, the method further comprises, if it is determined that there is a coloring conflict in the recoloring circuit layout, coloring the second geometry with a color of the predetermined plurality of colors that is different from the second color and the fourth color to update the recoloring circuit layout.

In some embodiments, the method further comprises: determining a plurality of geometric figures from the circuit layout, the plurality of geometric figures being colored to colors other than a predetermined plurality of colors; and selecting a first geometric figure from the plurality of geometric figures.

In a third aspect, a computer-readable storage medium is provided. The computer readable storage medium has stored thereon machine executable instructions which, when executed by a processor, cause the processor to implement a method according to the first aspect of the disclosure.

According to the embodiment of the present disclosure, the scheme for coloring the geometric figure can significantly reduce coloring conflict, so that coloring of the geometric figure can be optimized.

Drawings

The above and other objects, features and advantages of the present disclosure will become more apparent by describing in more detail exemplary embodiments thereof with reference to the attached drawings. In exemplary embodiments of the present disclosure, like reference numerals generally represent like parts. In the drawings:

FIG. 1 shows a schematic diagram of a colored circuit layout represented by nodes;

FIG. 2 is a schematic diagram of a circuit layout rendered according to a conventional rendering method;

FIG. 3 illustrates a screenshot of a conflict result displayed by running a known geometry shading method;

FIG. 4 shows a flow diagram of a geometry shading method according to an embodiment of the present disclosure;

FIG. 5 illustrates a screenshot of the results of a geometry shading method run in accordance with an embodiment of the present disclosure;

FIG. 6 shows a schematic diagram of a circuit layout after coloring by a geometry coloring method according to an embodiment of the disclosure; and

FIG. 7 is a schematic block diagram of an electronic device for implementing embodiments of the present disclosure.

Detailed Description

Preferred embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While the preferred embodiments of the present disclosure are illustrated in the accompanying drawings, it is to be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

The term "include" and variations thereof as used herein is meant to be inclusive in an open-ended manner, i.e., "including but not limited to". Unless specifically stated otherwise, the term "or" means "and/or". The term "based on" means "based at least in part on". The terms "one example embodiment" and "one embodiment" mean "at least one example embodiment". The term "another embodiment" means "at least one additional embodiment". The terms "first," "second," and the like may refer to different or the same object. Other explicit and implicit definitions are also possible below.

Fig. 1 shows a schematic diagram of a colored circuit layout 100 represented by nodes. As shown in FIG. 1, the circuit layout 100 includes a plurality of

nodes

102, 104, 106, 108, 110, 112, 114, 116, 118, 120 in its graph. The nodes are connected by line segments. Wherein each node represents a geometric figure, and a line segment connecting two nodes indicates that the geometric figures represented by the two nodes are adjacent. The graph is colored, and any two adjacent nodes (namely two nodes connected by line segments) do not have the same color, otherwise, coloring conflict exists. As shown in FIG. 1,

nodes

110, 112 and 114A, G and C have the same first color.

Nodes

104, 108 and 116 have the same second color.

Nodes

102, 106, 118, and 120 have the same third color. Thus, no two adjacent nodes in fig. 1 have the same color. That is, there is no coloring conflict in fig. 1.

However, as the number of geometries increases, the probability of collisions in the colored geometries increases. Conventional coloring methods cannot guarantee that all geometric figures in a figure are colored with only three colors without coloring conflicts. For this reason, in the case where all the geometric figures in the figure cannot be colored with three colors without coloring conflicts, a fourth or even more than fourth color is introduced to color the figure to avoid the conflicts. However, even if coloring is performed with the fourth or more color, there is no guarantee that there will certainly be no coloring conflict.

Fig. 2 shows a schematic diagram of a circuit layout 200 after coloring according to a conventional coloring method. As shown in fig. 2, the circuit layout 200 includes a plurality of geometric shapes. The geometry in the circuit layout shown in fig. 2 is a geometry colored by a conventional coloring method. For example, geometry rendered via the WP algorithm. The WP algorithm is a greedy algorithm. It ranks the nodes in a particular order n1, …, nk and assigns ni the smallest available color that the neighbor of ni does not use in n1, …, ni-1. New colors can be added if desired. The quality of the result coloring depends on the selected ordering. The WP algorithm proposes to rank the nodes according to their price/degree (number of neighboring nodes per node). The algorithm runs faster. As shown in fig. 2, the

geometries

202, 204, 206, 208, 210 shown in gray are geometries that conflict. The intermediate geometry 210 conflicts with the adjacent upper geometry 204 and geometry 206, and the intermediate geometry 210 also conflicts with the lower geometry 202 and geometry 208. In the rest of fig. 2, there is no conflict between two adjacent geometries within a predetermined distance. It can be seen that there are shading conflicts in the geometry shaded by the WP algorithm, and it is desirable to be able to improve the WP algorithm to eliminate shading conflicts between the

geometries

202, 204, 206, 208, and 210 shown in fig. 2, for example.

FIG. 3 illustrates a screenshot 300 of a conflict result displayed by running a known geometry shading method. The geometry for which this screenshot is directed is the geometry that has been rendered for the circuit layout using, for example, the WP algorithm. This screenshot shows the results of the coloring conflict. Fig. 3 shows that a total of 8 coloring conflicts occur, i.e., there are 8 nodes (geometry) that cannot be colored with less than three colors and that neighboring nodes do not have the same color. "odd locks of size 3" as shown in FIG. 3 represents a closed loop formed by an odd number of vertices. A closed loop indicates that there is a conflict.

As mentioned previously, it is desirable to improve current geometry shading schemes to reduce or even eliminate shading conflicts in geometry shading by current shading schemes at a faster rate.

At least to address the above-mentioned problems, embodiments of the present disclosure provide improvements for coloring geometric figures. According to an embodiment, the second geometry is determined from a first set of geometries adjacent to the first geometry. The first geometric figure is colored in a first color other than the predetermined plurality of colors, and the second geometric figure is colored in a second color of the predetermined plurality of colors. The second color is different from colors of other geometries in the first set of geometries except the second geometry. The first geometry and the second geometry are recoloring to obtain a recoloring circuit layout. In the recolored circuit layout, the first geometry is colored in a second color and the second geometry is colored in a third color of the predetermined plurality of colors. The third color is different from the second color. It is determined whether a coloring conflict exists in the recolored circuit layout. If it is determined that there are no adjacent geometries in the recolored circuit layout that are the same color, recolored first and second geometries are retained.

In this way, by determining, in the colored first geometric figure, a second geometric figure that is colored in a color other than the predetermined plurality of colors. The first geometric figure is then colored with the color of the second geometric figure. The second geometric figure is then colored with a third color. It is then determined whether a coloring conflict exists in the recolored circuit layout. If it is determined that no coloring conflicts exist in the recolored circuit layout, recolored first and second geometries are retained. In this way, coloring conflicts via current coloring schemes can be eliminated or reduced.

Various example embodiments of the disclosure will be described in detail below with reference to various embodiments in conjunction with the following figures.

FIG. 4 shows a flow diagram of a geometry shading method 400 according to an embodiment of the present disclosure. At block 402, a second geometry is determined from a set of geometries adjacent to the first geometry. This set of geometries is also referred to as the "first set of geometries". The first geometric figure is colored in a first color other than the predetermined plurality of colors. The second geometric figure is colored to a second color of the predetermined plurality of colors. The second color is different from colors of other geometries in the first set of geometries except the second geometry.

In some embodiments, the predetermined plurality of colors may be three colors, e.g., red, green, blue. The first geometric figure refers to a geometric figure colored in a color other than red, green, blue, for example, a geometric figure colored in yellow, purple, or the like. These geometric figures that are colored in addition to the predetermined plurality of colors are objects that embodiments of the present disclosure are to optimize for processing. In other words, it is desirable to color the geometric figures colored by colors other than the predetermined plurality of colors with colors within the predetermined plurality of colors. It is ultimately desirable to color all of the first geometric figures with colors within a predetermined plurality of colors.

In some embodiments, at least one third geometry may be determined from the first set of geometries. Each of the at least one third geometric figure has a different color than the other geometric figures in the first set of geometric figures. The second geometry may then be selected from the at least one third geometry based on the number of neighboring geometries of the respective at least one third geometry. That is, a geometry of a different color than the other geometries in the first set of geometries may be determined from the first set of geometries, and these determined geometries are referred to as third geometries. Some of the first set of geometries may not have a third geometry present. There may be more than one third geometry in some first set of geometries. After determining the third geometry, the second geometry may be selected from among based on a predetermined condition. The first geometric figure may then be colored with the color of the selected second geometric figure.

In some embodiments, the third geometry having the smallest number of adjacent geometries in the at least one third geometry may be selected as the second geometry. In such an embodiment, in the case where the third geometry is plural, the third geometry in which the number of adjacent geometries is the smallest may be preferentially selected as the second geometry. Such a second geometry has a minimal number of adjacent geometries and, therefore, is relatively less likely to collide with the geometry coloring adjacent to the second geometry when the second geometry is recolored.

In some embodiments, the third geometry with the smallest number of adjacent geometries is selected as the second geometry. The first geometric figure is then colored with the color of the second geometric figure. And the third geometry is recolored itself (after coloring the first geometry with the color of the third geometry, the third geometry must be recolored, otherwise the colors would conflict because the third geometry is adjacent to the first geometry). If the recoloring circuit board diagram is found to have adjacent geometric figures with the same color generated due to the recoloring, the recoloring is cancelled, namely, the recoloring of the first geometric figure by the third geometric figure is cancelled and the recoloring of the third geometric figure is cancelled.

In some embodiments, for ease of description, a geometric figure is represented by a node. For example, an S node represents a node colored by a color other than a predetermined color (e.g., yellow, which is a fourth color other than three colors of red, green, and blue). Assume that the S node has four neighboring nodes A, B, C and D (i.e., a first set of geometries). Wherein A is colored in a first color (red), B is colored in a second color (green), and C and D are each colored in a 3 rd color (blue). Node a and node B are nodes that are each a different color from the other nodes in the neighboring nodes. Nodes a and B may therefore be referred to as being selected as the third geometry. One node may be arbitrarily selected from the two nodes a and B as the second geometry. For example, node a is selected. Node S is next colored with the color of node a (red). Node a then needs to be recolored. Because node A is adjacent to node S, the colors of node A and node S conflict without recoloring.

Assume that the neighboring node E of node a is colored by the second color (green) and the neighboring node F of node a is colored by the third color (blue). As can be seen from the above, the neighboring node S of node A has been colored by a first color. Therefore, node E and node F are both nodes with unique colors in the neighboring nodes of node A. Node E and node F may be referred to as a fourth geometry. Node A may be colored with a second color of E and may also be colored with a third color of F. If node A is colored with E in the second color, node E needs to be colored again. For example, node E may be recolored with the first or third color without causing conflicts with neighboring nodes. If node A is colored with F in a third color, then F needs to be colored again. For example, node F may be recolored with the first or second color without causing a conflict with neighboring nodes. In addition, node A colored with the third color does not conflict with its neighboring node coloring. Thus, the coloring of the S node succeeds.

In the above embodiment, one node is arbitrarily selected from the nodes a and B, and the node S is colored with the color of the node. In other embodiments, whether node A or node B is selected may be determined based on the number of respective neighbors of node A and node B, and node S may be colored with its color. Thus, in some other embodiments, where both node a and node B may be selected as the second node (the second geometry), the number of respective neighboring nodes for node a and node B is then determined. Node a has three adjacent nodes S, E and F. Node B has four neighboring nodes S, G, H and I. Node a may be selected because it has fewer neighboring nodes. Next an attempt is made to color node S with the color of node a (red). Node a then needs to be recolored.

In some embodiments, it is assumed that after node S is colored with the color of node A, node A cannot be colored with its neighboring nodes. That is, if node a is colored with its neighbors, it will cause collisions with the neighbors. Node S is colored with node a is discarded. Node S may then be colored with the color of the second node B. Next, consider again whether node B can be colored by one of the neighboring nodes G, H and I, but not the same color as its neighboring nodes. For example, node G is colored in a first color, node H is colored in a third color, and node I is colored in a third color. Since the node G is a node of the neighboring nodes that is different in color from the other nodes, the node B is colored with the color of the node G (the first color). After that, G needs to be recolored. For example, node G may be recolored with a second or third color without conflict with the coloring of neighboring nodes.

The coloring scheme of the node a in the embodiment of the present disclosure is not limited to the above manner. In some embodiments, the nodes in the set of geometries are connected in the same manner as in the previous embodiments. The only difference is that, for example, node F is colored in the second color. At this time, there is no node having a unique color other than the node S among the neighboring nodes of the node a. So in this embodiment, node a cannot be colored with the color of node E or node F. Since the colors of the nodes adjacent to the node a are the first color and the second color, respectively, the node a may be colored with a third color. And such coloring does not cause node a to conflict with coloring of its neighboring nodes. It can be seen that, if there is no neighboring node with a color appearing only once among the neighboring nodes of the node a, whether coloring with other colors can be considered without being limited to finding a node available for coloring from its neighboring nodes.

In some embodiments, a third geometry that minimizes the number of adjacent geometries may be selected as the second geometry and the first geometry may be colored with the color of the third geometry. The third geometry is then itself recolored. It is then determined whether the recoloring circuit board map has adjacent geometries that are the same color, i.e., whether there is a coloring conflict. If there is no coloring conflict, the first geometry is successfully colored.

In some embodiments, the first geometry may be colored by selecting a third geometry with the smallest number of adjacent geometries in the third geometry or a second-smallest third geometry as the second geometry, which increases the success rate of coloring. In this way, the coloring of the geometry in the circuit layout may be improved.

At block 404, the first geometry and the second geometry are recoloring to obtain a recoloring circuit layout. In the recolored circuit layout, the first geometry is colored in a second color and the second geometry is colored in a third color of the predetermined plurality of colors. The third color is different from the second color.

In some embodiments, the first geometric figure may be recolored with a second color. The third color may then be selected from a predetermined plurality of colors. The second geometry may then be recoloring with a third color to obtain a recoloring circuit layout.

In some embodiments, a fourth geometric figure colored in a fourth color that is different from the colors of the geometric figures other than the fourth geometric figure in the second set of geometric figures and is one of the predetermined plurality of colors may be determined from the second set of geometric figures adjacent to the second geometric figure; coloring the second geometric figure with a fourth color; and recoloring the fourth geometry with a color of the predetermined plurality of colors to obtain a recoloring circuit layout.

In some embodiments, if it is determined that there are neighboring geometries in the recoloring circuit layout that are the same color due to the recoloring, the second geometry is colored with a color of the predetermined plurality of colors and that is different from the second color and the fourth color to update the recoloring circuit layout.

In this way, coloring conflicts in the colored layout can be reduced or even avoided at a faster rate to meet the coloring requirements, thereby improving the reliability of the semiconductor process.

At block 406, if it is determined that no coloring conflicts exist in the recolored circuit layout, recolored first and second geometries are retained. The shading conflict indicates neighboring geometries that are the same color due to recoloring the first geometry and the second geometry. In some embodiments, it is determined whether a coloring conflict exists in the recolored circuit layout, and corresponding processing is performed according to the determined result. Specifically, if it is determined at block 406 that no shading conflicts exist in the recoloring circuit layout, then the recoloring of the first geometry and the second geometry is successful, thus preserving the recoloring of the first geometry and the second geometry. That is, the first geometric figure is colored with the second color and the second geometric figure is colored with the third color of the predetermined plurality of colors without causing coloring conflict, and the above-described coloring result is retained.

If it is determined at block 406 that a coloring conflict exists in the recolored circuit layout, then recolored of the first geometry and the second geometry is abandoned.

In some embodiments, the first geometric figure may be changed from a color outside the predetermined color to a color within the predetermined color by coloring the first geometric figure with a second color and coloring the second geometric figure with a third color of the predetermined plurality of colors. In this way, coloring conflicts can be reduced or even eliminated. Reducing the cost of the manufacturing process and increasing the reliability in the manufacturing process.

According to an embodiment of the present disclosure, a second geometry is determined from a first set of geometries adjacent to a first geometry. The first geometric figure is colored in a first color other than the predetermined plurality of colors, and the second geometric figure is colored in a second color of the predetermined plurality of colors. The second color is different from colors of other geometries in the first set of geometries except the second geometry. The first geometry and the second geometry are recoloring to obtain a recoloring circuit layout. In the recolored circuit layout, the first geometry is colored a second color and the second geometry is colored a third color of the predetermined plurality of colors, the third color being different from the second color. It is determined whether adjacent geometries of the same color are present in the recoloring circuit layout. If it is determined that no coloring conflicts exist in the recolored circuit layout, recolored first and second geometries are retained. In this way, coloring conflicts in geometries colored by current coloring schemes can be reduced or even eliminated.

It should be understood that the coloring method of the nodes (geometric figures) in the above embodiments is illustrative. The coloring method of the embodiment of the present disclosure is not limited to the above-described embodiment, but may be variously changed.

FIG. 5 illustrates a screenshot 500 of the result of a geometry shading method run in accordance with an embodiment of the present disclosure. In some embodiments, as shown in fig. 5, a circuit layout with a large Via (large Via) is subjected to a triple coloring process using a WP coloring algorithm, resulting in a coloring conflict. The algorithm according to embodiments of the present disclosure finds and resolves most shading conflicts among them.

Fig. 6 shows a schematic diagram of a circuit board diagram 600 after coloring by a geometry coloring method according to an embodiment of the disclosure. In some embodiments, as shown in fig. 6, the geometry in the circuit layout 600 is the geometry shown in fig. 2 after the geometry is colored by the coloring method according to the embodiment of the disclosure. As shown in fig. 6, the

nodes

202, 204, 206, 208, 210 in fig. 2 that have conflicts have all resolved the conflicts. That is, any two adjacent nodes of

nodes

202, 204, 206, 208, 210 are colored by different colors.

According to embodiments of the present disclosure, an improved coloring scheme is provided that eliminates or reduces coloring conflicts in geometries colored by current coloring methods. In this way, the reliability in terms of the manufacturing process is increased.

In the embodiment of the present disclosure, the geometry colored by the WP algorithm is taken as an example to show the improvement of the coloring method of the present disclosure on the WP algorithm. Those skilled in the art will appreciate that this is merely illustrative. The rendering method of the present disclosure is not limited to the modification of geometry rendered by the WP algorithm. That is, the algorithm of the present disclosure is not limited to use on geometry rendered via the WP algorithm, but may be used on geometry rendered by any rendering method.

Fig. 7 shows a schematic block diagram of an electronic device 700 for implementing embodiments of the present disclosure. As shown in fig. 7, electronic device 700 includes a Central Processing Unit (CPU)701 that may perform various appropriate actions and processes in accordance with computer program instructions stored in a Read Only Memory (ROM)702 or computer program instructions loaded from a storage unit 708 into a Random Access Memory (RAM) 703. In the RAM 703, various programs and data required for the operation of the electronic device 700 can also be stored. The CPU 701, the ROM 702, and the RAM 703 are connected to each other via a bus 704. An input/output (I/O) interface 705 is also connected to bus 704.

A number of components in the electronic device 700 are connected to the I/O interface 705, including: an input unit 706 such as a keyboard, a mouse, or the like; an output unit 707 such as various types of displays, speakers, and the like; a storage unit 708 such as a magnetic disk, optical disk, or the like; and a communication unit 709 such as a network card, modem, wireless communication transceiver, etc. The communication unit 709 allows the electronic device 700 to exchange information/data with other devices via a computer network such as the internet and/or various telecommunication networks.

The various processes and processes described above, for example method 400, may be performed by processing unit 701. For example, in some embodiments, the method 400 may be implemented as a computer software program tangibly embodied in a machine-readable medium, such as the storage unit 708. In some embodiments, part or all of the computer program may be loaded and/or installed onto the electronic device 700 via the ROM 702 and/or the communication unit 709. When the computer program is loaded into the RAM 703 and executed by the CPU 701, one or more steps of the method 400 described above may be performed.

Aspects in accordance with embodiments of the present disclosure may be methods, apparatus, systems, and/or computer program products. The computer program product may include a computer-readable storage medium having computer-readable program instructions embodied thereon for carrying out various aspects of the present disclosure. The computer readable storage medium may be a tangible device that can hold and store the instructions for use by the instruction execution device. The computer-readable program instructions may be downloaded to the respective computing/processing device from a computer-readable storage medium, or to an external computer or external storage device via a network, such as the internet, a local area network, a wide area network, and/or a wireless network.

Having described embodiments of the present disclosure, the foregoing description is intended to be exemplary, not exhaustive, and not limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen in order to best explain the principles of the embodiments, the practical application, or improvements made to the technology in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A method of coloring a geometric figure in a circuit layout, comprising:

determining a second geometric figure from a first set of geometric figures adjacent to the first geometric figure, wherein the first geometric figure is colored in a first color other than a predetermined plurality of colors, and the second geometric figure is colored in a second color of the predetermined plurality of colors, the second color being different from colors of other geometric figures in the first set of geometric figures other than the second geometric figure;

re-coloring the first geometry and the second geometry to obtain a re-colored circuit layout in which the first geometry is colored in the second color and the second geometry is colored in a third color of the predetermined plurality of colors, the third color being different from the second color;

reserving the recoloring of the first and second geometries if it is determined that a coloring conflict does not exist in the recoloring circuit layout, the coloring conflict indicating adjacent geometries that are the same color due to recoloring the first and second geometries.

2. The method of claim 1, further comprising:

discarding the recoloring of the first geometry and the second geometry if it is determined that the coloring conflict exists in the recoloring circuit layout.

3. The method of claim 1, wherein determining the second geometry from the first set of geometries adjacent to the first geometry comprises:

determining at least one third geometry from the first set of geometries, each of the at least one third geometry having a different color than the other geometries of the first set of geometries; and

selecting the second geometry from the at least one third geometry based on a number of neighboring geometries of each of the at least one third geometry.

4. The method of claim 3, wherein selecting the second geometry from the at least one third geometry based on the number of neighboring geometries of each of the at least one third geometry comprises:

determining a third geometric figure with the minimum number of adjacent geometric figures in the at least one third geometric figure as the second geometric figure.

5. The method of claim 1, wherein recoloring the first geometry and the second geometry to obtain the recoloring circuit layout comprises:

re-coloring the first geometric figure with the second color;

selecting the third color from the predetermined plurality of colors; and

re-coloring the second geometry with the third color to obtain the re-colored circuit layout.

6. The method of claim 5, wherein recoloring the first geometry and the second geometry to obtain the recoloring circuit layout comprises:

determining a fourth geometry from a second set of geometries adjacent to the second geometry that is colored a fourth color that is different from the colors of geometries in the second set of geometries other than the fourth geometry and that is one of the predetermined plurality of colors;

coloring the second geometric figure with the fourth color; and

re-coloring the fourth geometry with a color of the predetermined plurality of colors to obtain the re-colored circuit layout.

7. The method of claim 6, further comprising:

coloring the second geometry with a color of the predetermined plurality of colors that is different from the second color and the fourth color to update the recolored circuit layout if it is determined that the coloring conflict exists in the recolored circuit layout.

8. The method of claim 1, further comprising:

determining a plurality of geometric figures from the circuit layout, the plurality of geometric figures being colored to a color other than the predetermined plurality of colors; and

selecting the first geometry from the plurality of geometries.

9. An electronic device, comprising:

a processing unit;

a memory coupled to the processing unit and including a program stored thereon, which when executed by the processing unit, causes the electronic device to perform the method of any of claims 1-8.

10. A computer readable storage medium having stored thereon machine executable instructions which, when executed by a processor, cause the processor to implement the method of any one of claims 1 to 8.