CN112562777B - Capacitance measuring circuit and method thereof - Google Patents
Capacitance measuring circuit and method thereof Download PDFInfo
- Publication number
- CN112562777B CN112562777B CN202011395068.6A CN202011395068A CN112562777B CN 112562777 B CN112562777 B CN 112562777B CN 202011395068 A CN202011395068 A CN 202011395068A CN 112562777 B CN112562777 B CN 112562777B
- Authority
- CN
- China
- Prior art keywords
- circuit
- resistor
- voltage
- capacitor
- signal input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims description 19
- 230000015654 memory Effects 0.000 claims abstract description 39
- 239000003990 capacitor Substances 0.000 claims description 50
- 230000005684 electric field Effects 0.000 claims description 20
- 238000005259 measurement Methods 0.000 claims description 18
- 230000002093 peripheral effect Effects 0.000 claims description 5
- 230000000694 effects Effects 0.000 claims description 3
- 239000000463 material Substances 0.000 description 9
- 238000010586 diagram Methods 0.000 description 8
- 229910052451 lead zirconate titanate Inorganic materials 0.000 description 7
- 238000012360 testing method Methods 0.000 description 7
- 230000010287 polarization Effects 0.000 description 6
- 230000009471 action Effects 0.000 description 2
- 230000000630 rising effect Effects 0.000 description 2
- 229910020684 PbZr Inorganic materials 0.000 description 1
- VNSWULZVUKFJHK-UHFFFAOYSA-N [Sr].[Bi] Chemical compound [Sr].[Bi] VNSWULZVUKFJHK-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000004364 calculation method Methods 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000013500 data storage Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- HFGPZNIAWCZYJU-UHFFFAOYSA-N lead zirconate titanate Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ti+4].[Zr+4].[Pb+2] HFGPZNIAWCZYJU-UHFFFAOYSA-N 0.000 description 1
- 230000007334 memory performance Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000002269 spontaneous effect Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/50—Marginal testing, e.g. race, voltage or current testing
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R27/00—Arrangements for measuring resistance, reactance, impedance, or electric characteristics derived therefrom
- G01R27/02—Measuring real or complex resistance, reactance, impedance, or other two-pole characteristics derived therefrom, e.g. time constant
- G01R27/26—Measuring inductance or capacitance; Measuring quality factor, e.g. by using the resonance method; Measuring loss factor; Measuring dielectric constants ; Measuring impedance or related variables
- G01R27/2605—Measuring capacitance
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Measurement Of Resistance Or Impedance (AREA)
- Tests Of Electronic Circuits (AREA)
Abstract
The invention discloses a measuring circuit of ferroelectric memory capacitance, which is arranged on a chip and comprises a reference voltage generating circuit and a capacitance measuring circuit, wherein the reference voltage generating circuit is connected in series with a resistor between a voltage source and the ground to obtain different reference voltages, and a pMOS is adopted as a circuit switch, the capacitance measuring circuit is a differential or integral circuit formed by a capacitance to be measured, the resistor and a voltage comparator, and the capacitance of the capacitance can be calculated by measuring the output of the voltage comparator through an off-chip oscilloscope on the premise that the resistance value is known.
Description
Technical Field
The present invention relates to ferroelectric memory technology, and more particularly, to a circuit and method for measuring capacitance of a ferroelectric memory.
Background
Ferroelectric accumulator FRAM utilizes ferroelectric effect of ferroelectric crystal to realize data storage, and currently commonly used ferroelectric materials mainly include PZT (lead zirconate titanate PbZr x Til -x O 3 ) SBT (strontium bismuth tantalate Sr) 1-y Bi 2+x Ta 2 O 9 ) High-K ferroelectric materials, and the like. The polarization characteristics of ferroelectric materials have two stable states, taking PZT materials as an example, fig. 1a and 1b show two stable states of PZT ferroelectric materials, wherein the PZT polarization direction is positive when a positive electric field is applied, denoted as state "0", and the PZT polarization direction is negative when a negative electric field is applied, denoted as state "1".
FIG. 2 shows the hysteresis loop of the FRAM capacitor showing the different polarities of the ferroelectric capacitor at different electric fields, where Q r Refers to the degree of remnant polarization, Q s Refers to spontaneous polarization intensity, V c Referred to as coercive field. In the absence of electric field strength, ±q r Representing states "0" and "1", the applied electric field must be greater than + -V in order to achieve both states c Where "±" denotes the direction of the applied electric field. For ferroelectric capacitors, when the applied electric field is directed from the bit line to the plate line, it can be considered to write a "1" into the FRAMWhen the direction of the applied electric field flows from the plate line to the bit line, it can be regarded as writing "0" into the FRAM.
In order to understand the memory performance of the ferroelectric memory, the read/write control is better, and parameters such as the polarization degree of the ferroelectric capacitor in the ferroelectric memory and the capacitance value of the ferroelectric capacitor are sometimes required to be measured. In the prior art, if the ferroelectric capacitor is required to be measured, more complex equipment is usually required, and the performance requirement on the measuring equipment is higher, so that the testing cost is higher.
Disclosure of Invention
In view of some or all of the problems in the prior art, an aspect of the present invention provides a measurement circuit of ferroelectric memory capacitance, the measurement circuit being integrated on a chip, comprising:
a reference voltage generating circuit for generating a reference voltage, comprising a first voltage output terminal and/or a second voltage output terminal, and:
a pMOS having a first terminal connected to a voltage source and a second terminal connected to a first terminal of a first resistor, wherein the first terminal and the second terminal are respectively a source or a drain;
a first resistor, a second end of which is connected with a first end of a second resistor, and a second end of which is connected to a first voltage output end;
a second resistor, the second end of which is connected with the first end of the third resistor, and the second end of which is connected with the second voltage output end; and
a third resistor, the second end of which is grounded; and
the capacitance measuring circuit comprises a resistor and a voltage comparator, wherein the resistor, the voltage comparator and the capacitor to be measured form a differential circuit and/or an integral circuit, and the differential circuit and/or the integral circuit comprises:
in the differential circuit, a first end of the capacitor to be tested is connected to a first signal input end, a second end of the capacitor to be tested is connected to a second signal input end through a resistor, a non-inverting input end of the voltage comparator is connected to the second end of the capacitor to be tested, and a inverting input end of the voltage comparator is connected to a first voltage output end of the reference voltage generating circuit; and
in the integrating circuit, a first end of the capacitor to be measured is connected to a first signal input end through a resistor, a second end of the capacitor to be measured is connected to a second signal input end, a non-inverting input end of the voltage comparator is connected to a second voltage output end of the reference voltage generating circuit, and a inverting input end of the voltage comparator is connected to the first end of the capacitor to be measured.
Further, the first resistor, the second resistor and the third resistor are formed by connecting a plurality of resistors in series, and the resistance is equal to the resistance value of the resistor in the capacitance measuring circuit.
Further, the capacitance to be measured is obtained by connecting ferroelectric capacitors in a plurality of ferroelectric memory units in parallel.
Further, the capacitor to be measured comprises a plurality of capacitors connected in parallel, and the capacitors are the same as the storage capacitors of the ferroelectric memory.
Further, the capacitance measuring circuit further includes a switch connected in parallel with the resistor.
Further, the first signal input and the second signal input are connected to a serial peripheral interface SPI, and the serial peripheral interface is connected to a drive control signal.
Based on the measuring circuit, another aspect of the invention provides a method for measuring capacitance, comprising:
providing a voltage V for a reference voltage generating circuit through a voltage source, and connecting a grid electrode of the pMOS with a voltage of 0V;
inputting a high level at a first signal input terminal and inputting a low level at a second signal input terminal;
measuring the pulse width output by the voltage comparator; and
and calculating the capacitance according to the pulse width.
Further, the method further includes calculating an actual resistance value of the resistor R, including:
and measuring the current of the reference voltage generating circuit through an ammeter, and further calculating to obtain the actual resistance value of the resistor R.
Further, based on the measurement circuit, the invention further provides a writing method of the ferroelectric memory, which comprises the following steps:
closing the switch in the integrating circuit; and
providing an electric field to the ferroelectric memory capacitance to effect writing, comprising:
inputting a high level at a first signal input terminal and a low level at a second signal input terminal, writing a '1' in the ferroelectric memory; or (b)
A low level is input at the first signal input terminal and a high level is input at the second signal input terminal, and "0" is written in the ferroelectric memory.
The invention provides a measuring circuit and a measuring method for a ferroelectric memory capacitance. The measuring circuit and the measuring method have at least the following beneficial effects:
1. the reference voltage generating circuit adopts a plurality of identical resistors to be connected to a voltage source in series to obtain different reference voltages, and the resistors are identical to the resistors adopted in the capacitance measuring circuit, so that the accurate resistance value of the resistor can be obtained by measuring the current of the reference voltage generating circuit through external equipment, and the calculation accuracy of the capacitance value is further improved;
2. in the circuit, 256 ferroelectric memory units are connected in parallel to serve as capacitors to be measured, so that the pulse width output by the voltage comparator can be measured by an oscilloscope;
3. the input signal is rapidly generated by performing AND computation on the serial peripheral interface and the driving control signal;
4. the differential or integral circuit is adopted to measure the capacitance, so that the time of the capacitance in a high electric field is ensured to be as short as possible, and the capacitance is prevented from being in the high electric field for a long time, so that the capacitance value is changed;
5. the circuit is integrated on the chip, has a simple structure, and can conveniently measure the capacitance value of any point or wafer;
6. the measuring circuit not only can realize the measurement of capacitance, but also can realize the writing operation of the ferroelectric memory.
Drawings
To further clarify the above and other advantages and features of embodiments of the present invention, a more particular description of embodiments of the invention will be rendered by reference to the appended drawings. It is appreciated that these drawings depict only typical embodiments of the invention and are therefore not to be considered limiting of its scope. In the drawings, for clarity, the same or corresponding parts will be designated by the same or similar reference numerals.
FIGS. 1a-1b show two steady state schematic diagrams of a ferroelectric material PZT;
fig. 2 shows a ferroelectric hysteresis loop of a ferroelectric memory capacitor;
FIG. 3 shows a reference voltage generation circuit schematic of one embodiment of the invention;
FIG. 4a shows a schematic diagram of a differential circuit of one embodiment of the present invention;
FIG. 4b shows a schematic diagram of an integrating circuit according to one embodiment of the present invention;
FIG. 5a shows a differential circuit output schematic of one embodiment of the invention;
FIG. 5b shows a schematic diagram of the output of the integrating circuit according to one embodiment of the present invention;
FIG. 6a shows a schematic diagram of the operation of a ferroelectric memory according to one embodiment of the present invention to write a "1"; and
fig. 6b shows a schematic diagram of the operation of the ferroelectric memory according to one embodiment of the present invention to write a "0".
Detailed Description
In the following description, the present invention is described with reference to various embodiments. One skilled in the relevant art will recognize, however, that the embodiments may be practiced without one or more of the specific details, or with other alternative and/or additional methods, materials, or components. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of the invention. Similarly, for purposes of explanation, specific numbers, materials and configurations are set forth in order to provide a thorough understanding of the embodiments of the invention. However, the invention is not limited to these specific details. Furthermore, it should be understood that the embodiments shown in the drawings are illustrative representations and are not necessarily drawn to scale.
Reference throughout this specification to "one embodiment" or "the embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. The appearances of the phrase "in one embodiment" in various places in the specification are not necessarily all referring to the same embodiment.
It should be noted that the embodiments of the present invention describe the process steps in a specific order, however, this is merely to illustrate the specific embodiment and not to limit the order of the steps. In contrast, in various embodiments of the present invention, the order of the steps may be adjusted according to process adjustments.
In writing to ferroelectric memories, the applied electric field needs to be larger than the coercive field of the ferroelectric memory capacitance, and therefore it is necessary to measure the ferroelectric memory capacitance to better determine the magnitude of the electric field required in writing. The equipment required for directly measuring the capacitance of the ferroelectric memory is complex, and the requirement on the equipment precision is high, which makes the cost of the test high. In view of this problem, the inventors have invented a capacitance measuring circuit provided on a chip, and the scheme of the present invention is further described below with reference to the drawings of the embodiments.
A measuring circuit of ferroelectric memory capacitance is integrated on a chip and comprises a reference voltage generating circuit and a capacitance measuring circuit, wherein the reference voltage generating circuit is used for generating a reference voltage, and the reference voltage is input to the capacitance measuring circuit so as to realize the measurement of capacitance.
Fig. 3 shows a reference voltage generation circuit schematic of an embodiment of the invention. As shown in fig. 3, the reference voltage generating circuit includes a plurality of resistors connected in series to a voltage source, and employs a pMOS as a switch. The first end of the pMOS is connected with a voltage source, the second end of the pMOS is connected to a resistor, the first end and the second end are respectively a source electrode or a drain electrode, when the grid voltage of the pMOS is 0V, the pMOS is turned on, and when the grid is at a high level, the pMOS is turned off. The voltage source may be any on-chip dc voltage source. In one embodiment of the present invention, the output voltage of the voltage source is 3V, the current flowing through the reference voltage generating circuit is 30uA, and the reference voltage required by the capacitance measuring circuit is 1.2V and/or 1.8V, so the reference voltage generating circuit includes a first resistor, a second resistor and a third resistor, where the first resistor, the second resistor and the third resistor are connected in series, the first end of the first resistor is connected to the second end of the pMOS, the second end of the third resistor is grounded, the junction of the first resistor and the second resistor is connected to the first voltage output end, the first reference voltage is output, the junction of the second resistor and the third resistor is connected to the second voltage output end, and the resistances of the first resistor, the second resistor and the third resistor are 40kΩ, 20kΩ and 40kΩ, respectively.
Fig. 4a and 4a show two different capacitance measuring circuits according to the embodiment of the invention, wherein fig. 4a shows a differential circuit and fig. 4b shows an integral circuit. For ferroelectric memory, if a strong electric field is loaded at both ends of the capacitor for a long time, the capacitance value of the capacitor will change, in order to accurately measure the capacitor, the shorter the duration of the strong electric field loaded on the capacitor is, based on this, the inventor adopts a resistor and a voltage comparator to form a differential circuit and/or an integral circuit with the capacitor to be measured, and measures the pulse width output by the voltage comparator through an off-chip oscilloscope, and finally calculates the capacitance value of the capacitor, wherein:
in the differentiating circuit, a first end of the capacitor to be measured is connected to a first signal input end, a second end of the capacitor to be measured is connected to a second signal input end through a resistor, a non-inverting input end of the voltage comparator is connected to the second end of the capacitor to be measured, and a inverting input end of the voltage comparator is connected to the first voltage output end. Fig. 5a shows a schematic diagram of an output waveform of a voltage comparator in a differential circuit, after a test mode is activated, a first signal input terminal keeps a high level input, the output of the voltage comparator forms a rising edge, under the action of the differential circuit, the voltage of an in-phase input terminal of the voltage comparator is gradually reduced by Vcc and is finally lower than a first reference voltage, at this time, the output of the voltage comparator forms a falling edge to obtain a pulse comp, the pulse and the width thereof can be conveniently measured by an off-chip oscilloscope, and then the capacitance C of the capacitor to be measured can be obtained according to the following formula:
C＝tcr/R/ln(Vcc/refcr)，
wherein tcr is the width of the pulse combr, R is the resistance of the resistor, vcc is the input voltage of the differential circuit and refcr is the first reference voltage; and
in the integrating circuit, a first end of the capacitor to be tested is connected to a first signal input end through a resistor, a second end of the capacitor to be tested is connected to a second signal input end, a non-inverting input end of the voltage comparator is connected to the second voltage output end, and a inverting input end of the voltage comparator is connected to the first end of the capacitor to be tested. Fig. 5b shows a schematic diagram of an output waveform of a voltage comparator in an integrating circuit, after a test mode is activated, a first signal input terminal keeps a high level input, the output of the voltage comparator forms a rising edge, under the action of the integrating circuit, the voltage of an inverting input terminal of the voltage comparator rises gradually from 0 and is finally higher than a second reference voltage, at this time, the output of the voltage comparator forms a falling edge to obtain a pulse comp C, the pulse and the width thereof can be conveniently measured by adopting an off-chip oscilloscope, and then the capacitance value C of the capacitor to be measured can be obtained according to the following formula:
C＝trc/R/ln[1/(1-refrc/Vcc)]，
wherein trc is the width of the pulse combc, R is the resistance of the resistor, vcc is the input voltage of the integrating circuit and refrc is the second reference voltage.
In one embodiment of the present invention, the first signal input terminal and the second signal input terminal are connected to a serial peripheral interface SPI, when a test is required, a designated sequence is sent through the SPI to activate a test mode, and after the "mode_capm_in" and the drive control signal in the sequence are respectively and-ed, a first signal input capm_in and a second signal input capm_plin are obtained, and in the test mode, the mode_capm_in=1 and the mode_capm_plin=0, so that after the drive control, a first signal input capm_in=1 and a second signal input capm_plin=0 are obtained.
In order to calculate the capacitance value more accurately, it is necessary to obtain an accurate resistance value, but the direct measurement of the resistance value has higher requirements on equipment, based on which the inventors propose the following resistance value measuring method: in the reference voltage generating circuit, the same resistors as those in the capacitance measuring circuit are adopted in series to obtain a first resistor, a second resistor and a third resistor, and in consideration of the measuring precision of an oscilloscope, the resistance R of the resistor adopted in the differentiating circuit and/or the integrating circuit is about 10kΩ, so that the requirement is satisfied, in one embodiment of the invention, the first resistor comprises four resistors R, the second resistor comprises 2 resistors R, the third resistor comprises 4 resistors R, and the nominal value of the resistor R is 10kΩ. After the pMOS is conducted, the current value Isup in the reference voltage generating circuit can be conveniently measured through the off-chip meter, and then the accurate resistance value of the resistor R can be calculated according to the current value and the output voltage Vrffs of the voltage source:
R＝Vrefs/Isup/10。
in addition, since the accuracy of the oscilloscope is usually 100ns, the capacitance value in the differentiating circuit and/or the integrating circuit should be about 10pF, and in order to achieve this capacitance value, in actual measurement, a plurality of, for example, 256 memory cells of the ferroelectric memory should be connected in parallel, or a plurality of, for example, 256 ferroelectric capacitors equal to the memory capacitance of the memory cells of the ferroelectric memory should be additionally provided on the chip for parallel connection, and then connected to the capacitance measuring circuit.
Based on the measuring circuit, the measurement of the ferroelectric memory capacitance can be performed according to the following method:
firstly, providing a voltage Vrefs for a reference voltage generating circuit through a voltage source, and connecting a grid electrode of the pMOS with a 0V voltage to obtain a first reference voltage and a second reference voltage;
next, the enabling chip sends a specified sequence through the SPI, so that the first signal input terminal outputs a high level, and the second signal input terminal outputs a low level;
next, measuring a pulse width output by the voltage comparator by an off-chip oscilloscope, and measuring a current Isup in the reference voltage generating circuit by an off-chip ammeter; and
finally, calculating the capacitance value of the capacitor:
c=tcr/R/ln (Vcc/refcr), or
C＝trc/R/ln[1/(1-refrc/Vcc)]，
Where tcr is the width of the pulse output by the differentiating circuit, trc is the width of the pulse output by the integrating circuit, r=vrefs/Isup/10 is the resistance of the resistor, vcc is the input voltage of the differentiating circuit and/or integrating circuit, refcr is the first reference voltage, and refrc is the second reference voltage.
After the measurement circuit is simply modified, the write operation of the ferroelectric memory can be realized, if the function is to be realized, only a switch is connected in parallel to two ends of a resistor in the integrating or differentiating circuit, and the switch is closed during the write operation, so that pgm=1.
The following describes the procedure of the write operation specifically by taking an integrating circuit as an example:
when "1" needs to be written, as shown in fig. 6a, the switch is closed first, then a designated sequence is sent through the SPI, so that the cap_in=1 and cap_plin=0, and at this time, the electric field flowing through the ferroelectric memory capacitor is a positive electric field, so that "1" writing is completed; and
when "0" needs to be written, as shown in fig. 6b, the switch is first closed, and then a designated sequence is sent through the SPI, so that the capm_in=0 and the capm_plin=1, and at this time, the electric field flowing through the ferroelectric memory capacitor is a negative electric field, and the writing of "0" is completed.
While various embodiments of the present invention have been described above, it should be understood that they have been presented by way of example only, and not limitation. It will be apparent to those skilled in the relevant art that various combinations, modifications, and variations can be made therein without departing from the spirit and scope of the invention. Thus, the breadth and scope of the present invention as disclosed herein should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.
Claims (9)
1. A ferroelectric memory capacitance measurement circuit, disposed on a chip, comprising:
a reference voltage generation circuit configured to generate a reference voltage, the reference voltage generation circuit comprising:
a first voltage output terminal;
a second voltage output terminal;
a pMOS having a first terminal connected to a voltage source and a second terminal connected to a first terminal of a first resistor, wherein the first terminal and the second terminal are respectively a source or a drain;
a first resistor, a second end of which is connected with a first end of a second resistor, and a second end of the first resistor is connected to the first voltage output end;
a second resistor, a second end of which is connected with a first end of a third resistor, and a second end of which is connected to the second voltage output end; and
a third resistor, the second end of which is grounded; and
the capacitance measuring circuit comprises a resistor and a voltage comparator, wherein the resistor, the voltage comparator and the capacitor to be measured form a differential circuit and/or an integral circuit, and the differential circuit and/or the integral circuit comprises:
in the differential circuit, a first end of the capacitor to be tested is connected to a first signal input end, a second end of the capacitor to be tested is connected to a second signal input end through a resistor, a non-inverting input end of the voltage comparator is connected to the second end of the capacitor to be tested, and a inverting input end of the voltage comparator is connected to a first voltage output end of the reference voltage generating circuit; and
in the integrating circuit, a first end of the capacitor to be measured is connected to a first signal input end through a resistor, a second end of the capacitor to be measured is connected to a second signal input end, a non-inverting input end of the voltage comparator is connected to a second voltage output end of the reference voltage generating circuit, and a inverting input end of the voltage comparator is connected to the first end of the capacitor to be measured.
2. The measurement circuit of claim 1 wherein the first, second and third resistors are formed from a plurality of identical resistors in series, and the resistances are equal to the resistances of the resistors in the capacitance measurement circuit.
3. The measurement circuit of claim 1 wherein the capacitance to be measured is formed by a plurality of ferroelectric capacitors in parallel, the ferroelectric capacitors being the same as the storage capacitance of the ferroelectric memory.
4. The measurement circuit of claim 1, wherein the capacitance measurement circuit further comprises a switch in parallel with the resistor.
5. The measurement circuit of claim 1 wherein the first signal input and the second signal input are connected to a serial peripheral interface, SPI, and the SPI is connected to a drive control signal.
6. A method of capacitance measurement based on a measurement circuit according to any of claims 2 to 5, comprising the steps of:
providing a voltage to a reference voltage generating circuit by a voltage source to generate a first reference voltage and/or a second reference voltage;
inputting a high level at a first signal input terminal and inputting a low level at a second signal input terminal;
measuring the pulse width output by the voltage comparator; and
and calculating the measured value of the capacitor to be measured according to the pulse width.
7. The method of claim 6, wherein: when a differential circuit is adopted, the measured value C=tcr/R/ln (Vcc/refcr) of the capacitor to be measured, wherein tcr is the pulse width output by the voltage comparator, R is the resistance value of the resistor, vcc is the input voltage of the differential circuit and refcr is the first reference voltage output by the first voltage output end; when the integrating circuit is adopted, the measured value C=trc/R/ln [ 1/(1-refrc/Vcc) ] of the capacitor to be measured, wherein trc is the pulse width output by the voltage comparator, R is the resistance value of the resistor, vcc is the input voltage of the integrating circuit and refrc is the second reference voltage output by the second voltage output end.
8. The method of claim 7, further comprising calculating an actual resistance value of the resistor R, comprising:
if the resistances of the first resistor, the second resistor and the third resistor are the same as the resistances in the differentiating circuit and the integrating circuit, the current of the reference voltage generating circuit is measured by an ammeter, and then the actual resistance of the resistor is calculated.
9. A ferroelectric memory writing method based on the measuring circuit according to claim 4, characterized in that when the measuring circuit is an integrating circuit, the writing method comprises the steps of:
closing the switch; and
providing an electric field to the ferroelectric memory capacitance to effect writing, comprising:
inputting a high level at a first signal input terminal and a low level at a second signal input terminal to write "1" in the ferroelectric memory; or (b)
A low level is input at the first signal input terminal and a high level is input at the second signal input terminal to write "0" in the ferroelectric memory.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011395068.6A CN112562777B (en) | 2020-12-03 | 2020-12-03 | Capacitance measuring circuit and method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011395068.6A CN112562777B (en) | 2020-12-03 | 2020-12-03 | Capacitance measuring circuit and method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN112562777A CN112562777A (en) | 2021-03-26 |
| CN112562777B true CN112562777B (en) | 2024-01-26 |
Family
ID=75047638
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202011395068.6A Active CN112562777B (en) | 2020-12-03 | 2020-12-03 | Capacitance measuring circuit and method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112562777B (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0415564A (en) * | 1990-05-08 | 1992-01-20 | Seiko Epson Corp | Capacitance measuring circuit |
| JP2005322889A (en) * | 2004-04-05 | 2005-11-17 | Fujitsu Ltd | Measuring method of ferroelectric capacitor and designing method of ferroelectric memory |
| CN111402939A (en) * | 2020-03-26 | 2020-07-10 | 珠海拍字节信息科技有限公司 | Ferroelectric memory and method of operating the same |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100400773B1 (en) * | 2001-06-29 | 2003-10-08 | 주식회사 하이닉스반도체 | Circuit for Testing Ferroelectric Capacitor in Ferroelectric Random Access Memy |
| WO2007091419A1 (en) * | 2006-02-07 | 2007-08-16 | Pioneer Corporation | Electrostatic capacity detection device |
-
2020
- 2020-12-03 CN CN202011395068.6A patent/CN112562777B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0415564A (en) * | 1990-05-08 | 1992-01-20 | Seiko Epson Corp | Capacitance measuring circuit |
| JP2005322889A (en) * | 2004-04-05 | 2005-11-17 | Fujitsu Ltd | Measuring method of ferroelectric capacitor and designing method of ferroelectric memory |
| CN111402939A (en) * | 2020-03-26 | 2020-07-10 | 珠海拍字节信息科技有限公司 | Ferroelectric memory and method of operating the same |
Also Published As
| Publication number | Publication date |
|---|---|
| CN112562777A (en) | 2021-03-26 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5682352A (en) | Digital testing of analog memory devices | |
| US8009484B2 (en) | Read circuit and read method | |
| US7286428B2 (en) | Offset compensated sensing for magnetic random access memory | |
| KR100525213B1 (en) | Method and circuit for evaluating the information content of a memory cell | |
| US20070121368A1 (en) | Programmable memory device circuit | |
| US9196380B2 (en) | Method for measuring data retention characteristic of resistive random access memory device | |
| JP2013036975A (en) | Detecting disconnected wire to connect battery cell and external circuit | |
| TW504833B (en) | Semiconductor memory and method for driving the same | |
| CN114121059A (en) | Sense amplifier and method of operation for non-volatile memory | |
| Barella et al. | LabOSat: Low cost measurement platform designed for hazardous environments | |
| WO2020068121A1 (en) | Charge metering circuit for memristor | |
| CN112562777B (en) | Capacitance measuring circuit and method thereof | |
| KR100845773B1 (en) | Circuit for Measuring Power-up Signal Trip Point of Semiconductor Memory Apparatus And Method of measuring Power-up Signal Trip Point Level Using The Same | |
| US6687173B2 (en) | Circuit for testing ferroelectric capacitor in FRAM | |
| WO2001001161A1 (en) | Ferroelectric film property measuring device, measuring method therefor and measuring method for semiconductor memory units | |
| JP2004515032A (en) | Magnetoresistive memory and reading method thereof | |
| JP3090329B2 (en) | Nonvolatile differential memory device and operation test method thereof | |
| CN114217156A (en) | Pulse voltage measurement method with adjustable ferroelectric domain motion speed | |
| US6791879B1 (en) | Structure and method for programmable and non-volatile analog signal storage for a precision voltage reference | |
| CN108693461B (en) | Calibration circuit and method for calibrating protection IC | |
| US7042783B2 (en) | Magnetic memory | |
| CN101943721B (en) | Method for fast measuring imprinting effect of ferroelectric film | |
| US20030227809A1 (en) | Temperature-adjusted pre-charged reference for an integrated circuit 1T/1C ferroelectric memory | |
| CN115598579B (en) | Vehicle-mounted domain control voltage sampling system and error compensation method and system thereof | |
| US8581595B2 (en) | Method of measuring flash memory cell current |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20230526 Address after: Room A302-H36, Feiyu Building, Software Park, No. 111-2 Linghu Avenue, Xinwu District, Wuxi City, Jiangsu Province, 214000 Applicant after: Wuxi Shunming Storage Technology Co.,Ltd. Address before: No.502, Jinbo block, Dongzhuang Power Electronic Science and Technology Park, No.8, Hongyi Road, Xinwu District, Wuxi City, Jiangsu Province, 214135 Applicant before: Wuxi paibyte Technology Co.,Ltd. |
|
| TA01 | Transfer of patent application right | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |