CN112562582B - Pixel circuit driving method, pixel circuit, display panel and display device - Google Patents

Pixel circuit driving method, pixel circuit, display panel and display device Download PDF

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Publication number
CN112562582B
CN112562582B CN202011640972.9A CN202011640972A CN112562582B CN 112562582 B CN112562582 B CN 112562582B CN 202011640972 A CN202011640972 A CN 202011640972A CN 112562582 B CN112562582 B CN 112562582B
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node
unit
transistor
driving
light
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CN112562582A (en
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翟应腾
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Hubei Changjiang New Display Industry Innovation Center Co Ltd
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Hubei Changjiang New Display Industry Innovation Center Co Ltd
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Control Of El Displays (AREA)

Abstract

The invention discloses a pixel circuit driving method, a pixel circuit, a display panel and a display device. The driving method comprises the steps that a data writing unit writes a data signal into a first node, and a resetting unit resets the potential of a second node to a reference voltage; the driving unit compensates the threshold voltage of the driving unit to the potential of the third node under the action of the data signal and the reference voltage; the second light-emitting control unit is communicated with the driving unit and the light-emitting element, the clamping unit cuts off a path between a fourth node and the second power supply voltage end, and the driving unit provides driving current for the light-emitting element so as to drive the light-emitting element to emit light; the clamping unit cuts off a path between the fourth node and the second power supply voltage terminal after the second light emission control unit communicates the driving unit and the light emitting element. The embodiment of the invention can avoid short circuit between the data signal and the reference voltage and prevent the driving current from being influenced by VDD.

Description

Pixel circuit driving method, pixel circuit, display panel and display device
Technical Field
The invention belongs to the technical field of display driving, and relates to a driving method of a pixel circuit, the pixel circuit, a display panel and a display device.
Background
The led display panel has advantages of high image quality, power saving, thin body, and wide application range, and is widely used in various consumer electronics products such as mobile phones, televisions, personal digital assistants, digital cameras, notebook computers, and desktop computers, and is the mainstream of the display panel. In the pixel circuit based on the transistor, the driving transistor serves as a core transistor to provide driving current for the light-emitting diode, so that each pixel point is lightened, and the luminous brightness of the pixel point is directly determined by the current. However, in the operation process of the pixel circuit, the threshold voltage of the driving transistor may drift due to the long-time operation of the transistor under the gate voltage, which affects the stability of the driving current. And all Sub-pixels (Sub-pixels) are supplied with voltage by external PVDD, and the actual PVDD obtained by the pixels at different positions has different sizes when the product is normally displayed due to factors such as the layout of the driving circuit, the wiring impedance of the PVDD and the like, so that the size of the driving current is influenced, and the uniformity of the display brightness is influenced.
Disclosure of Invention
Embodiments of the present invention provide a pixel circuit, a driving method, a display panel, and a display device, which can implement compensation of a threshold voltage of a driving transistor, make a driving current magnitude independent of a power supply voltage magnitude, and avoid a short circuit between a data signal and a reference voltage.
In a first aspect, an embodiment of the present invention provides a driving method of a pixel circuit, where the pixel circuit includes a data writing unit, a reset unit, a driving unit, a first light-emitting control unit, a second light-emitting control unit, a storage unit, a light-emitting element, and a clamping unit, the data writing unit is electrically connected between a data signal input terminal and a first node, the reset unit is electrically connected between a reference voltage input terminal and a second node, the driving unit is electrically connected between a first power voltage terminal and a third node, the first light-emitting control unit is electrically connected between the first node and the second node, the second light-emitting control unit is electrically connected between the third node and a fourth node, the light-emitting element is electrically connected between the fourth node and a second power voltage terminal, and the clamping unit is electrically connected between the fourth node and the second power voltage terminal, the storage unit is electrically connected between the first node and the third node;
the driving method includes:
in a data writing phase, the first light-emitting control unit cuts off the connection between the first node and the second node, the second light-emitting control unit communicates with a path between the third node and the fourth node, the data writing unit writes a data signal into the first node, and the resetting unit resets the potential of the second node to a reference voltage;
in a threshold voltage compensation phase, the first light emitting control unit cuts off the connection between the first node and the second node, the second light emitting control unit cuts off a path between the third node and the fourth node, and the driving unit compensates the threshold voltage of the driving unit into the potential of the third node under the action of the data signal and the reference voltage;
in a light emitting phase, the second light emitting control unit communicates the driving unit and the light emitting element, the clamping unit cuts off a path between the fourth node and the second power supply voltage end, and the driving unit supplies a driving current to the light emitting element to drive the light emitting element to emit light;
wherein the clamping unit cuts off a path between the fourth node and the second power supply voltage terminal after the second light emission control unit communicates the driving unit and the light emitting element.
In a second aspect, an embodiment of the present invention provides a pixel circuit, including:
a data writing unit electrically connected between a data signal input terminal and a first node, for providing a signal of the data signal input terminal to the first node in response to a signal of a first scan signal terminal;
a reset unit electrically connected between a reference voltage input terminal and a second node, for providing a signal of the reference voltage input terminal to the second node in response to a signal of the first scan signal terminal;
the driving unit is electrically connected between a first power supply voltage end and a third node and responds to the potential of the second node to provide driving current;
a first light emitting control unit electrically connected between the first node and the second node, and turning on a path between the first node and the second node in response to a signal of a first light emitting control signal terminal;
a second light-emitting control unit electrically connected between the third node and the fourth node, responding to a signal of a second light-emitting control signal terminal, and conducting a path between the third node and the fourth node;
a light emitting element electrically connected between the fourth node and a second power supply voltage terminal;
a clamping unit electrically connected between the fourth node and the second power voltage terminal, for providing a voltage of the second power voltage terminal to the fourth node in response to a signal of a second scan signal terminal;
a memory cell electrically connected between the first node and the third node;
wherein a voltage of the second power supply voltage terminal is higher than a voltage of the first power supply voltage terminal.
In a third aspect, embodiments of the present invention provide a display panel including the pixel circuit according to the second aspect of the present invention.
In a fourth aspect, embodiments of the present invention provide a display device comprising the display panel according to the third aspect of the present invention.
According to the pixel circuit driving method, the pixel circuit, the display panel and the display device, the threshold voltage of the driving transistor is compensated to the potential of the third node (the source electrode of the driving transistor), the gate voltage and the source voltage of the driving transistor both comprise PVDD, so that the driving current is independent of the power voltage, and the short circuit between the data signal and the reference voltage can be avoided. In addition, in the on-phase of the clamping unit, the voltage of the fourth node is clamped at PVDD, and the problem that the falling edge of the second light-emitting control unit arrives and the fourth node is pulled down, so that the black picture is stolen and brightened is solved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required to be used in the embodiments of the present invention will be briefly described below, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a circuit diagram of a pixel circuit;
FIG. 2 is a timing diagram of driving signals of the pixel circuit shown in FIG. 1;
fig. 3 is a schematic structural diagram of a pixel circuit according to an embodiment of the invention;
FIG. 4 is a circuit diagram of a pixel circuit according to an embodiment of the present invention;
fig. 5 is a timing diagram of driving signals of the pixel circuit shown in fig. 4.
Detailed Description
Features and exemplary embodiments of various aspects of the present invention will be described in detail below, and in order to make objects, technical solutions and advantages of the present invention more apparent, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting. It will be apparent to one skilled in the art that the present invention may be practiced without some of these specific details. It should be noted that the technical features of the embodiments provided in the present application may be combined with each other as needed. The following description of the embodiments is merely intended to provide a better understanding of the present invention by illustrating examples of the present invention.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
It will be understood that when a layer, region or layer is referred to as being "on" or "over" another layer, region or layer in describing the structure of the component, it can be directly on the other layer, region or layer or intervening layers or regions may also be present. Also, if the component is turned over, one layer or region may be "under" or "beneath" another layer or region.
A pixel circuit of the present invention will be described with reference to fig. 1 to 2 for better understanding.
Fig. 1 is a circuit diagram of a pixel circuit 100. Fig. 2 is a timing diagram of driving signals of the pixel circuit shown in fig. 1.
Referring to fig. 1, the pixel circuit 100 includes a data writing unit 161, a driving unit 162, a storage unit 163, a first light-emitting control unit 164, a second light-emitting control unit 165, a first resetting unit 166, and a second resetting unit 167.
The data writing unit 161 is coupled between a data signal terminal Vdata and a first node N1 for transmitting a data signal. The control terminal of the driving unit 162 is connected to the first node N1 for generating a driving current according to the data signal of the data writing unit 161. The storage unit 163 is also connected to the first node N1 for storing the data signal transmitted to the driving unit 162.
The first light emitting control unit 164 is connected between the driving unit 162 and the light emitting element 130. The second light-emission control unit 165 is connected between the first power source terminal PVDD and the driving unit 162.
The first reset unit 166 is connected to the first node N1, and the first reset unit 166 is configured to reset (i.e., initialize) the first node N1 during a reset phase.
The second reset unit 167 is connected to one input terminal of the third light emitting element 130, and the second reset unit 167 is configured to be able to reset the input terminal of the third light emitting element 130.
The third light emitting element 130 is an OLED light emitting element, and includes a first end and a second end opposite to each other, and in this embodiment, the first end of the third light emitting element 130 is taken as an anode end, and the second end is taken as a cathode end. A first end of the third light emitting element 130 is connected to the driving unit 162 via the first light emitting control unit 164, and a second end of the third light emitting element 130 is coupled to the second power source terminal PVEE.
In some alternative embodiments, the second reset unit 167 is connected to the second node N2 between the first light emitting control unit 164 and the third light emitting element 130, so that the first end of the third light emitting element 130 can be reset.
The first light emitting control unit 164 may include a first transistor M1, a gate of the first transistor M1 is connected to the light emitting signal terminal EMT for receiving and responding to the light emitting signal, a first pole of the first transistor M1 is connected to the driving unit 162, and a second pole of the first transistor M1 is connected to the third light emitting element 130.
The second light-emission control unit 165 may include a second transistor M2 having a gate connected to the light-emission signal terminal EMT for receiving and responding to the light-emission signal, a first electrode of the second transistor M2 connected to the first power terminal PVDD, and a second electrode of the second transistor M2 connected to the driving unit 162.
The driving unit 162 may include a third transistor M3, a gate of the third transistor M3 is connected to the first node N1, a first pole of the third transistor M3 is connected to the second light emission control unit 165, i.e., to the second pole of the second transistor M2, and a second pole of the third transistor M3 is connected to the first light emission control unit 164, i.e., to the first pole of the first transistor M1.
The storage unit 163 includes a storage capacitor Cst having a first electrode connected to the first power source terminal PVDD and a second electrode connected to the first node N1.
The first reset unit 166 may include a fourth transistor M4, a gate of the fourth transistor M4 is connected to the first scan signal terminal S1, a first pole of the fourth transistor M4 is connected to the reference voltage signal terminal Vref, and a second pole of the fourth transistor M4 is connected to the first node N1.
The data writing unit 161 may include a fifth transistor M5 and a sixth transistor M6, and a gate of the fifth transistor M5 and a gate of the sixth transistor M6 are connected to the second scan signal terminal S2. A first pole of the fifth transistor M5 is connected to the data signal terminal Vdate, a second pole of the fifth transistor M5 is connected to a third node N3 between the second light-emitting control unit 165 and the driving unit 162, and the third node N3 is located between the second transistor M2 and the third transistor M3. A first pole of the sixth transistor M6 is connected to a fourth node N4 between the first light emission control unit 164 and the driving unit 162, the fourth node N4 is located between the first transistor M1 and the third transistor M3, and a second pole of the sixth transistor M6 is connected to the first node N1.
The second reset unit 167 may include a seventh transistor M7, in this embodiment, a gate of the seventh transistor M7 is connected to the second scan signal terminal S2, a first terminal of the seventh transistor M7 is connected to the reference voltage signal terminal Vref, and a second terminal of the seventh transistor M7 is connected to the second node N2.
As shown in fig. 2, the first Scan signal terminal S1 provides the first Scan signal Scan1, the second Scan signal terminal S2 provides the second Scan signal Scan2, and the emission signal terminal EMT provides the emission signal Emit.
In the reset period t1, the first Scan signal Scan1 is a continuous on signal, the second Scan signal Scan2 and the emission signal Emit are turned off, and the fourth transistor M4 of the first reset unit 166 is turned on, so as to reset the first node N1. The seventh transistor M7 of the second reset unit 167 is turned on, thereby resetting the second node N2. The voltage level of the first node N1 is Vref, Vref is a low level signal, and the driving unit 162 is turned on.
In the data writing period t2, the second Scan signal Scan2 is a continuous on signal, and the first Scan signal Scan1 and the emission signal Emit are turned off. At this time, the fifth transistor M5 and the sixth transistor M6 are turned on, and the data signal of the data signal terminal Vdata is transmitted to the first node N1 through the fifth transistor M5, the third transistor M3 and the sixth transistor M6, and the data signal can be stored in the storage capacitor Cst. And is turned off when the gate potential of the driving unit 162 reaches Vdata + Vth (Vth is the threshold voltage of the third transistor M3), where the potential of the first node N1 is Vdata + Vth and the potential of the third node is Vdata
In the light emitting period t3, the first Scan signal Scan1 and the second Scan signal Scan2 are turned off, and the light emitting signal Emit is a continuous on signal, so that the first transistor M1 and the second transistor M2 are continuously turned on, and the first power source terminal PVDD and the driving unit 162, and the driving unit 162 and the light emitting element 130 are continuously turned on in the light emitting period, and the driving current drives the light emitting element to Emit light.
At this time, the third node potential becomes PVDD, and the driving TFT operates in the saturation region:
Ids＝(1/2)K(Vgs-Vth)2＝(1/2)K(Vdata+Vref-PVDD-Vth)2 ＝(1/2)K
(Vdata-PVDD)2where K is Cox μ W/L, a current flows through the light emitting element 130, where Ids is a current flowing through the OLED when the third transistor M3 is operated in a saturation region, μ is an electron mobility, Cox is a unit area capacitance of the MIS structure of the third transistor M3, and W/L represents a ratio of a channel width to a channel length of the device of the third transistor M3.
As described above, since the PVDD of the pixel circuit generates a voltage drop (IR drop), which causes the first power source terminal PVDD of the pixels at different positions to receive different power source voltages, and the magnitude of the driving current is affected by the magnitude of the power source voltage, the driving currents of the pixels at different positions are different, and the magnitude of the driving current is related to the luminance of the light emitting element, so that the PVDD voltage drop causes a luminance uniformity problem. And the source voltage of the first lighting control unit 164 (the first transistor M1) is too low for the PVEE + Voled, resulting in poor conduction capability and high power consumption.
The present invention provides a driving method of a pixel circuit, a display panel and a display device, so as to overcome the above problems.
Fig. 3 is a schematic structural diagram of a pixel circuit 200 according to an embodiment of the present invention.
Referring to fig. 3, a pixel circuit 200 according to an embodiment of the present invention includes a data writing unit 210, a resetting unit 220, a driving unit 230, a storage unit 240, a first light-emitting control unit 250, a second light-emitting control unit 260, a clamping unit 270, and a light-emitting device 280.
The Data writing unit 210 is electrically connected between a Data signal input terminal Data and the first node N1, and supplies a signal Vdata of the Data signal input terminal Data to the first node N1 in response to a signal of the first scan signal terminal 21. The reset unit 220 is connected between the reference voltage input terminal VREF and the second node, and provides the signal VREF of the reference voltage input terminal VREF to the second node N2 in response to the first scan signal of the first scan signal terminal S1. The driving unit 230 is electrically connected between the first power voltage terminal PVEE and the third node N3, and provides a driving current in response to the potential of the second node N2.
The first lighting control unit 250 is electrically connected between the first node N1 and the second node N2, and turns on a path between the first node N1 and the second node N2 in response to the first lighting control signal of the EM1 of the first lighting control signal terminal.
The second light-emitting control unit 260 is electrically connected between the third node N3 and the fourth node N4, and turns on a path between the third node N3 and the fourth node N4 in response to the second light-emitting control signal of the second light-emitting control signal terminal EM 2.
The light emitting element 280 is electrically connected between the fourth node N4 and the second power voltage terminal PVDD.
The clamping unit 270 is electrically connected between the fourth node N4 and the second power voltage terminal PVDD, and supplies a voltage of the second power voltage terminal PVDD to the fourth node N4 in response to the second scan signal of the second scan signal terminal S2.
The memory cell 240 is electrically connected between the first node N1 and the third node N3, and stores data to be written.
Wherein the potential of the second power voltage terminal PVDD is higher than the potential of the first power voltage terminal PVEE.
In the embodiment of the present invention, the compensation of the threshold voltage of the driving transistor is achieved by compensating the threshold voltage itself to the potential of the third node N3 (source of the driving transistor) by writing the data signal into the first node N1, transmitting the signal of the second power source terminal PVDD to the third node N3, and passing through under the action of the second node potential and the first node potential. In the light emitting period, since the memory cell 240 stores the voltage difference between the nodes N1 and N3 during the threshold voltage compensation period, when the signal of the second power source terminal PVDD is transmitted to the third node N3 again, the gate voltage (the potential of the second node N2) and the source voltage (the potential of the third node N3) of the driving unit both include PVDD, so that the driving current of the driving unit is independent of the magnitude of the power source voltage.
In addition, since the first light emission control unit and the second light emission control unit are controlled by different light emission signals, a short circuit between the data signal and the reference voltage can be avoided. In addition, in the on-phase of the clamping unit, the voltage of the fourth node N4 is clamped at PVDD, so as to avoid that the falling edge of the second light-emitting control unit arrives and the fourth node is pulled down, thereby causing the problem of the black picture being stolen.
Fig. 4 is a circuit diagram of a pixel circuit according to an embodiment of the invention.
Referring to fig. 4, a pixel circuit 200 according to an embodiment of the present invention includes a data writing unit 210, a resetting unit 220, a driving unit 230, a first light-emitting control unit 250, a second light-emitting control unit 260, a clamping unit 270, and a light-emitting device 280.
The Data writing unit 210 is electrically connected between a Data signal input terminal Data and the first node N1, and supplies a signal Vdata of the Data signal input terminal Data to the first node N1 in response to a signal of the first scan signal terminal 21. The data writing unit 210 may include a first transistor M1, and a gate of the first transistor M1 is connected to the first scan signal terminal S1 for receiving a first scan signal to control the first transistor M1 to be turned on or off. A first pole of the first transistor M1 is connected to the Data signal input terminal Data for receiving the Data signal Vdata. The second pole of the first transistor M1 is connected to the first node N1, i.e., to the memory unit 240 and the first light emitting control unit 250.
The reset unit 220 is connected between the reference voltage input terminal VREF and the second node, and provides the signal VREF of the reference voltage input terminal VREF to the second node N2 in response to the first scan signal of the first scan signal terminal S1. The reset unit 220 may include a second transistor M2. The gate of the second transistor M2 is connected to the first scan signal terminal S1 for receiving the first scan signal to control the second transistor M2 to turn on or off. A first pole of the second transistor M2 is connected to the second node N2, i.e., to the gate of the driving unit 230. The second pole of the second transistor M2 is connected to the reference voltage input VREF for receiving the reference voltage signal VREF.
The driving unit 230 is electrically connected between the first power voltage terminal PVEE and the third node N3, and provides a driving current in response to the potential of the second node N2. The first lighting control unit 250 is electrically connected between the first node N1 and the second node N2, and turns on a path between the first node N1 and the second node N2 in response to the first lighting control signal of the EM1 of the first lighting control signal terminal. The driving unit 230 may include a third transistor M3. The gate connection of the third transistor M3 is connected to the second node N2 for turning on or off under the control of the potential of the second node N2. The first electrode of the third transistor M3 is connected to the third node N3, that is, to the memory cell 240 and the second light emission control unit 260. The second pole of the third transistor M3 is connected to the first power supply voltage terminal PVEE.
The memory cell 240 is electrically connected between the first node N1 and the third node N3, and stores data to be written. The storage unit 240 may include a capacitor Cst.
The first lighting control unit 250 is electrically connected between the first node N1 and the second node N2, and turns on a path between the first node N1 and the second node N2 in response to the first lighting control signal of the EM1 of the first lighting control signal terminal. The first light emitting control unit 250 may include a fourth transistor M4. The gate of the fourth transistor M4 is connected to the first light-emitting control signal terminal EM1, and is configured to receive the first light-emitting control signal to control the fourth transistor M4 to turn on or off. A first pole of the fourth transistor M4 is connected to the first node N1, that is, to the data writing unit 210 and the memory unit 240. A second pole of the fourth transistor M4 is connected to the second node N2, i.e., to the reset unit 220 and the driving unit 230.
The second light-emitting control unit 260 is electrically connected between the third node N3 and the fourth node N4, and turns on a path between the third node N3 and the fourth node N4 in response to the second light-emitting control signal of the second light-emitting control signal terminal EM 2. The second light emission control unit 260 may include a fifth transistor M5. The gate of the fifth transistor M5 is connected to the second emission control signal terminal EM2 for receiving the second emission control signal to control the on or off of the fifth transistor M5. A first pole of the fifth transistor M5 is connected to the fourth node N4, and a second pole of the fifth transistor M5 is connected to the third node N3.
The clamping unit 270 is electrically connected between the fourth node N4 and the second power voltage terminal PVDD, and supplies a voltage of the second power voltage terminal PVDD to the fourth node N4 in response to the second scan signal of the second scan signal terminal S2. The clamping unit 270 includes a sixth transistor M6. The gate of the M6 of the sixth transistor is connected to the second scan signal terminal S2 for receiving the second scan signal to control the M6 of the sixth transistor to be turned on or off. A first pole of the sixth transistor M6 is connected to the second power voltage terminal PVDD, and a second pole of the sixth transistor M6 is connected to the fourth node N4. In the on-phase of the clamping unit 270, the voltage of the fourth node N4 is clamped at PVDD, so that the problem of the black frame being stolen due to the fourth node being pulled low when the falling edge of the second light-emitting control unit 260 arrives can be avoided.
The light emitting element 280 is electrically connected between the fourth node N4 and the second power voltage terminal PVDD. In the embodiment of the present invention, the voltage of the second power voltage terminal PVDD is higher than the voltage of the first power voltage terminal PVEE. The light emitting element 280 may include an Organic Light Emitting Diode (OLED) and an inorganic Light Emitting Diode (LED).
Fig. 5 is a timing diagram provided in accordance with an embodiment of the invention, involved in using the pixel circuit shown in fig. 4. In the embodiment of the present invention, the transistors are P-type transistors, and the transistors are turned on at a low level. It is understood that in some other embodiments, each transistor may be an N-type transistor, that is, each transistor is turned on at a high level, and the timing diagram corresponding to the transistor is opposite to the timing diagram of the embodiment in terms of the high and low levels of each signal at each stage.
In the embodiment of the present invention, the first Scan signal terminal S1 provides the first Scan signal Scan1, the second Scan signal terminal S2 provides the second Scan signal Scan2, the first emission signal terminal EM1 provides the first emission signal Emit1, and the second emission signal terminal EM2 provides the second emission signal Emit 2. The reference voltage Vref is a low level signal.
In the initialization stage T1, the first Scan signal Scan1 is at a high level, and the data writing unit 210(M1) and the reset unit 220(M2) are turned off. The second Scan signal Scan2 is at a low level, the clamp unit 270 is turned on, a path between the fourth node N4 and the second power voltage terminal PVDD is connected, the potential of the fourth node N4 is initialized to the voltage of the second power voltage terminal PVDD to turn off the light emitting element, and the memory cell 240 is precharged so that the potential of the 3 rd node becomes the voltage of the second power voltage terminal PVDD. The first light emission control signal Emit1 is at a low level, the first light emission control unit 250(M4) is turned on, and the potentials of the first node N1 and the second node N2 are the same. The second emission control signal Emit2 is at a low level, and the second emission control unit 260(M5) is turned on to transmit the potential (i.e., PVDD) of the fourth node N4 to the third node N3, thereby initializing the third node N3. In the initialization period T1, the potentials of the first node N1 and the second node N2 are the potentials of the last light-emitting period T6. The potentials of the third node N3 and the fourth node are PVDD.
In the data writing phase T2, the first Scan signal Scan1 is at a low level, the data writing unit 210(M1) and the reset unit 220(M2) are turned on, and the data writing unit 210 writes the data signal Vdata into the first node N1. The reset unit 220(M2) resets the potential of the second node N2 to the reference voltage Vref, and turns on the driving unit 230 (M3). When the second Scan signal Scan2 is at a low level, the clamp unit 270 is turned on to connect the path between the fourth node N4 and the second power voltage terminal PVDD, thereby clamping the potential of the fourth node N4 to the voltage of the second power voltage terminal PVDD. The first emission control signal Emit1 is at a high level, and the first emission control unit 250(M4) turns off, disconnecting the first node N1 from the second node N2. The second emission control signal Emit2 is at a low level, and the second emission control unit 260(M5) is turned on to communicate with a path between the third node N3 and the fourth node N4, and transmit the potential (i.e., PVDD) of the fourth node N4 to the third node N3. In the data writing phase T2, the potential Vdata of the first node N1 and the potential Vref of the second node N2 are set. The potentials of the third node N3 and the fourth node are PVDD.
In the threshold voltage compensation period T3, the first Scan signal Scan1 is at a low level, the data writing unit 210(M1) and the reset unit 220(M2) are turned on, and the data writing unit 210 transmits the data signal Vdata to the first node N1. The reset unit 220(M2) transmits the reference voltage Vref to the second node N2, and turns on the driving unit 230 (M3). When the second Scan signal Scan2 is at a low level, the clamp unit 270 is turned on to connect the path between the fourth node N4 and the second power voltage terminal PVDD, thereby clamping the potential of the fourth node N4 to the voltage of the second power voltage terminal PVDD. The first emission control signal Emit1 is at a high level, and the first emission control unit 250(M4) turns off, disconnecting the first node N1 from the second node N2. The second emission control signal Emit2 is at a high level, and the second emission control unit 260(M5) is turned off, cutting off a path between the third node N3 and the fourth node N4. Then, a current path (i.e., the capacitor CSt discharges) is formed between the Data signal terminal Data, the Data writing unit 210, the memory unit 240, the driving unit 230, and the first power supply voltage terminal PVEE. When the potential discharged to the third node N3 becomes Vref-Vth3, the driving unit 230(M3) is turned off. At this time, the potential Vdata of the first node N1 and the potential Vref of the second node N2 are set. The potential of the third node N3 is Vref-Vth3, and the potential of the fourth node is PVDD. Where Vth3 is the threshold voltage of the driving cell 230 (M3). That is, in the threshold voltage compensation period T3, the driving unit 230 compensates the threshold voltage Vth3 thereof into the potential of the third node N3 by the data signal Vdata and the reference voltage Vref.
T4 and T5 together form a driving stage in which the driving unit 230 generates a driving current by the voltages of the second node N2 and the fourth node N4, but since the second Scan signal Scan2 is at a low level, the clamping unit 270 is turned on, and a path between the fourth node N4 and the second power supply voltage terminal PVDD is connected, so that the potential of the fourth node N4 is clamped to the voltage of the second power supply voltage terminal PVDD. Therefore, the driving current does not flow through the light emitting element 280, so that the light emitting element 280 does not emit light.
In the first driving phase T4, the first Scan signal Scan1 is at a high level, and the data writing unit 210(M1) and the reset unit 220(M2) are turned off. The first emission control signal Emit1 is at a high level, and the first emission control unit 250(M4) turns off, disconnecting the first node N1 from the second node N2. The second emission control signal Emit2 is at a high level, and the second emission control unit 260(M5) is turned off, cutting off a path between the third node N3 and the fourth node N4. In the first driving period T4, the potential Vdata of the first node N1 and the potential Vref of the second node N2 are set. The potential of the third node N3 is Vref-Vth3, and the potential of the fourth node is PVDD, and remains unchanged. The first driving period T4 is a transition period for stabilizing the individual node voltage.
In the second driving period T5, the first emission control signal Emit1 is low level, the first emission control unit 250(M4) is turned on, and the potentials of the first node N1 and the second node N2 become the same. The second emission control signal Emit2 is at a low level, and the second emission control unit 260(M5) is turned on to transmit the potential (i.e., PVDD) of the fourth node N4 to the third node N3. At this time, since the potential of the third node N3 becomes PVDD, that is, the lower plate potential of the memory cell 240 (storage capacitor Cst) becomes PVDD, accordingly the upper plate potential of the memory cell 240 (storage capacitor Cst), that is, the potentials of the first node N1 and the second node N2 become Vdata-Vref + Vth3+ PVDD to be maintained. The voltage difference across the memory cell 240 (storage capacitor Cst) is consistent with the voltage difference Vdata-Vref + Vth3 during the threshold voltage compensation phase T3. At this time, the driving unit 230(M3) is turned on and operates in a saturation region, and the driving current is Ids ═ 1/2K (Vgs-Vth)2＝(1/2)K(Vdata-Vref+Vth3+PVDD-PVDD-Vth3)2 ＝(1/2)K(Vdata-Vref)2Where K is Cox μ W/L, where Ids is the current of the third transistor M3 operating in the saturation region, μ is the electron mobility, Cox is the capacitance per unit area of the third transistor M3MIS structure, and W/L represents the ratio of the channel width to the channel length of the third transistor M3 device.
In the light emitting period T6, the first Scan signal Scan1 is at a high level, and the data writing unit 210(M1) and the reset unit 220(M2) are turned off. The first emission control signal Emit1 is at a low level, the first emission control unit 250(M4) is turned on, and the potentials of the first node N1 and the second node N2 become the same. The second emission control signal Emit2 is at a low level, and the second emission control unit 260(M5) is turned on to transmit the potential (i.e., PVDD) of the fourth node N4 to the third node N3. The second Scan signal Scan2 is at a high level, the clamping unit 270 is turned off, and a path between the fourth node N4 and the second power supply voltage terminal PVDD is cut off. At this time, the potentials of the third node N3 and the fourth node N4 become PVDD-V1, where V1 is the voltage across the light emitting element 280 (D1). Drive current ds ═ and (d) flowing through the light-emitting element1/2)K(Vgs-Vth)2＝(1/2)K(Vdata-Vref+Vth3+PVDD-V1-(PVDD-V1)-Vth3)2 ＝(1/2)K(Vdata-Vref)2. As can be seen, the magnitude of the current flowing through the light emitting element 280 is related to the coefficient K, the data signal Vdata and the reference voltage Vref, and is not related to the second power voltage terminal PVDD. That is, the pixel circuit provided in the embodiment of the present invention has a driving current that is not affected by the voltage PVDD, that is, is not affected by the voltage drop of the PVDD. In addition, in the embodiment of the invention, in the light emitting period T6, the source voltage of the second light emitting control unit 260(M5) is PVDD-V1, which has strong on-state capability and low power consumption. In addition, only one conducting tube (M5) is arranged on the flow path of the driving current (PVDD-D1-M5-M3-PVEE), and compared with a circuit with two conducting tubes, which is similar to the circuit in the figure 1, the power consumption is lower.
Referring to fig. 4 and 5 again, in the embodiment of the invention, after the second light-emitting control unit 260 connects the driving unit 240 and the light-emitting element 280 (at the stage of T5), the clamping unit 270 cuts off the path between the fourth node N3 and the second power voltage terminal PVDD, so that the voltage of the fourth node is clamped at the PVDD at the conducting stage of the clamping unit 270, and therefore, the problem of the black frame being stolen due to the falling edge of the second light-emitting control unit 260 coming and the fourth node N4 being pulled low can be avoided. In other words, the rising edge of the second Scan signal Scan2 is located behind the falling edge of the second emission control signal Emit2 in one driving period in time sequence, so that the problem that the falling edge of the second emission control signal Emit2 arrives, the fourth node N4 is pulled down, and the light-emitting element 280 is stolen and is lighted by a black picture can be avoided.
Referring to fig. 4 and 5 again, in the embodiment of the invention, the first light-emitting control unit 250 and the second light-emitting control unit 260 use different light-emitting control signals, so that the Data writing unit 210, the reset unit 220, and the first light-emitting control unit 250 can be prevented from being turned on simultaneously in the Data writing phase T2 and the threshold voltage compensation phase T3 (if EM1 uses EM2, it may cause the Data writing unit 210, the reset unit 220, and the first light-emitting control unit 250 to be turned on simultaneously), which causes Data and Vref to be shorted, and thus the gate potential of the driving unit 230(M3) is unstable during the writing and compensation processes.
As described above, only the specific embodiments of the present invention are provided, and it can be clearly understood by those skilled in the art that, for convenience and brevity of description, the specific working processes of the system, the module and the unit described above may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again. It should be understood that the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive various equivalent modifications or substitutions within the technical scope of the present invention, and these modifications or substitutions should be covered within the scope of the present invention.

Claims (11)

1. A driving method of a pixel circuit includes a data writing unit, a reset unit, a driving unit, a first light emitting control unit, a second light emitting control unit, a storage unit, a light emitting element, and a clamping unit, the data writing unit is electrically connected between a data signal input terminal and a first node, the reset unit is electrically connected between a reference voltage input terminal and a second node, the driving unit is electrically connected between a first power voltage terminal and a third node, the first light emitting control unit is electrically connected between the first node and the second node, the second light emitting control unit is electrically connected between the third node and a fourth node, the light emitting element is electrically connected between the fourth node and a second power voltage terminal, the clamping unit is electrically connected between the fourth node and the second power voltage terminal, the storage unit is electrically connected between the first node and the third node;
the driving method includes:
in a data writing phase, the first light-emitting control unit cuts off the connection between the first node and the second node, the second light-emitting control unit communicates with a path between the third node and the fourth node, the data writing unit writes a data signal into the first node, and the resetting unit resets the potential of the second node to a reference voltage;
in a threshold voltage compensation phase, the first light emitting control unit cuts off the connection between the first node and the second node, the second light emitting control unit cuts off a path between the third node and the fourth node, and the driving unit compensates the threshold voltage of the driving unit into the potential of the third node under the action of the data signal and the reference voltage;
in a light emitting phase, the second light emitting control unit communicates the driving unit and the light emitting element, the clamping unit cuts off a path between the fourth node and the second power supply voltage end, and the driving unit supplies a driving current to the light emitting element to drive the light emitting element to emit light;
wherein the clamping unit cuts off a path between the fourth node and the second power supply voltage terminal after the second light emission control unit communicates the driving unit and the light emitting element.
2. The driving method according to claim 1, further comprising an initialization phase,
in an initialization stage, the second light-emitting control unit initializes the potential of the third node, and the clamping unit initializes the potential of the fourth node;
wherein the initialization phase precedes the data write phase.
3. The driving method according to claim 1 or 2, further comprising a driving phase,
in the driving phase, the driving unit generates the driving current under the action of the potentials of the second node and the fourth node.
4. The driving method according to claim 3, characterized in that the driving phases comprise a first driving phase and a second driving phase,
in the first driving phase, the first light emission control unit cuts off a path between the first node and the second node, and the second light emission control unit cuts off a path between the third node and the fourth node;
in the second driving phase, the first light emission control unit turns on a path between the first node and the second node, and the second light emission control unit turns on a path between the third node and the fourth node.
5. The driving method according to claim 3,
in the driving phase, the clamping unit conducts a path between the fourth node and the second power supply voltage terminal to clamp the potential of the fourth node at the voltage of the second power supply voltage terminal.
6. The driving method according to claim 1,
the data writing unit and the resetting unit are controlled by a first scanning signal, the first light-emitting control unit is controlled by the first light-emitting control signal, the second light-emitting control unit is controlled by a second light-emitting control signal, and the clamping unit is controlled by the second scanning signal.
7. The driving method according to claim 6, wherein a rising edge of the second scan signal is located after a falling edge of the second emission control signal in one driving period in timing.
8. A pixel circuit, comprising:
a data writing unit electrically connected between a data signal input terminal and a first node, for providing a signal of the data signal input terminal to the first node in response to a signal of a first scan signal terminal;
a reset unit electrically connected between a reference voltage input terminal and a second node, for providing a signal of the reference voltage input terminal to the second node in response to a signal of the first scan signal terminal;
the driving unit is electrically connected between a first power supply voltage end and a third node and responds to the potential of the second node to provide driving current;
a first light emitting control unit electrically connected between the first node and the second node, and turning on a path between the first node and the second node in response to a signal of a first light emitting control signal terminal;
a second light-emitting control unit electrically connected between the third node and the fourth node, responding to a signal of a second light-emitting control signal terminal, and conducting a path between the third node and the fourth node;
a light emitting element electrically connected between the fourth node and a second power supply voltage terminal;
a clamping unit electrically connected between the fourth node and the second power voltage terminal, for providing a voltage of the second power voltage terminal to the fourth node in response to a signal of a second scan signal terminal;
a memory cell electrically connected between the first node and the third node;
wherein a voltage of the second power supply voltage terminal is higher than a voltage of the first power supply voltage terminal.
9. The pixel circuit according to claim 8,
the data writing unit comprises a first transistor, a grid electrode of the first transistor is connected with the first scanning signal end, a first pole of the first transistor is connected with the data signal input end, and a second pole of the first transistor is connected with the first node;
the reset unit comprises a second transistor, a grid electrode of the second transistor is connected with the first scanning signal end, a first pole of the second transistor is connected with the second node, and a second pole of the second transistor is connected with the reference voltage input end;
the driving unit includes a third transistor, a gate of which is connected to the second node, a first pole of which is connected to the third node, and a second pole of which is connected to the first power supply voltage terminal;
the first light emitting control unit comprises a fourth transistor, a grid electrode of the fourth transistor is connected with the first light emitting control signal end, a first pole of the fourth transistor is connected with the first node, and a second pole of the fourth transistor is connected with the second node;
the second light-emitting control unit comprises a fifth transistor, a grid electrode of the fifth transistor is connected with the second light-emitting control signal end, a first pole of the fifth transistor is connected with the fourth node, and a second pole of the fifth transistor is connected with the third node;
the clamping unit comprises a sixth transistor, a grid electrode of the sixth transistor is connected with the second scanning signal end, a first pole of the sixth transistor is connected with the second power supply voltage end, and a second pole of the sixth transistor is connected with the fourth node.
10. A display panel comprising the pixel circuit according to claim 8 or 9.
11. A display device characterized by comprising the display panel according to claim 10.
CN202011640972.9A 2020-12-31 2020-12-31 Pixel circuit driving method, pixel circuit, display panel and display device Active CN112562582B (en)

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