CN112560377B - Simulation verification method and system based on combination of virtual platform and FPGA - Google Patents
Simulation verification method and system based on combination of virtual platform and FPGA Download PDFInfo
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Abstract
The invention discloses a simulation verification method and a system based on the combination of a virtual platform and an FPGA, wherein the method comprises the steps of constructing a first conversion model, receiving a simulation request of a host model based on TLM2.0 through the virtual platform, and converting the simulation request into a first data packet; constructing a FIFO transfer verification model according to a third party PCIe DMA method, and simulating a data receiving and transmitting channel; constructing a second conversion model, receiving a first data packet, analyzing according to a preset protocol, and sending an analysis result to an RTL design DUT according to an AHB/AXI protocol; and a simulation step, generating an executable file according to the host model and the second conversion model, storing the executable file in an upper computer for simulation, generating a burning file according to a third party PCIe DMA method, the first conversion model and the RTL design DUT, downloading the burning file to the FPGA, and operating the executable file by the upper computer to be connected with the FPGA for joint simulation. The invention greatly reduces the economic cost and the verification cost of the simulation and is convenient for users to flexibly optimize and modify according to actual demands.
Description
Technical Field
The invention relates to the technical field of simulation verification, in particular to a simulation verification method and system based on combination of a virtual platform and an FPGA.
Background
As the performance of SoC chips increases, the design scale increases, and the RTL simulation speed based on the conventional EDA tool cannot meet the project period requirement. At present, simulation is performed through cooperation of software and hardware, one of the methods is to perform pure software hybrid simulation by using EDA tools based on a functional model of a CPU/GPU/DSP and RTL design, but if the scale of the RTL design is large, the simulation speed is too slow and is often unacceptable. Another approach is to implement software and hardware co-simulation through a virtual platform and a hardware accelerator, but the use cost of the hardware accelerator of up to millions of dollars per year is not affordable to small and medium-sized chip companies.
Disclosure of Invention
The present invention aims to solve at least one of the technical problems existing in the prior art. Therefore, the invention provides a simulation verification method based on the combination of the virtual platform and the FPGA, which can reduce the economic cost of simulation verification and improve the simulation speed.
The invention also provides a simulation verification system based on the combination of the virtual platform and the FPGA, which is provided with the simulation verification method based on the combination of the virtual platform and the FPGA.
According to an embodiment of the first aspect of the invention, the simulation verification method based on the combination of the virtual platform and the FPGA comprises a verification step and a simulation step, wherein the verification step comprises the following steps: constructing a first conversion model, receiving a simulation request of a host model based on TLM2.0 through a virtual platform, converting the simulation request into a first data packet, and receiving simulation reply data to return to the host model, wherein the simulation request comprises register configuration and excitation data; constructing a FIFO transfer verification model according to a third party PCIe DMA method, and simulating a data receiving and transmitting channel; constructing a second conversion model, receiving the first data packet, analyzing according to a preset protocol, sending an analysis result to an RTL design DUT according to an AHB/AXI protocol, obtaining the corresponding simulation reply data, and packaging the simulation reply data based on the preset protocol; the host model, the first conversion model, the FIFO switching verification model, the second conversion model and the RTL design DUT are sequentially connected, and an EDA simulation platform is built for verification; and a simulation step, wherein executable files are generated according to the host model and the second conversion model and stored in an upper computer for simulation, and burning files are generated according to the third party PCIe DMA method, the first conversion model and the RTL design DUT and downloaded to an FPGA, and the upper computer runs the executable files and is connected with the FPGA for joint simulation.
The simulation verification method based on the combination of the virtual platform and the FPGA has at least the following beneficial effects: by converting the TLM2.0 into the corresponding RIFFA C++ interface, generating a first data packet according to the simulation request, analyzing the first data packet, sending the first data packet to the RTL design DUT according to the hardware protocol, and simulating, the economic cost and the verification cost of the simulation are greatly reduced, and the user can flexibly optimize and modify according to actual requirements.
A method for data interaction of the virtual platform with the host model according to some embodiments of the invention includes: the virtual platform is connected with a tlm_initiator_socket of the host model through a tlm_generation_payload class based on TLM2.0, receives the simulation request and converts the simulation request into the first data packet, wherein the tlm_generation_payload class corresponds to an AHB/AXI request; the virtual platform receives the simulation reply data through the RIFFA C++ API function, converts the simulation reply data into data loads of a tlm_genetic_payload class, and replies the data loads to the host model through a tlm_target_socket class.
According to some embodiments of the present invention, the first data packet includes a header portion and a payload portion, wherein the header portion includes a read-write type, a burst type, a host ID, and a number of trans, and the payload portion includes an address and a data length of each trans; the reply data is read-only data without a packet header.
According to some embodiments of the present invention, the FIFO transfer verification model pulls down chnl_rx_data_ren when the amount of transmission DATA reaches a preset FIFO transmission depth and the DATA transmission is not finished, marks that the channel is full, and pulls up chnl_rx_data_ren after waiting for the first delay count, so as to continue to transmit DATA.
According to some embodiments of the invention, the FIFO transfer verification model pulls down chnl_tx_data_ren when the received DATA amount reaches a predetermined FIFO reception depth and the DATA transmission is not finished, marks that the channel is full, and continues to receive DATA after waiting for the second delay count to pull up chnl_tx_data_ren.
According to a second aspect of the embodiment of the invention, a simulation verification system based on the combination of a virtual platform and an FPGA comprises: the first conversion module is used for receiving a simulation request of a host model based on TLM2.0 through the virtual platform, converting the simulation request into a first data packet, and receiving simulation reply data to return to the host model, wherein the simulation request comprises register configuration and excitation data; the FIFO transfer verification module is used for simulating a data channel to transmit and receive data based on a third party PCIe DMA method; the second conversion module is used for receiving the first data packet, analyzing according to a preset protocol, sending an analysis result to an RTL design DUT according to an AHB/AXI protocol, obtaining the corresponding simulation reply data, and packaging the simulation reply data based on the preset protocol; the verification processing module is used for sequentially connecting the host model, the first conversion module, the FIFO switching verification module, the second conversion module and the RTL design DUT, and constructing an EDA simulation platform for verification; the simulation management module is used for generating an executable file according to the host model and the first conversion module, storing the executable file in an upper computer for simulation, generating a burning file according to the third party PCIe DMA method, the second conversion module and the RTL design DUT, downloading the burning file to the FPGA, and running the executable file by the upper computer to perform joint simulation in connection with the FPGA.
The simulation verification system based on the combination of the virtual platform and the FPGA has at least the following beneficial effects: through converting TML2.0 into a corresponding RIFFA C++ interface, generating a first data packet according to a simulation request, analyzing the first data packet, and sending the first data packet to an RTL design DUT according to hardware to simulate, the economic cost and the verification cost of the simulation are greatly reduced, and the user can flexibly optimize and modify according to actual requirements.
According to some embodiments of the invention, the first conversion module comprises: the first communication module is used for generating a C++ thread which is communicated with the FPGA hardware, interacting with the FPGA hardware and receiving the simulation reply data; the first control module is used for judging whether the simulation reply data can be generated or not according to the simulation task of the host computer through the system thread, and waking up the first communication module according to the judgment result.
According to some embodiments of the invention, the FIFO transfer verification module simulates the data channel based on the RIFFA, comprising: a first state machine module, configured to control a data transmission timing of the data channel, including: if the data channel is in the IDLE state, pulling up the CHNL_RX signal and entering an RX_ACK state; if the DATA channel is in an RX_ACK state, CHNL_RX_ACK is pulled up, entering a SIM_DMI_ACCESS state, and entering a SEND_DATA state after random delay to SEND DATA; returning to the IDLE state after the data transmission is completed; a second state machine module, configured to control a data receiving timing of the data channel, including: if the data channel is in the IDLE state and CHNL_TX is high, pulling up the CHNL_TX_ACK signal and entering a TX_ACK state; pulling down CHNL_TX_ACK after entering a TX_ACK state, clearing received DATA resources, and entering a RECV_DATA state to receive DATA; and entering an IDLE state after the data is received.
According to some embodiments of the invention, the first state machine module further comprises: and the transmission busy simulation module is used for simulating a transmission DATA busy state, if the DATA channel is in a send_data state, detecting that the transmission DATA quantity reaches a preset FIFO transmission depth, and if the DATA transmission is not finished, pulling down CHNL_RX_DATA_REN and entering into the FIFO_FULL_CLEAN state, carrying out first delay counting, entering into the send_DATA state after the first delay counting is overtime, and pulling up CHNL_RX_DATA_REN to continuously transmit DATA.
According to some embodiments of the invention, the second state machine module further comprises: and the receiving busy simulation module is used for simulating a receiving DATA busy state, if the DATA channel is in the RECV_DATA state, detecting that the received DATA quantity reaches the preset FIFO receiving depth and the DATA transmission is not finished, pulling down CHNL_TX_DATA_REN and entering the FIFO_FULL_CLEAN state, carrying out second delay counting, entering the RECV_DATA state after the second delay counting is overtime, and pulling up CHNL_TX_DATA_REN to continuously receive DATA.
Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.
Drawings
The foregoing and/or additional aspects and advantages of the invention will become apparent and may be better understood from the following description of embodiments taken in conjunction with the accompanying drawings in which:
FIG. 1 is a flow chart of a method according to an embodiment of the invention;
FIG. 2 is a block schematic diagram of a system of an embodiment of the present invention;
FIG. 3 is a schematic diagram of simulation verification of a system building EDA of an embodiment of the present invention;
FIG. 4 is a schematic diagram of a simulation operation performed by the system according to an embodiment of the present invention;
FIG. 5 is a first state machine transition diagram in a system according to an embodiment of the present invention;
fig. 6 is a schematic diagram of a second state machine transition in the system according to an embodiment of the present invention.
Reference numerals:
the system comprises a first conversion module 100, a FIFO switching verification module 200, a second conversion module 300, a verification processing module 400 and a simulation management module 500;
a first communication module 110, a first control module 120;
a first state machine module 210, a send busy simulation module 211, a second state machine module 220, a receive busy simulation module 221.
Detailed Description
Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements or elements having like or similar functions throughout. The embodiments described below by referring to the drawings are illustrative only and are not to be construed as limiting the invention.
In the description of the present invention, a plurality means one or more, and a plurality means two or more, and it is understood that greater than, less than, exceeding, etc. does not include the present number, and it is understood that greater than, less than, within, etc. include the present number. The description of the first and second is for the purpose of distinguishing between technical features only and should not be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated or implicitly indicating the precedence of the technical features indicated.
Noun interpretation:
and (3) FPGA: programmable logic device, a semi-custom application specific integrated circuit.
GPU: a graphics processor.
CPU: and a central processing unit.
DSP: a digital signal processor.
NPU: a neural network processor.
EDA: the generic term for electronic design automation software.
PCIe: a high speed serial computer expansion bus standard.
RTL: register conversion stage circuitry, generally referred to as circuitry described in hardware description language.
DUT: the target device under test.
Referring to fig. 1, the method of the embodiment of the present invention includes a verification step and a simulation step, wherein the verification step includes: constructing a first conversion model, receiving a simulation request of a host model based on TLM2.0 through a virtual platform, converting the simulation request into a first data packet, and receiving simulation reply data to return to the host model, wherein the simulation request comprises register configuration and excitation data; constructing a FIFO transfer verification model according to a third party PCIe DMA method, and simulating a data receiving and transmitting channel; constructing a second conversion model, receiving a first data packet, analyzing according to a preset protocol, sending an analysis result to an RTL design DUT according to an AHB/AXI protocol, acquiring corresponding simulation reply data, and packaging the simulation reply data based on the preset protocol; sequentially connecting a host model, a first conversion model, a FIFO switching verification model, a second conversion model and an RTL design DUT, and constructing an EDA simulation platform for verification; and a simulation step, generating an executable file according to the host model and the first conversion model, storing the executable file in an upper computer for simulation, generating a burning file according to a third party PCIe DMA method, the second conversion model and the RTL design DUT, downloading the burning file to the FPGA, and running the executable file by the upper computer to be connected with the FPGA for joint simulation. The virtual platform is connected with a tlm_initiator_socket in the host model through a tlm_target_socket class based on TML2.0, receives a simulation request through a tlm_genetic_payload class, and converts the simulation request into a first data packet; each tlm_genetic_payload class corresponds to an AHB/AXI request; the first data packet includes: the header part comprises a read-write type, a burst type, a host ID and the number of the trans-ns (one trans corresponds to a request of an AHB/AXI protocol), and the address and the data length of each trans-ns of the load part. The virtual platform receives the reply data through the RIFFA C++ API function, converts the reply data into a data load of a tlm_generation_payload class, and replies the data to the host through a tlm_target_socket class; the emulation reply data does not include a header, but only data of a read-only payload portion. In the embodiment of the invention, the host model on the virtual platform can be an open source CPU model, a C++/SystemC model of a third party, or a host excitation model or a framework exploration model which is self-developed.
In the embodiment of the invention, taking RIFFA as a third party PCIe DMA as an example, a corresponding FIFO transfer verification model is constructed, a plurality of RIFFA data channels can be simulated to communicate with the FPGA, and each data channel comprises a data receiving FIFO interface and a data sending FIFO interface which are mutually independent; for a single DATA channel, when the transmission DATA amount reaches a preset FIFO transmission depth and the DATA transmission is not finished, pulling down CHNL_RX_DATA_REN, marking that the channel is full, and after waiting for a first delay count, pulling up CHNL_RX_DATA_REN to continue transmitting DATA; when the received DATA amount reaches the preset FIFO receiving depth and the DATA transmission is not finished, the chnl_tx_data_ren is pulled down, the mark channel is full, and after waiting for the second delay count, the chnl_tx_data_ren is pulled up to continue receiving DATA.
Referring to fig. 2, the system according to the embodiment of the present invention includes: the first conversion module 100 is configured to receive, through the virtual platform, a simulation request of the host model based on TLM2.0, convert the simulation request into a first data packet, and receive simulation reply data to return to the host model, where the simulation request includes register configuration and excitation data; the FIFO transfer verification module 200 is configured to simulate a data channel to perform data transceiving based on a third party PCIe DMA method; the second conversion module 300 is configured to receive the first data packet, parse the first data packet according to a preset protocol, send the parsed result to the RTL design DUT according to an AHB/AXI protocol hardware protocol, obtain corresponding simulation reply data, and package the simulation reply data based on the preset protocol; the verification processing module 400 is used for sequentially connecting the host model, the first conversion module 100, the FIFO switching verification module 200, the second conversion module 300 and the RTL design DUT, and constructing an EDA simulation platform for verification; the simulation management module 500 is configured to generate an executable file according to the host model and the first conversion module 100, store the executable file in an upper computer for simulation, generate a burn file according to a third party PCIe DMA method, the second conversion module 300 and an RTL design DUT, download the burn file to the FPGA, and run the executable file by the upper computer to connect with the FPGA for joint simulation.
In the embodiment of the invention, a packet protocol is constructed to exchange data between a virtual platform and an RTL design DUT of an FPGA, wherein the header of a first data packet sent by the virtual platform comprises a read-write type, a burst type, a host ID and the number of trans (one trans corresponds to a request of an AHB/AXI protocol), and the load part comprises: the address and data length of each trans. The simulation reply data returned by the FPGA does not comprise a packet header and only comprises loaded read-only data.
A first conversion module 100 for converting a TLM2.0 interface into a RIFFA c++ API function, referring to fig. 2, includes: the first communication module 110 is configured to generate a c++ thread that communicates with the FPGA hardware, interact with the FPGA hardware, and receive hardware reply data; the first control module 120 is configured to determine, according to a simulation task of the host, whether hardware reply data needs to be generated by using a system thread, and wake up the first communication module 110 according to a determination result. The system mc thread of the first control module 120 generates a c++ thread in the first communication module 110 in the scope of sc_start function call, and the thread is in a dormant state until the first control module 120 determines that hardware reply data needs to be acquired, the first control module 120 wakes up the first communication module 110, the first communication module 110 requests to receive the hardware reply data, and the communication is completed and enters into dormancy again. The first communication module 110 detects that the system C thread in the first control module 120 is finished and the c++ thread also exits. According to the embodiment of the invention, the system C model and two parts of functions communicated with FPGA hardware are combined together through mixed programming of the system C and C++ multithread, and compared with the common method of writing the two parts of functions into independent program sockets for communication, the simulation is simplified through reducing the complexity of function coordination; the speed of the system mc simulation is uncorrelated with the rate of the hardware communication part, reducing the probability that the system mc simulation is blocked.
The FIFO transfer verification module 200 may simulate several data channels corresponding to the pin level (pin level) model of the system c. Taking RFIFA as an example, the data transceiving function of the riffa_fifo can be obtained from a global static container through a global function with the same name and the same reference as the RIFFA API. By asserting the pin level signal, which is the same name as the hardware protocol, the FIFO transfer verification module can directly connect to and emulate an RTL IP (IO pin) with a RIFFA hardware protocol interface.
The FIFO switching verification module 200 completes communication with the FPGA through a first path and a second path, wherein the first path is used for sending data to the FPGA, and the second path is used for sending and receiving data from the FPGA; referring to fig. 2, the state machines of the first path and the second path are controlled by a first state machine module 210 and a second state machine module 220, respectively.
The state machine of the first path, referring to fig. 5, is as follows:
(1) in the IDLE state, entering the RX_ACK state after pulling up the CHNL_RX signal;
(2) in the RX_ACK state, if CHNL_RX_ACK is pulled high, entering a SIM_DMI_ACCESS state;
(3) simulating a random delay in the SIM_DMI_ACCESS state, and entering the SEND_DATA state to SEND DATA after overtime;
(4) in the send_data state, if the DATA transmission is completed, the IDLE state is entered.
In order to simulate that the inside of the RIFFA channel is busy during transmission, the embodiment of the present invention further detects the amount of transmission DATA by the transmission busy simulation module 211 in the send_data state at the state machine of the first path, and pulls down chnl_rx_data_ren to enter the fifo_full_clear state if the transmission DATA reaches the preset FIFO transmission DATA depth and the transmission is not finished, performs the first delay count, returns to the send_data state after timeout and pulls up chnl_rx_data_ren to continue transmitting DATA.
The state machine of the second path, referring to fig. 6, is as follows:
(1) if CHNL_TX is high in the IDLE state, pulling CHNL_TX_ACK high, and entering a TX_ACK state;
(2) after entering the tx_ack state, the chnl_tx_ack is pulled low, the received DATA resources are emptied, and the recv_data state is entered.
(3) The IDLE state is entered at the end of the transmission in the recv_data state.
In order to simulate the busy inside the RIFFA channel during transmission, the embodiment of the present invention further detects the received DATA amount by the receiving busy simulation module 221 in the recv_data state at the state machine of the second path, if the received DATA amount reaches the preset FIFO received DATA depth and the transmission is not finished, pulls down the chnl_tx_data_ren to enter the fifo_full_clear state, performs the second delay count, and returns to the recv_data state after timeout to pull up the chnl_tx_data_ren to continue receiving DATA.
In the system of the embodiment of the present invention, when simulation is applied, verification processing is performed first, taking one RIFFA of the third party pcie dma method as an example, in an EDA environment, referring to fig. 3, a simulation platform of pure EDA is built through the first conversion module 100, the FIFO transfer verification module 200, the second conversion module 300, the host model and the RTL design DUT (hardware design code); the FIFO transfer verification module 200 is an RFFIA FIFO transfer verification module corresponding to RFFIA, abbreviated as RFFIA FIFO module. At this time, the virtual platform side is responsible for sending the register configuration and excitation data to the first conversion module 100, where the first conversion module 100 packages the request into first data, and sends the first data to the second conversion module 300 on the FPGA side through the RFFIA FIFO module to perform protocol conversion (convert FIFO interface into AH/axirtl), unpacks the received first data packet, and sends the unpacked first data packet to the RTL design DUT according to the hardware protocol. The reply data of the RTL design DUT is packed in the second conversion module 300 and sent to the first conversion module 100 on the virtual platform side via the RFFIA FIFO module, and the reply data is returned to the host model by the first conversion module 100.
After the EDA simulation environment is verified, the next step of simulation operation comprises the following steps:
firstly, generating an executable file of OSCI (a standard, namely a program developed based on an acelera open source standard and C++ codes) through a host model and a second conversion module, and copying the executable file to an upper computer connected with an FPGA;
step two, connecting an RTL code of the RIFFA, an RTL design code and a PCIecontroller RTL code provided by an FPGA manufacturer, generating a bin file for burning the FPGA, and downloading the bin file to the FPGA;
and thirdly, running registers and storage space of RTL design codes on the python debug FPGA.
And fourthly, running the executable program of the OSCI and the FPGA to perform joint simulation. In the system during the simulation operation, referring to fig. 4, the virtual platform side is responsible for sending the register configuration and the excitation data to the first conversion module 100, and the first conversion module 100 packages the request into the first data according to the package, and sends the first data to the FPGA side. The FPGA side receives the first data packet through the RFFIA, performs protocol conversion through the second conversion module 300, unpacks the first data packet and sends the first data packet to the RTL design DUT according to the AHB/AXI protocol. The simulation reply data is packaged by the second conversion module 300 and then returned to the virtual platform side through the RFFIA.
Although specific embodiments are described herein, those of ordinary skill in the art will recognize that many other modifications or alternative embodiments are also within the scope of the present disclosure. For example, any of the functions and/or processing capabilities described in connection with a particular device or component may be performed by any other device or component. In addition, while various exemplary implementations and architectures have been described in terms of embodiments of the present disclosure, those of ordinary skill in the art will recognize that many other modifications to the exemplary implementations and architectures described herein are also within the scope of the present disclosure.
Certain aspects of the present disclosure are described above with reference to block diagrams and flowchart illustrations of systems, methods, systems and/or computer program products according to example embodiments. It will be understood that one or more blocks of the block diagrams and flowchart illustrations, and combinations of blocks in the block diagrams and flowchart illustrations, respectively, can be implemented by executing computer-executable program instructions. Also, some of the blocks in the block diagrams and flowcharts may not need to be performed in the order shown, or may not need to be performed in their entirety, according to some embodiments. In addition, additional components and/or operations beyond those shown in blocks of the block diagrams and flowcharts may be present in some embodiments.
Accordingly, blocks of the block diagrams and flowchart illustrations support combinations of means for performing the specified functions, combinations of elements or steps for performing the specified functions and program instruction means for performing the specified functions. It will also be understood that each block of the block diagrams and flowchart illustrations, and combinations of blocks in the block diagrams and flowchart illustrations, can be implemented by special purpose hardware-based computer systems that perform the specified functions, elements or steps, or combinations of special purpose hardware and computer instructions.
Program modules, applications, etc. described herein may include one or more software components including, for example, software objects, methods, data structures, etc. Each such software component may include computer-executable instructions that, in response to execution, cause at least a portion of the functions described herein (e.g., one or more operations of the exemplary methods described herein) to be performed.
The software components may be encoded in any of a variety of programming languages. An exemplary programming language may be a low-level programming language, such as an assembly language associated with a particular hardware architecture and/or operating system platform. Software components including assembly language instructions may need to be converted into executable machine code by an assembler prior to execution by a hardware architecture and/or platform. Another exemplary programming language may be a higher level programming language that may be portable across a variety of architectures. Software components, including higher-level programming languages, may need to be converted to an intermediate representation by an interpreter or compiler before execution. Other examples of programming languages include, but are not limited to, a macro language, a shell or command language, a job control language, a scripting language, a database query or search language, or a report writing language. In one or more exemplary embodiments, a software component containing instructions of one of the programming language examples described above may be executed directly by an operating system or other software component without first converting to another form.
The software components may be stored as files or other data storage constructs. Software components having similar types or related functionality may be stored together, such as in a particular directory, folder, or library. The software components may be static (e.g., preset or fixed) or dynamic (e.g., created or modified at execution time).
The embodiments of the present invention have been described in detail with reference to the accompanying drawings, but the present invention is not limited to the above embodiments, and various changes can be made within the knowledge of one of ordinary skill in the art without departing from the spirit of the present invention.
Claims (10)
1. The simulation verification method based on the combination of the virtual platform and the FPGA comprises a verification step and a simulation step, and is characterized in that,
the verification step comprises the following steps: constructing a first conversion model, receiving a simulation request of a host model based on TLM2.0 through a virtual platform, converting the simulation request into a first data packet, and receiving simulation reply data to return to the host model, wherein the simulation request comprises register configuration and excitation data; constructing a FIFO transfer verification model according to a third party PCIe DMA method, and simulating a data receiving and transmitting channel; constructing a second conversion model, receiving the first data packet, analyzing according to a preset protocol, sending an analysis result to an RTL design DUT according to an AHB/AXI protocol, obtaining the corresponding simulation reply data, and packaging the simulation reply data based on the preset protocol; the host model, the first conversion model, the FIFO switching verification model, the second conversion model and the RTL design DUT are sequentially connected, and an EDA simulation platform is built for verification;
and a simulation step, wherein an executable file is generated according to the host model and the first conversion model and stored in an upper computer for simulation, a burning file is generated according to the third party PCIe DMA method, the second conversion model and the RTL design DUT and is downloaded to an FPGA, and the upper computer runs the executable file and is connected with the FPGA for joint simulation.
2. The method for simulating verification based on combination of a virtual platform and an FPGA according to claim 1, wherein the method for data interaction of the virtual platform and the host model comprises:
the virtual platform is connected with a tlm_initiator_socket of the host model through a tlm_generation_payload class based on TLM2.0, receives the simulation request and converts the simulation request into the first data packet, wherein the tlm_generation_payload class corresponds to an AHB/AXI request;
the virtual platform receives the simulation reply data through the RIFFA C++ API function, converts the simulation reply data into data loads of a tlm_genetic_payload class, and replies the data loads to the host model through a tlm_target_socket class.
3. The virtual platform and FPGA joint-based simulation verification system according to claim 1, wherein the first data packet includes a header portion and a payload portion, wherein the header portion includes a read-write type, a burst type, a host ID, and a number of trans s, and the payload portion includes an address and a data length of each trans; the reply data is read-only data without a packet header.
4. The simulation verification system based on the combination of a virtual platform and an FPGA according to claim 1, wherein the FIFO transfer verification model pulls down chnl_rx_data_ren when the amount of transmission DATA reaches a preset FIFO transmission depth and the DATA transmission is not finished, marks that the channel is full, and pulls up chnl_rx_data_ren after waiting for the first delay count, and continues to transmit DATA.
5. The simulation verification system based on the combination of a virtual platform and an FPGA according to claim 1, wherein the FIFO transfer verification model pulls down chnl_tx_data_ren when the received DATA amount reaches a preset FIFO receiving depth and the DATA transmission is not finished, marks that the channel is full, and pulls up chnl_tx_data_ren after waiting for the second delay count to continue receiving DATA.
6. A simulation verification system based on the combination of a virtual platform and an FPGA is characterized by comprising:
the first conversion module is used for receiving a simulation request of a host model based on TLM2.0 through the virtual platform, converting the simulation request into a first data packet, and receiving simulation reply data to return to the host model, wherein the simulation request comprises register configuration and excitation data;
the FIFO transfer verification module is used for simulating a data channel to transmit and receive data based on a third party PCIe DMA method;
the second conversion module is used for receiving the first data packet, analyzing according to a preset protocol, sending an analysis result to an RTL design DUT according to an AHB/AXI protocol, obtaining the corresponding simulation reply data, and packaging the simulation reply data based on the preset protocol;
the verification processing module is used for sequentially connecting the host model, the first conversion module, the FIFO switching verification module, the second conversion module and the RTL design DUT, and constructing an EDA simulation platform for verification;
the simulation management module is used for generating an executable file according to the host model and the first conversion module, storing the executable file in an upper computer for simulation, generating a burning file according to the third party PCIe DMA method, the second conversion module and the RTL design DUT, downloading the burning file to the FPGA, and running the executable file by the upper computer to perform joint simulation in connection with the FPGA.
7. The virtual platform and FPGA joint-based simulation verification system of claim 6, wherein the first conversion module comprises:
the first communication module is used for generating a C++ thread which is communicated with the FPGA hardware, interacting with the FPGA hardware and receiving the simulation reply data;
the first control module is used for judging whether the simulation reply data can be generated or not according to the simulation task of the host computer through the system thread, and waking up the first communication module according to the judgment result.
8. The virtual platform and FPGA joint-based simulation verification system of claim 6, wherein the FIFO transfer verification module simulates the data channel based on a RIFFA, comprising:
a first state machine module, configured to control a data transmission timing of the data channel, including: if the data channel is in the IDLE state, pulling up the CHNL_RX signal and entering an RX_ACK state; if the DATA channel is in an RX_ACK state, CHNL_RX_ACK is pulled up, entering a SIM_DMI_ACCESS state, and entering a SEND_DATA state after random delay to SEND DATA; returning to the IDLE state after the data transmission is completed;
a second state machine module, configured to control a data receiving timing of the data channel, including: if the data channel is in the IDLE state and CHNL_TX is high, pulling up the CHNL_TX_ACK signal and entering a TX_ACK state; pulling down CHNL_TX_ACK after entering a TX_ACK state, clearing received DATA resources, and entering a RECV_DATA state to receive DATA; and entering an IDLE state after the data is received.
9. The virtual platform and FPGA joint-based simulation verification system of claim 8, wherein the first state machine module further comprises:
and the transmission busy simulation module is used for simulating a transmission DATA busy state, if the DATA channel is in a send_data state, detecting that the transmission DATA quantity reaches a preset FIFO transmission depth, and if the DATA transmission is not finished, pulling down CHNL_RX_DATA_REN and entering into the FIFO_FULL_CLEAN state, carrying out first delay counting, entering into the send_DATA state after the first delay counting is overtime, and pulling up CHNL_RX_DATA_REN to continuously transmit DATA.
10. The virtual platform and FPGA joint-based simulation verification system of claim 8, wherein the second state machine module further comprises:
and the receiving busy simulation module is used for simulating a receiving DATA busy state, if the DATA channel is in the RECV_DATA state, detecting that the received DATA quantity reaches the preset FIFO receiving depth and the DATA transmission is not finished, pulling down CHNL_TX_DATA_REN and entering the FIFO_FULL_CLEAN state, carrying out second delay counting, entering the RECV_DATA state after the second delay counting is overtime, and pulling up CHNL_TX_DATA_REN to continuously receive DATA.
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| CN114567627B (en) * | 2022-02-25 | 2024-01-26 | 山东云海国创云计算装备产业创新中心有限公司 | Simulation platform management method, system, equipment and medium |
| CN114584411B (en) * | 2022-02-25 | 2024-04-02 | 山东云海国创云计算装备产业创新中心有限公司 | PCIe multicast verification method and device, electronic equipment and storage medium |
| CN114896931B (en) * | 2022-05-12 | 2023-09-01 | 北京联盛德微电子有限责任公司 | Verification method and system for Bluetooth transceiving path based on handshake mechanism |
| CN115688676B (en) * | 2022-11-14 | 2023-06-16 | 沐曦集成电路(上海)有限公司 | TLM-based GPU joint simulation system |
| CN115496034B (en) * | 2022-11-14 | 2023-02-07 | 沐曦集成电路(上海)有限公司 | Multi-mode GPU joint simulation system |
| CN117009276B (en) * | 2023-06-27 | 2024-06-25 | 进迭时空(珠海)科技有限公司 | Method, device and system for signal compression transmission based on AXI bus |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1928877A (en) * | 2006-08-17 | 2007-03-14 | 电子科技大学 | Verification method for SOC software and hardware integration design |
| CN101499937A (en) * | 2009-03-16 | 2009-08-05 | 盛科网络（苏州）有限公司 | Software and hardware collaborative simulation verification system and method based on FPGA |
| CN110765715A (en) * | 2019-11-21 | 2020-02-07 | 中国航空工业集团公司西安航空计算技术研究所 | GPU chip-oriented rendering output unit performance simulation method and platform |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20110307847A1 (en) * | 2010-06-10 | 2011-12-15 | Global Unichip Corporation | Hybrid system combining TLM simulators and HW accelerators |
| KR20130081354A (en) * | 2012-01-09 | 2013-07-17 | 삼성전자주식회사 | Communication method in distributed parallel simulation |
-
2020
- 2020-12-11 CN CN202011441137.2A patent/CN112560377B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1928877A (en) * | 2006-08-17 | 2007-03-14 | 电子科技大学 | Verification method for SOC software and hardware integration design |
| CN101499937A (en) * | 2009-03-16 | 2009-08-05 | 盛科网络（苏州）有限公司 | Software and hardware collaborative simulation verification system and method based on FPGA |
| CN110765715A (en) * | 2019-11-21 | 2020-02-07 | 中国航空工业集团公司西安航空计算技术研究所 | GPU chip-oriented rendering output unit performance simulation method and platform |
Non-Patent Citations (2)
| Title |
|---|
| SOC验证平台的联合架构设计;汪洋;耿相铭;;信息技术;20130725(07);全文 * |
| 基于混合原型平台的UARTIP核设计与验证;赵新超;陈岚;冯燕;彭智聪;;电子技术应用;20151006(10);全文 * |
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