CN112558366A - Liquid crystal display panel and manufacturing method thereof - Google Patents
Liquid crystal display panel and manufacturing method thereof Download PDFInfo
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- CN112558366A CN112558366A CN202011441748.7A CN202011441748A CN112558366A CN 112558366 A CN112558366 A CN 112558366A CN 202011441748 A CN202011441748 A CN 202011441748A CN 112558366 A CN112558366 A CN 112558366A
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1345—Conductors connecting electrodes to cell terminals
- G02F1/13452—Conductors connecting driver circuitry and terminals of panels
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1345—Conductors connecting electrodes to cell terminals
- G02F1/13454—Drivers integrated on the active matrix substrate
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- Crystallography & Structural Chemistry (AREA)
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- Thin Film Transistor (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
The invention provides a liquid crystal display panel and its preparation method, the liquid crystal display panel has display area and gate drive circuit area located in display area periphery, the gate drive circuit includes the low level main line that multiple gate drive circuit units connect with multiple gate drive circuit units, there are low level branch lines in each gate drive circuit unit, and set up in both sides of low level branch line respectively and 2 pairs of parallel metal wires or 2 pairs of parallel transparent wires that set up at ordinary times; wherein the low-level branch line in each gate driving circuit unit is connected to the low-level main line through the contact hole. The invention reduces the risk of electrostatic shock damage to the photomask graph, achieves the purposes of high pixel PPI and high resolution display screen, and can avoid the problem of TFT channel short circuit caused by electrostatic shock, thereby improving the product yield and reducing the production cost.
Description
Technical Field
The invention relates to the technical field of display panels, in particular to a liquid crystal display panel and a manufacturing method thereof.
Background
The gate driving circuit is applied to the flat display screen of the thin film transistor, and the method is to utilize the process of carrying out the TFT process and simultaneously complete the gate driving circuit so as to replace a gate driving chip and achieve the purpose of reducing the manufacturing cost of the panel.
In practical applications, the gate driving circuit is completed by using a photomask and a designed circuit drawing through processes such as a thin film process, a photolithography process, an etching process, and the like. As shown in fig. 1(a) and 1(b), static electricity generated during the transportation of the mask 10 or due to the humidity change of the surrounding environment often damages the patterns of the source 10 and the drain 20 of the tft formed on the mask, and these belt-shaped traces 30 damaged by static electricity may cause the trenches 30 of the patterns of the source 10 and the drain 20 on the mask, as shown in fig. 2(a) and 2(b), which are the structural diagrams of the patterns of the source 10 and the drain 20 of the tft of a normal mask, the light transmittance of the pattern of the mask at the trenches 30 is reduced from 100% to 0%, so that the electrostatic damage traces 30 are not exposed enough during yellow light exposure, and then the photoresist remains after development; therefore, after the etching process, a short circuit between the source and the drain is directly formed, so that the thin film transistor switch fails, and finally, an abnormal display result is caused.
The gate driving circuit is formed by connecting a plurality of cells in series, taking a cell of 15T1C (15 thin film transistors (M1 to M15) and 1 capacitor C1) as an example, fig. 3 is an equivalent circuit of the gate driving circuit, the thin film transistors of the cells are pulled down to a low level line VSS, 11 thin film transistors are connected, M3, M4, M6, M7, M8, M9, M10, M11, M12, M13 and M15 are respectively arranged from left to right, the low level line VSS is a metal line with the largest area in the whole gate driving circuit, and the low level line VSS is formed with the source and the drain of the thin film transistors at the same time, so that electrostatic breakdown is easily caused.
Disclosure of Invention
The invention aims to provide a liquid crystal display panel and a manufacturing method thereof, which reduce the risk of damaging a photomask graph by electrostatic shock and achieve the purposes of a high-pixel PPI and high-resolution display screen.
The invention provides a liquid crystal display panel, which is provided with a display area and a grid drive circuit area positioned at the periphery of the display area, wherein the grid drive circuit comprises a plurality of grid drive circuit units and a low-level main line connected with the grid drive circuit units, and each grid drive circuit unit is internally provided with a low-level branch line and 2 pairs of parallel metal wires or 2 pairs of parallel transparent wires which are respectively arranged at two sides of the low-level branch line and are arranged at ordinary times; wherein the low-level branch line in each gate driving circuit unit is connected to the low-level main line through the contact hole.
The invention also provides a manufacturing method of the liquid crystal display panel, which comprises the following steps:
s1: depositing a first metal layer, etching the first metal layer by adopting a first photomask, and simultaneously forming a grid connected with a scanning line and a low-level main line positioned in a grid driving circuit when the scanning line is formed;
s2: depositing a gate insulating layer covering the first metal;
s3: depositing an active layer, and carrying out exposure and etching processes on the active layer by adopting a second photomask to form an island-shaped pattern;
s4: carrying out exposure and etching processes on the gate insulating layer by adopting a third photomask, and forming a first contact hole, a second contact hole, a third contact hole, a fourth contact hole and a fifth contact hole which are positioned on the low-level main line, wherein the first contact hole, the second contact hole, the third contact hole, the fourth contact hole and the fifth contact hole are sequentially arranged;
s5: depositing a second metal layer, etching the second metal layer by using a fourth photomask to form a data line, a source electrode, a drain electrode, a low-level branch line which is positioned in each gate drive circuit unit and is connected with the low-level main line through a third contact hole, a first connecting metal line which is connected with the low-level main line through the first contact hole and the second contact hole, and a second connecting metal line which is connected with the low-level main line through the fourth contact hole and the fifth contact hole, wherein the first connecting metal line is respectively provided with a first parallel metal line and a second parallel metal line in the first contact hole and the second contact hole, the second connecting metal line is respectively provided with a third parallel metal line and a fourth parallel metal line in the fourth contact hole and the fifth contact hole, the first parallel metal line and the second parallel metal line are arranged in parallel, and the third parallel metal line and the fourth parallel metal line are arranged in parallel.
The invention also provides a manufacturing method of the liquid crystal display panel, which comprises the following steps:
s1: depositing a first metal layer, etching the first metal layer by adopting a first photomask, and simultaneously forming a grid connected with a scanning line and a low-level main line positioned in a grid driving circuit when the scanning line is formed;
s2: depositing a gate insulating layer covering the first metal;
s3: depositing an active layer, and carrying out exposure and etching processes on the active layer by adopting a second photomask to form an island-shaped pattern;
s4: depositing a second metal layer, and etching the second metal layer by adopting a fourth photomask to form a data line, a source electrode, a drain electrode, a low-level branch line positioned in each gate drive circuit unit, and a first connecting metal line and a second connecting metal line positioned on two sides of the low-level branch line;
s5: depositing a first insulating layer covering the second metal layer;
s6: exposing and etching the first insulating layer and the grid insulating layer by using a fifth photomask, and forming a first contact hole, a second contact hole, a third contact hole, a fourth contact hole and a fifth contact hole which are positioned on the low-level main line; etching the first insulating layer by using a fifth photomask to form a first sub-contact hole and a second sub-contact hole which are positioned on the first connecting metal wire, a third sub-contact hole which is positioned on the low-level main wire, and a fourth sub-contact hole and a fifth sub-contact hole which are positioned on the second connecting metal wire, wherein the first contact hole, the second contact hole, the third contact hole, the fourth contact hole and the fifth contact hole are sequentially arranged;
s7: depositing a transparent conductive material layer, performing exposure and etching processes on the transparent conductive material layer by using a fifth photomask to form a pixel electrode, a first transparent electrode connected with the low-level main line and the first connecting metal line through the first contact hole and the first sub-contact hole, a second transparent electrode connected with the low-level main line and the first connecting metal line through the second contact hole and the second sub-contact hole, a third transparent electrode connected with the low-level main line and the low-level branch line through the third contact hole and the third sub-contact hole, a fourth transparent electrode connected with the low-level main line and the second connecting metal line through the fourth contact hole and the fourth sub-contact hole, and a fifth transparent electrode connected with the low-level main line and the second connecting metal line through the fifth contact hole and the fifth sub-contact hole, wherein the transparent conductive material layer forms a first parallel transparent line and a second parallel transparent line in the first contact hole and the second contact hole respectively, the transparent conductive material layer is provided with a third parallel transparent line and a fourth parallel transparent line in the fourth contact hole and the fifth contact hole respectively, the first parallel transparent line and the second parallel transparent line are arranged in parallel, and the third parallel transparent line and the fourth parallel transparent line are arranged in parallel.
The invention also provides a manufacturing method of the liquid crystal display panel, which comprises the following steps:
s1: depositing a first metal layer, etching the first metal layer by adopting a first photomask, and simultaneously forming a grid connected with a scanning line and a low-level main line positioned in a grid driving circuit when the scanning line is formed;
the first mask is a main line mask considering a low-level main line.
S2: depositing a gate insulating layer covering the first metal;
s3: depositing an active layer, and carrying out exposure and etching processes on the active layer by adopting a second photomask to form an island-shaped pattern;
s4: depositing a second metal layer, and etching the second metal layer by adopting a fourth photomask to form a data line, a source electrode, a drain electrode, a low-level branch line positioned in each gate drive circuit unit, and a first connecting metal line and a second connecting metal line positioned on two sides of the low-level branch line;
s5: depositing a first insulating layer covering the second metal layer;
s6: exposing and etching the transparent conductive material layer by adopting a fourth photomask to form a common electrode;
s7: depositing a second insulating layer covering the common electrode;
s8: exposing and etching the second insulating layer, the first insulating layer and the grid insulating layer by using a fifth photomask, and forming a first contact hole, a second contact hole, a third contact hole, a fourth contact hole and a fifth contact hole which are positioned on the low-level main line; etching the first insulating layer and the grid insulating layer by adopting a fifth photomask to form a first sub-contact hole and a second sub-contact hole which are positioned on the first connecting metal wire, a third sub-contact hole which is positioned on the low-level main wire and a fourth sub-contact hole and a fifth sub-contact hole which are positioned on the second connecting metal wire, wherein the first contact hole, the second contact hole, the third contact hole, the fourth contact hole and the fifth contact hole are sequentially arranged;
s9: depositing a transparent conductive material layer, performing exposure and etching processes on the transparent conductive material layer by using a fifth photomask to form a pixel electrode, a first transparent electrode connected with the low-level main line and the first connecting metal line through the first contact hole and the first sub-contact hole, a second transparent electrode connected with the low-level main line and the first connecting metal line through the second contact hole and the second sub-contact hole, a third transparent electrode connected with the low-level main line and the low-level branch line through the third contact hole and the third sub-contact hole, a fourth transparent electrode connected with the low-level main line and the second connecting metal line through the fourth contact hole and the fourth sub-contact hole, and a fifth transparent electrode connected with the low-level main line and the second connecting metal line through the fifth contact hole and the fifth sub-contact hole, wherein the transparent conductive material layer forms a first parallel transparent line and a second parallel transparent line in the first contact hole and the second contact hole respectively, the transparent conductive material layer is provided with a third parallel transparent line and a fourth parallel transparent line in the fourth contact hole and the fifth contact hole respectively, the first parallel transparent line and the second parallel transparent line are arranged in parallel, and the third parallel transparent line and the fourth parallel transparent line are arranged in parallel.
According to the invention, the low-level branch line and the low-level main line of each gate drive circuit unit are positioned at different layers, so that the low-level branch line of each gate drive circuit unit is connected with the low-level main line through the contact hole, the area is minimized, and the light cover is prevented from being greatly accumulated with static electricity; meanwhile, parallel metal wires or parallel transparent wires which are positioned at two sides of the low-level branch wires are arranged on the low-level main wire, so that the impedance of the low-level main wire is reduced; on the other hand, the low-level branch lines of the units of the gate drive circuit are independent from each other, so that the risk of electrostatic shock to the photomask graph is reduced under the requirement of increasing the scanning lines due to improvement of the resolution of the display screen, the purposes of high-pixel PPI and high-resolution display screen are achieved, the problem of TFT channel short circuit caused by electrostatic shock can be avoided, the product yield is improved, and the production cost is reduced.
Drawings
FIGS. 1(a) and 1(b) are schematic diagrams of electrostatic breakdown of a mask for patterning a source and a drain of a conventional TFT;
FIGS. 2(a) and 2(b) are schematic diagrams of a conventional mask for patterning a source and a drain of a TFT;
FIG. 3 is a diagram of a conventional gate driving circuit 15T 1C;
FIG. 4 is a schematic diagram of a single gate driving circuit unit of the LCD panel according to the present invention;
fig. 5 is a partial schematic view of a single gate driving circuit unit shown in fig. 4 in a contact hole.
Detailed Description
The present invention is further illustrated by the following figures and specific examples, which are to be understood as illustrative only and not as limiting the scope of the invention, which is to be given the full breadth of the appended claims and any and all equivalent modifications thereof which may occur to those skilled in the art upon reading the present specification.
For the sake of simplicity, the drawings only schematically show the parts relevant to the present invention, and they do not represent the actual structure as a product. In addition, in order to make the drawings concise and understandable, components having the same structure or function in some of the drawings are only schematically illustrated or only labeled. In this document, "one" means not only "only one" but also a case of "more than one".
As shown in fig. 4 and 5, the liquid crystal display panel of the present invention includes a display region and a gate driving circuit region located around the display region.
The liquid crystal display panel includes criss-cross scanning lines and data lines, a pixel region defined by intersections of the scanning lines and the data lines, a thin film transistor located at the intersections of the scanning lines and the data lines, a pixel electrode located in the pixel region, a gate insulating layer covering the scanning lines, a first insulating layer covering the data lines, and a pixel electrode.
As shown in fig. 5, the gate driving circuit includes a plurality of gate driving circuit units and a low-level main line 100 connected to the plurality of gate driving circuit units, and each gate driving circuit unit is provided therein with a low- level branch line 200 and 2 pairs of parallel metal lines disposed on both sides of the low-level branch line 200 and disposed at normal times. Wherein the low-level branch line 200 within each gate driving circuit unit is connected to the low-level main line 100 through a contact hole.
In order to reduce the electrostatic breakdown between the source and the drain, in this embodiment, at least two sets of the first connecting metal line 301 and the second connecting metal line 302, which are normally disposed, are added in each gate driving circuit unit, and the impedance of the low-level main line 100 is reduced by disposing 2 pairs of parallel metal lines in parallel.
The first embodiment:
a manufacturing method of a liquid crystal display panel comprises the following steps:
s1: depositing a first metal layer, etching the first metal layer by adopting a first photomask, and simultaneously forming a grid connected with a scanning line and a low-level main line 100 positioned in a grid driving circuit when the scanning line is formed;
the first mask is a main line mask considering a low-level main line.
S2: depositing a gate insulating layer 30 covering the first metal;
s3: depositing an active layer, and carrying out exposure and etching processes on the active layer by adopting a second photomask to form an island-shaped pattern;
s4: performing exposure and etching processes on the gate insulating layer by using a third photomask, and forming a first contact hole 101, a second contact hole 102, a third contact hole 103, a fourth contact hole 104 and a fifth contact hole 105 which are positioned on the low-level main line 100, wherein the first contact hole 101, the second contact hole 102, the third contact hole 103, the fourth contact hole 104 and the fifth contact hole 105 are sequentially arranged;
s5: depositing a second metal layer, etching the second metal layer by using a fourth photomask to form a data line, a source electrode, a drain electrode, a low-level branch line 200 located in each gate driving circuit unit and connected to the low-level main line 100 through a third contact hole 103, a first connecting metal line 30 connected to the low-level main line 100 through a first contact hole 101 and a second contact hole 105, and a second connecting metal line 302 connected to the low-level main line 100 through a fourth contact hole 104 and a fifth contact hole 105, wherein the first connecting metal line 301 is provided with a first parallel metal line 303 and a second parallel metal line 304 in the first contact hole 101 and the second contact hole 105, the second connecting metal line 302 is provided with a third parallel metal line 305 and a fourth parallel metal line 306 in the fourth contact hole 104 and the fifth contact hole 105, respectively, the first parallel metal line 303 and the second parallel metal line 304 are arranged in parallel, the third parallel metal line 305 and the fourth parallel metal line 306 are disposed in parallel.
The fourth photomask is a branch photomask which takes into account low-level branch lines and parallel metal lines, so that the branch photomask is integrated in the fourth photomask.
The low-level main line 100 is connected to an out-of-plane low-level signal VSS, the low-level branch lines 200 of the gate driving circuit units are connected through the low-level main line, parallel metal lines are disposed on both sides of the low-level branch lines 200 in parallel, and the impedance of the low-level main line is reduced by the parallel design of the parallel metal lines.
Wherein, the distance between the first connection metal line 301 and one side of the low-level branch line 200 is d1, and the distance between the second connection metal line 302 and one side of the low-level branch line 200 is d2, wherein d1 > 0um, and d2 > 0 um.
Second embodiment: the liquid crystal display panel adopts a VA mode.
A manufacturing method of a liquid crystal display panel comprises the following steps:
s1: depositing a first metal layer, etching the first metal layer by adopting a first photomask, and simultaneously forming a grid connected with a scanning line and a low-level main line positioned in a grid driving circuit when the scanning line is formed;
the first mask is a main line mask considering a low-level main line.
S2: depositing a gate insulating layer covering the first metal;
s3: depositing an active layer, and carrying out exposure and etching processes on the active layer by adopting a second photomask to form an island-shaped pattern;
s4: depositing a second metal layer, and etching the second metal layer by adopting a fourth photomask to form a data line, a source electrode, a drain electrode, a low-level branch line positioned in each gate drive circuit unit, and a first connecting metal line and a second connecting metal line positioned on two sides of the low-level branch line;
s5: depositing a first insulating layer covering the second metal layer;
s6: exposing and etching the first insulating layer and the grid insulating layer by using a fifth photomask, and forming a first contact hole, a second contact hole, a third contact hole, a fourth contact hole and a fifth contact hole which are positioned on the low-level main line; etching the first insulating layer by using a fifth photomask to form a first sub-contact hole and a second sub-contact hole which are positioned on the first connecting metal wire, a third sub-contact hole which is positioned on the low-level main wire, and a fourth sub-contact hole and a fifth sub-contact hole which are positioned on the second connecting metal wire, wherein the first contact hole, the second contact hole 102, the third contact hole 103, the fourth contact hole 104 and the fifth contact hole 105 are sequentially arranged;
s7: depositing a transparent conductive material layer, performing exposure and etching processes on the transparent conductive material layer by using a fifth photomask to form a pixel electrode, a first transparent electrode connected with the low-level main line and the first connecting metal line through the first contact hole and the first sub-contact hole, a second transparent electrode connected with the low-level main line and the first connecting metal line through the second contact hole and the second sub-contact hole, a third transparent electrode connected with the low-level main line and the low-level branch line through the third contact hole and the third sub-contact hole, a fourth transparent electrode connected with the low-level main line and the second connecting metal line through the fourth contact hole and the fourth sub-contact hole, and a fifth transparent electrode connected with the low-level main line and the second connecting metal line through the fifth contact hole and the fifth sub-contact hole, wherein the transparent conductive material layer forms a first parallel transparent line and a second parallel transparent line in the first contact hole and the second contact hole respectively, the transparent conductive material layer is provided with a third parallel transparent line and a fourth parallel transparent line in the fourth contact hole and the fifth contact hole respectively, the first parallel transparent line and the second parallel transparent line are arranged in parallel, and the third parallel transparent line and the fourth parallel transparent line are arranged in parallel.
The low-level signal VSS outside the low-level main line connecting surface is connected with the low-level branch lines of each gate drive circuit unit through the low-level main line, and meanwhile parallel transparent lines arranged in parallel are arranged on two sides of each low-level branch line, so that the impedance of the low-level main line is reduced through the parallel design of the parallel transparent lines.
Wherein, the distance between the first connecting metal wire and one side of the low-level branch line is d1, the distance between the second connecting metal wire and one side of the low-level branch line is d2, wherein d1 is more than 0um, and d2 is more than 0 um.
The third embodiment: the liquid crystal display panel adopts an FFS mode.
A manufacturing method of a liquid crystal display panel comprises the following steps:
s1: depositing a first metal layer, etching the first metal layer by adopting a first photomask, and simultaneously forming a grid connected with a scanning line and a low-level main line positioned in a grid driving circuit when the scanning line is formed;
the first mask is a main line mask considering a low-level main line.
S2: depositing a gate insulating layer covering the first metal;
s3: depositing an active layer, and carrying out exposure and etching processes on the active layer by adopting a second photomask to form an island-shaped pattern;
s4: depositing a second metal layer, and etching the second metal layer by adopting a fourth photomask to form a data line, a source electrode, a drain electrode, a low-level branch line positioned in each gate drive circuit unit, and a first connecting metal line and a second connecting metal line positioned on two sides of the low-level branch line;
s5: depositing a first insulating layer covering the second metal layer;
s6: exposing and etching the transparent conductive material layer by adopting a fourth photomask to form a common electrode;
s7: depositing a second insulating layer covering the common electrode;
s8: exposing and etching the second insulating layer, the first insulating layer and the grid insulating layer by using a fifth photomask, and forming a first contact hole, a second contact hole, a third contact hole, a fourth contact hole and a fifth contact hole which are positioned on the low-level main line; etching the first insulating layer and the gate insulating layer by using a fifth photomask to form a first sub-contact hole and a second sub-contact hole which are positioned on the first connecting metal wire, a third sub-contact hole which is positioned on the low-level main wire, and a fourth sub-contact hole and a fifth sub-contact hole which are positioned on the second connecting metal wire, wherein the first contact hole, the second contact hole 102, the third contact hole 103, the fourth contact hole 104 and the fifth contact hole 105 are sequentially arranged;
s9: depositing a transparent conductive material layer, performing exposure and etching processes on the transparent conductive material layer by using a fifth photomask to form a pixel electrode, a first transparent electrode connected with the low-level main line and the first connecting metal line through the first contact hole and the first sub-contact hole, a second transparent electrode connected with the low-level main line and the first connecting metal line through the second contact hole and the second sub-contact hole, a third transparent electrode connected with the low-level main line and the low-level branch line through the third contact hole and the third sub-contact hole, a fourth transparent electrode connected with the low-level main line and the second connecting metal line through the fourth contact hole and the fourth sub-contact hole, and a fifth transparent electrode connected with the low-level main line and the second connecting metal line through the fifth contact hole and the fifth sub-contact hole, wherein the transparent conductive material layer forms a first parallel transparent line and a second parallel transparent line in the first contact hole and the second contact hole respectively, the transparent conductive material layer is provided with a third parallel transparent line and a fourth parallel transparent line in the fourth contact hole and the fifth contact hole respectively, the first parallel transparent line and the second parallel transparent line are arranged in parallel, and the third parallel transparent line and the fourth parallel transparent line are arranged in parallel.
The low-level signal VSS outside the low-level main line connecting surface is connected with the low-level branch lines of each gate drive circuit unit through the low-level main line, and meanwhile parallel transparent lines arranged in parallel are arranged on two sides of each low-level branch line, so that the impedance of the low-level main line is reduced through the parallel design of the parallel transparent lines.
Wherein, the distance between the first connecting metal wire and one side of the low-level branch line is d1, the distance between the second connecting metal wire and one side of the low-level branch line is d2, wherein d1 is more than 0um, and d2 is more than 0 um.
According to the invention, the low-level branch line and the low-level main line of each gate drive circuit unit are positioned at different layers, so that the low-level branch line of each gate drive circuit unit is connected with the low-level main line through the contact hole, the area is minimized, and the light cover is prevented from being greatly accumulated with static electricity; meanwhile, parallel metal wires or parallel transparent wires which are positioned at two sides of the low-level branch wires are arranged on the low-level main wire, so that the impedance of the low-level main wire is reduced; on the other hand, the low-level branch lines of the units of the gate drive circuit are independent from each other, so that the risk of electrostatic shock to the photomask graph is reduced under the requirement of increasing the scanning lines due to improvement of the resolution of the display screen, the purposes of high-pixel PPI and high-resolution display screen are achieved, the problem of TFT channel short circuit caused by electrostatic shock can be avoided, the product yield is improved, and the production cost is reduced.
Although the preferred embodiments of the present invention have been described in detail, the present invention is not limited to the details of the foregoing embodiments, and various equivalent changes (such as number, shape, position, etc.) may be made to the technical solution of the present invention within the technical spirit of the present invention, and these equivalent changes are all within the protection scope of the present invention.
Claims (7)
1. A liquid crystal display panel is provided with a display area and a grid drive circuit area positioned at the periphery of the display area, and is characterized in that the grid drive circuit comprises a plurality of grid drive circuit units and a low-level main line connected with the grid drive circuit units, and each grid drive circuit unit is internally provided with a low-level branch line and 2 pairs of parallel metal wires or 2 pairs of parallel transparent wires which are respectively arranged at two sides of the low-level branch line and are arranged at ordinary times; wherein the low-level branch line in each gate driving circuit unit is connected to the low-level main line through the contact hole.
2. The liquid crystal display panel according to claim 1, wherein the 2 pairs of parallel metal lines or the 2 pairs of parallel transparent lines are connected to a low-level main line.
3. The liquid crystal display panel according to claim 1, wherein a first metal connecting line and a second metal connecting line are further disposed in each gate driving circuit unit and located at two sides of the low-level branch line, respectively, wherein one pair of parallel metal lines or one pair of parallel transparent lines are connected to the first metal connecting line, and the other pair of parallel metal lines or one pair of parallel transparent lines are connected to the second metal connecting line.
4. The liquid crystal display panel of claim 1, wherein the distance between the first connection metal line and the side of the low-level branch line is d1, and the distance between the second connection metal line and the side of the low-level branch line is d2, where d1 > 0um and d2 > 0 um.
5. A method for manufacturing a liquid crystal display panel is characterized by comprising the following steps:
s1: depositing a first metal layer, etching the first metal layer by adopting a first photomask, and simultaneously forming a grid connected with a scanning line and a low-level main line positioned in a grid driving circuit when the scanning line is formed;
s2: depositing a gate insulating layer covering the first metal;
s3: depositing an active layer, and carrying out exposure and etching processes on the active layer by adopting a second photomask to form an island-shaped pattern;
s4: carrying out exposure and etching processes on the gate insulating layer by adopting a third photomask, and forming a first contact hole, a second contact hole, a third contact hole, a fourth contact hole and a fifth contact hole which are positioned on the low-level main line, wherein the first contact hole, the second contact hole, the third contact hole, the fourth contact hole and the fifth contact hole are sequentially arranged;
s5: depositing a second metal layer, etching the second metal layer by using a fourth photomask to form a data line, a source electrode, a drain electrode, a low-level branch line which is positioned in each gate drive circuit unit and is connected with the low-level main line through a third contact hole, a first connecting metal line which is connected with the low-level main line through the first contact hole and the second contact hole, and a second connecting metal line which is connected with the low-level main line through the fourth contact hole and the fifth contact hole, wherein the first connecting metal line is respectively provided with a first parallel metal line and a second parallel metal line in the first contact hole and the second contact hole, the second connecting metal line is respectively provided with a third parallel metal line and a fourth parallel metal line in the fourth contact hole and the fifth contact hole, the first parallel metal line and the second parallel metal line are arranged in parallel, and the third parallel metal line and the fourth parallel metal line are arranged in parallel.
6. A method for manufacturing a liquid crystal display panel is characterized by comprising the following steps:
s1: depositing a first metal layer, etching the first metal layer by adopting a first photomask, and simultaneously forming a grid connected with a scanning line and a low-level main line positioned in a grid driving circuit when the scanning line is formed;
s2: depositing a gate insulating layer covering the first metal;
s3: depositing an active layer, and carrying out exposure and etching processes on the active layer by adopting a second photomask to form an island-shaped pattern;
s4: depositing a second metal layer, and etching the second metal layer by adopting a fourth photomask to form a data line, a source electrode, a drain electrode, a low-level branch line positioned in each gate drive circuit unit, and a first connecting metal line and a second connecting metal line positioned on two sides of the low-level branch line;
s5: depositing a first insulating layer covering the second metal layer;
s6: exposing and etching the first insulating layer and the grid insulating layer by using a fifth photomask, and forming a first contact hole, a second contact hole, a third contact hole, a fourth contact hole and a fifth contact hole which are positioned on the low-level main line; etching the first insulating layer by using a fifth photomask to form a first sub-contact hole and a second sub-contact hole which are positioned on the first connecting metal wire, a third sub-contact hole which is positioned on the low-level main wire, and a fourth sub-contact hole and a fifth sub-contact hole which are positioned on the second connecting metal wire, wherein the first contact hole, the second contact hole, the third contact hole, the fourth contact hole and the fifth contact hole are sequentially arranged;
s7: depositing a transparent conductive material layer, performing exposure and etching processes on the transparent conductive material layer by using a fifth photomask to form a pixel electrode, a first transparent electrode connected with the low-level main line and the first connecting metal line through the first contact hole and the first sub-contact hole, a second transparent electrode connected with the low-level main line and the first connecting metal line through the second contact hole and the second sub-contact hole, a third transparent electrode connected with the low-level main line and the low-level branch line through the third contact hole and the third sub-contact hole, a fourth transparent electrode connected with the low-level main line and the second connecting metal line through the fourth contact hole and the fourth sub-contact hole, and a fifth transparent electrode connected with the low-level main line and the second connecting metal line through the fifth contact hole and the fifth sub-contact hole, wherein the transparent conductive material layer forms a first parallel transparent line and a second parallel transparent line in the first contact hole and the second contact hole respectively, the transparent conductive material layer is provided with a third parallel transparent line and a fourth parallel transparent line in the fourth contact hole and the fifth contact hole respectively, the first parallel transparent line and the second parallel transparent line are arranged in parallel, and the third parallel transparent line and the fourth parallel transparent line are arranged in parallel.
7. A method for manufacturing a liquid crystal display panel is characterized by comprising the following steps:
s1: depositing a first metal layer, etching the first metal layer by adopting a first photomask, and simultaneously forming a grid connected with a scanning line and a low-level main line positioned in a grid driving circuit when the scanning line is formed;
the first mask is a main line mask considering a low-level main line.
S2: depositing a gate insulating layer covering the first metal;
s3: depositing an active layer, and carrying out exposure and etching processes on the active layer by adopting a second photomask to form an island-shaped pattern;
s4: depositing a second metal layer, and etching the second metal layer by adopting a fourth photomask to form a data line, a source electrode, a drain electrode, a low-level branch line positioned in each gate drive circuit unit, and a first connecting metal line and a second connecting metal line positioned on two sides of the low-level branch line;
s5: depositing a first insulating layer covering the second metal layer;
s6: exposing and etching the transparent conductive material layer by adopting a fourth photomask to form a common electrode;
s7: depositing a second insulating layer covering the common electrode;
s8: exposing and etching the second insulating layer, the first insulating layer and the grid insulating layer by using a fifth photomask, and forming a first contact hole, a second contact hole, a third contact hole, a fourth contact hole and a fifth contact hole which are positioned on the low-level main line; etching the first insulating layer and the grid insulating layer by adopting a fifth photomask to form a first sub-contact hole and a second sub-contact hole which are positioned on the first connecting metal wire, a third sub-contact hole which is positioned on the low-level main wire and a fourth sub-contact hole and a fifth sub-contact hole which are positioned on the second connecting metal wire, wherein the first contact hole, the second contact hole, the third contact hole, the fourth contact hole and the fifth contact hole are sequentially arranged;
s9: depositing a transparent conductive material layer, performing exposure and etching processes on the transparent conductive material layer by using a fifth photomask to form a pixel electrode, a first transparent electrode connected with the low-level main line and the first connecting metal line through the first contact hole and the first sub-contact hole, a second transparent electrode connected with the low-level main line and the first connecting metal line through the second contact hole and the second sub-contact hole, a third transparent electrode connected with the low-level main line and the low-level branch line through the third contact hole and the third sub-contact hole, a fourth transparent electrode connected with the low-level main line and the second connecting metal line through the fourth contact hole and the fourth sub-contact hole, and a fifth transparent electrode connected with the low-level main line and the second connecting metal line through the fifth contact hole and the fifth sub-contact hole, wherein the transparent conductive material layer forms a first parallel transparent line and a second parallel transparent line in the first contact hole and the second contact hole respectively, the transparent conductive material layer is provided with a third parallel transparent line and a fourth parallel transparent line in the fourth contact hole and the fifth contact hole respectively, the first parallel transparent line and the second parallel transparent line are arranged in parallel, and the third parallel transparent line and the fourth parallel transparent line are arranged in parallel.
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