CN112543064A - Clock recovery device and method for high-speed coherent optical communication system - Google Patents
Clock recovery device and method for high-speed coherent optical communication system Download PDFInfo
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- CN112543064A CN112543064A CN202011399990.2A CN202011399990A CN112543064A CN 112543064 A CN112543064 A CN 112543064A CN 202011399990 A CN202011399990 A CN 202011399990A CN 112543064 A CN112543064 A CN 112543064A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
- H04B10/60—Receivers
- H04B10/61—Coherent receivers
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
- H04B10/60—Receivers
- H04B10/61—Coherent receivers
- H04B10/616—Details of the electronic signal processing in coherent optical receivers
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0054—Detection of the synchronisation error by features other than the received signal transition
- H04L7/0058—Detection of the synchronisation error by features other than the received signal transition detection of error based on equalizer tap values
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0079—Receiver details
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Abstract
A clock recovery device and method used for high-speed coherent optical communication system, relate to the field of high-speed coherent optical communication system, in the receive end of the system, use ADC first digital signal output calculate the timing error first, carry on the preliminary recovery of the clock; and calculating a timing error by using a third digital signal output by the self-adaptive equalizer to perform fine recovery of a clock, so that the stability of clock synchronization of the coherent optical communication system is improved.
Description
Technical Field
The present invention relates to the field of high-speed coherent optical communication systems, and in particular, to a clock recovery apparatus and method for a high-speed coherent optical communication system.
Background
The Gardner timing synchronization algorithm is a feedback algorithm suitable for high-speed signals, only needs two sampling points per symbol, and the carrier phase error does not affect the timing performance of the algorithm.
For high-speed signals with the baud rate of more than 6G, the symbol period of the signals is short, and under the influence of various interferences, the symbol boundary is not clear enough, so that the performance of the Gardner algorithm is influenced, and the clock synchronization is unstable. At this time, the recovered clock frequency is near the target frequency, but the phase is unstable, so that the subsequent digital signal processing cannot work normally. For example, the first sampling point is data 1, the second is a changing edge, and the third is data 2, if the phase relationship is unstable, the sampling point may drift, so that the sampling points 1, 3 and 5 are aligned with data for a period of time, and the sampling points 2, 4 and 6 are aligned with data for the other end of time, so that the subsequent digital signal processing cannot work normally.
Disclosure of Invention
In view of the defects in the prior art, an object of the present invention is to provide a clock recovery apparatus and method for a high-speed coherent optical communication system, which can improve the stability of clock synchronization of the coherent optical communication system.
In order to achieve the above object, in one aspect, a clock recovery apparatus for a high-speed coherent optical communication system is provided at a receiving end, the clock recovery apparatus including:
an integrated coherent receiver ICR for receiving signal light and local oscillator light;
the analog-digital converter ADC is used for sampling the electric signal output by the ICR and outputting a first digital signal;
the self-adaptive equalizer is used for eliminating intersymbol interference of the first digital signal to obtain a second digital signal and simultaneously outputting a third digital signal;
the synchronization calculation module is used for judging whether the second digital signal is synchronous with the synchronization sequence or not through the correlation between the second digital signal and the synchronization sequence inserted by the transmitting end;
a timing error calculation module for calculating a timing error from the first digital signal when the second digital signal is not synchronized with the synchronization sequence; and further for calculating a timing error from the third digital signal after the second digital signal is synchronized with the synchronization sequence; and further for adjusting the VCO according to the timing error;
and the voltage-controlled oscillator VCO is used for providing a sampling clock for the ADC, so that the output clock signal is matched with the clock signal of the transmitting end.
Preferably, the clock recovery apparatus further includes:
the carrier recovery module is used for receiving the second digital signal and carrying out carrier recovery;
and the code element judging module is used for carrying out code element judgment on the signal output by the carrier recovery module to obtain a decoded signal.
Preferably, the sampling clock of the ADC is set to be twice the baud rate of the high-speed coherent optical communication system.
Preferably, the adaptive equalizer uses a transversal filter with N taps, and N is an odd number greater than 1.
Preferably, the second digital signal is:
wherein h isiAnd i is a tap serial number, i is a positive integer less than N, and N is a signal serial number.
Preferably, the third digital signal is:
wherein h isiAnd i is a tap serial number, i is a positive integer less than N, and N is a signal serial number.
Preferably, the timing error E2 is calculated by the third digital signalnThe method comprises the following steps:
E2n＝(S32n+1-S32n-1)*S32n。
preferably, the passing of the first numberSignal calculation timing error E1nThe method comprises the following steps:
E1n＝(S12n+2-S12n)*S12n+1
wherein n is a signal number.
On the other hand, a clock recovery method based on a clock recovery device of a high-speed coherent optical communication system is also provided, which comprises the following steps:
the ICR receives the signal light and the local oscillator light, the output electric signal is converted into a first digital signal through ADC sampling, and a timing error calculation module and a self-adaptive equalizer are respectively output;
the self-adaptive equalizer eliminates intersymbol interference of the first digital signal, outputs a second digital signal to the synchronous calculation module, and simultaneously outputs a third digital signal to the timing error calculation module;
the synchronization calculation module judges whether the second digital signal and the synchronization sequence inserted by the sending end are synchronous or not and informs the timing error calculation module;
the timing error calculation module calculates a timing error through the first digital signal when the second digital signal is asynchronous with the synchronous sequence; calculating a timing error from the third digital signal after the second digital signal is synchronized with the synchronization sequence;
and the timing error calculation module adjusts the VCO according to the timing error so that the clock signal output by the VCO is matched with the clock signal of the transmitting end.
Preferably, the timing error E2 is calculated from the third digital signalnThe method comprises the following steps:
E2n＝(S32n+1-S32n-1)*S32n
wherein n is a signal number according to:
wherein S3nFor the third digital signal, the adaptive equalizer uses a transversal filter with N taps, where N is an odd number greater than 1, hiFor the coefficients of the taps of the adaptive equalizer, i is the tap number, andi is a positive integer less than N.
The technical scheme has the following beneficial effects:
at the receiving end of the system, a first digital signal output by an ADC (Analog-to-digital converter) is adopted to calculate a timing error to perform initial recovery of a clock; and calculating a timing error by using a third digital signal output by the self-adaptive equalizer to perform fine recovery of a clock, so that the stability of clock synchronization of the coherent optical communication system is improved.
Drawings
Fig. 1 is a schematic diagram of a receiving end where a clock recovery apparatus for a high-speed coherent optical communication system according to an embodiment of the present invention is located;
fig. 2 is a schematic diagram of a clock recovery process according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention. In addition, the technical features involved in the embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.
As shown in fig. 1, an embodiment of a clock recovery apparatus for a high-speed coherent optical communication system is provided at a receiving end of the system. The clock recovery apparatus specifically includes: an ICR (Integrated Coherent Receiver), an ADC, an adaptive equalizer, a synchronization calculation module, a timing error calculation module, and a VCO (voltage-controlled oscillator). At the transmitting end of the high-speed coherent optical communication system, a synchronization sequence is periodically inserted into a signal; at the receiving end, as long as the signal output by the adaptive equalizer can be synchronized with the synchronous sequence, the clock can be indicated to be preliminarily recovered.
The ICR is used for receiving signal light and local oscillator light simultaneously and outputting an electric signal.
The ADC is used for sampling the electric signal output by the ICR and outputting a first digital signal.
The self-adaptive equalizer is used for receiving and eliminating intersymbol interference of the first digital signal to obtain a second digital signal, and is also used for simultaneously outputting a third digital signal.
And the synchronous calculation module is used for judging whether the second digital signal is synchronous with the synchronous sequence or not by judging whether the peak value exceeds a set threshold value or not through the correlation between the second digital signal and the synchronous sequence and outputting a judgment result.
And the timing error calculation module is used for calculating the timing error of the input signal of the module according to the Gardner algorithm and adjusting the VCO according to the timing error. The timing error calculation module receives the judgment result of the synchronous calculation module, and calculates the timing error through the first digital signal when the second digital signal is asynchronous with the synchronous sequence; and for calculating a timing error from the third digital signal after the second digital signal is synchronized with the synchronization sequence.
The VCO is used to provide a sampling clock to the ADC to match the output clock signal with the originating clock signal.
Preferably, the clock recovery apparatus may further include a carrier recovery module and a symbol decision module, where the carrier recovery module is configured to receive the second digital signal and perform carrier recovery to obtain a signal with compensated frequency and phase deviation; the code element judgment module is used for carrying out code element judgment on the signal output by the carrier recovery module to obtain a decoded SoutnAs an output of the overall system.
In the above embodiment, the sampling clock of the ADC is provided by the VCO, and needs to be set to be twice the baud rate of the high-speed coherent optical communication system.
The adaptive equalizer employs an N-tap transversal filter, and N is an odd number greater than 1. The second digital signal output by the adaptive equalizer is:
wherein h isiFor coefficients of taps of the adaptive equalizer, i is a tap number, and i is positive less than NInteger, n is signal sequence number, S2nIs the nth second digital signal.
Meanwhile, the third digital signal output by the adaptive equalizer is:
wherein, S2nIs the nth second digital signal.
When the second digital signal S2nCannot synchronize with the synchronization sequence, based on the first digital signal S1nThe timing error E1 is calculatedn：
E1n＝(S12n+2-S12n)*S12n+1
When the second digital signal S2nAfter synchronization with the synchronization sequence, the third digital signal S3 is usednThe timing error E2 is calculatedn：
E2n＝(S32n+1-S32n-1)*S32n
Wherein n is a signal number.
Based on the clock recovery apparatus of the above embodiment, an embodiment of a clock recovery method is provided, which includes the following steps:
the ICR receives the signal light and the local oscillator light, the output electric signal is converted into a first digital signal through ADC sampling, and a timing error calculation module and a self-adaptive equalizer are respectively output;
the self-adaptive equalizer eliminates intersymbol interference of the first digital signal, outputs a second digital signal to the synchronous calculation module, and simultaneously outputs a third digital signal to the timing error calculation module;
the synchronization calculation module judges whether the second digital signal and the synchronization sequence inserted by the sending end are synchronous or not and informs the timing error calculation module;
the timing error calculation module calculates a timing error through the first digital signal when the second digital signal is asynchronous with the synchronous sequence; calculating a timing error from the third digital signal after the second digital signal is synchronized with the synchronization sequence;
and the timing error calculation module adjusts the VCO according to the timing error so that the clock signal output by the VCO is matched with the clock signal of the transmitting end.
As shown in fig. 2, a clock recovery process includes the steps of:
s1, the timing error calculation module calculates the second digital signal S2nOut of synchronization with the synchronization sequence, by means of a first digital signal S1nThe timing error E1 is calculatednAccording to E1nThe VCO is adjusted.
S2, the synchronization calculation module judges the second digital signal S2nIf yes, go to S3; if not, the process proceeds to S1. Wherein the second digital signal S2nIs that the adaptive equalizer receives the first digital signal S1nAfter output, S1nThe ADC samples and outputs the electric signal output by the ICR.
S3, the timing error calculation module passes through the third digital signal S3nThe timing error E2 is calculatednAccording to E2nThe VCO is adjusted.
The present invention is not limited to the above embodiments, and any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention are included in the scope of the claims of the present invention which are filed as the application.
Claims (10)
1. A clock recovery device for a high-speed coherent optical communication system is provided at a receiving end, the clock recovery device comprising:
an integrated coherent receiver ICR for receiving signal light and local oscillator light;
the analog-digital converter ADC is used for sampling the electric signal output by the ICR and outputting a first digital signal;
the self-adaptive equalizer is used for eliminating intersymbol interference of the first digital signal to obtain a second digital signal and simultaneously outputting a third digital signal;
the synchronization calculation module is used for judging whether the second digital signal is synchronous with the synchronization sequence or not through the correlation between the second digital signal and the synchronization sequence inserted by the transmitting end;
a timing error calculation module for calculating a timing error from the first digital signal when the second digital signal is not synchronized with the synchronization sequence; and further for calculating a timing error from the third digital signal after the second digital signal is synchronized with the synchronization sequence; and further for adjusting the VCO according to the timing error;
and the voltage-controlled oscillator VCO is used for providing a sampling clock for the ADC, so that the output clock signal is matched with the clock signal of the transmitting end.
2. The clock recovery apparatus for a high speed coherent optical communication system according to claim 1, wherein the clock recovery apparatus further comprises:
the carrier recovery module is used for receiving the second digital signal and carrying out carrier recovery;
and the code element judging module is used for carrying out code element judgment on the signal output by the carrier recovery module to obtain a decoded signal.
3. The clock recovery apparatus for a high speed coherent optical communication system of claim 1, wherein the sampling clock of the ADC is set to be twice the baud rate of the high speed coherent optical communication system.
4. The clock recovery apparatus for a high-speed coherent optical communication system according to claim 1, wherein the adaptive equalizer employs a transversal filter of N taps, and N is an odd number greater than 1.
5. The clock recovery apparatus for a high speed coherent optical communication system of claim 4, wherein the second digital signal is:
wherein h isiFor the coefficients of the adaptive equalizer taps, i is decimationThe serial number of the head, i is a positive integer less than N, and N is the serial number of the signal.
6. The clock recovery apparatus for a high speed coherent optical communication system according to claim 4, wherein the third digital signal is:
wherein h isiAnd i is a tap serial number, i is a positive integer less than N, and N is a signal serial number.
7. The clock recovery apparatus for a high speed coherent optical communication system according to claim 6, wherein said calculating the timing error E2 from the third digital signalnThe method comprises the following steps:
E2n＝(S32n+1-S32n-1)*S32n。
8. the clock recovery apparatus for a high speed coherent optical communication system according to claim 4, wherein said calculating the timing error E1 from the first digital signalnThe method comprises the following steps:
E1n＝(S12n+2-S12n)*S12n+1
wherein n is a signal number.
9. A clock recovery method based on the clock recovery apparatus of the high-speed coherent optical communication system according to claim 1, comprising the steps of:
the ICR receives the signal light and the local oscillator light, the output electric signal is converted into a first digital signal through ADC sampling, and a timing error calculation module and a self-adaptive equalizer are respectively output;
the self-adaptive equalizer eliminates intersymbol interference of the first digital signal, outputs a second digital signal to the synchronous calculation module, and simultaneously outputs a third digital signal to the timing error calculation module;
the synchronization calculation module judges whether the second digital signal and the synchronization sequence inserted by the sending end are synchronous or not and informs the timing error calculation module;
the timing error calculation module calculates a timing error through the first digital signal when the second digital signal is asynchronous with the synchronous sequence; calculating a timing error from the third digital signal after the second digital signal is synchronized with the synchronization sequence;
and the timing error calculation module adjusts the VCO according to the timing error so that the clock signal output by the VCO is matched with the clock signal of the transmitting end.
10. The clock recovery method of claim 9, wherein the timing error E2 is calculated from the third digital signalnThe method comprises the following steps:
E2n＝(S32n+1-S32n-1)*S32n
wherein n is a signal number according to:
wherein S3nFor the third digital signal, the adaptive equalizer uses a transversal filter with N taps, where N is an odd number greater than 1, hiFor the coefficients of the adaptive equalizer taps, i is the tap number, and i is a positive integer less than N.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN115001645A (en) * | 2022-06-13 | 2022-09-02 | 北京邮电大学 | Clock recovery method and device, electronic equipment and computer storage medium |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102164031A (en) * | 2011-03-16 | 2011-08-24 | 华为技术有限公司 | Link clock recovery method and device |
| CN104170286A (en) * | 2012-03-19 | 2014-11-26 | 华为技术有限公司 | Method and apparatus of using joint timing recovery for a coherent optical system |
| CN109462421A (en) * | 2018-10-22 | 2019-03-12 | 北京睿信丰科技有限公司 | Signal timing recovery method and recovery device, signal demodulating method and demodulating system |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102164031A (en) * | 2011-03-16 | 2011-08-24 | 华为技术有限公司 | Link clock recovery method and device |
| CN104170286A (en) * | 2012-03-19 | 2014-11-26 | 华为技术有限公司 | Method and apparatus of using joint timing recovery for a coherent optical system |
| CN109462421A (en) * | 2018-10-22 | 2019-03-12 | 北京睿信丰科技有限公司 | Signal timing recovery method and recovery device, signal demodulating method and demodulating system |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115001645A (en) * | 2022-06-13 | 2022-09-02 | 北京邮电大学 | Clock recovery method and device, electronic equipment and computer storage medium |
| CN115001645B (en) * | 2022-06-13 | 2023-12-26 | 北京邮电大学 | Clock recovery method, clock recovery device, electronic equipment and computer storage medium |
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